Added common code for charger profile override for fast charging.
Fast charging configs can be defined in the respective board battery
file and use the common code for imposing the custom data.
BUG=chrome-os-partner:59393
BRANCH=none
TEST=Enabled the config on Reef. Manually overrode the temperature
and voltage. Observed correct charge profile config is selected
for each tests.
Change-Id: I075d271258470b98d38e4d5395d749469d3fd469
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/407928
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For oak, set a different list of task (no als, no accel) for compiling
revision 4 or less. Fix GPIO include issue.
BUG=chrome-os-partner:59423,chrome-os-partner:59084
TEST=compile for oak with board 4 and 5, tested on Reef.
BRANCH=kevin,reef
Change-Id: I09051a69cbad6d477a7b3bf9907f4c5c144b5136
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424220
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The CONFIG_FLASH_NVMEM option implements persistent, reliable storage
regions in flash. This adds CONFIG_FLASH_NVMEM_VARS, which uses one of
those storage regions for free-form variables.
Refer to the comments in include/nvmem_vars.h and common/nvmem_vars.c
for usage and implementation details.
BUG=chrome-os-partner:61107
BRANCH=none
TEST=make runtests
This CL includes a number of new tests, specifically for this feature.
No target boards use this feature yet so there's nothing to test on
actual hardware, but the test/nvmem_vars executable includes console
commands ("get", "set", "print") to try it out.
Change-Id: I8597415dc3b00a1462f5b164eeb5073129030525
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414194
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
After every reboot, we were resetting the write protect and console
lock states back to default. With this change the wp and lock states
will be preserved through deep sleep. They will still be reset on any
other type of reboot (like Power On reset or panic).
The states are also cleared if the system detects a rollback even when
booting from the deep sleep.
With this patch it is going to be impossible to remove hardware write
protection guarding writes into AP and EC firmware flash, unless the
cr50 console is unlocked.
Locking the console would reinstate hardware write protection
automatically even if it was disabled when the console was unlocked.
Two long life scratch register 1 bits are used to keep the console and
write protect states over resets. To make code cleaner bitmap
assignments of the long life scratch register is put in its own
include file.
BUG=chrome-os-partner:58961
BRANCH=none
TEST=manual
On prod/dev images verify that the default wp and console lock
states are still correct.
change the lock and write protect states from the default and
verify they are preserved through deep sleep.
reboot cr50 and make sure that they are reset.
unlock the console and enable flash writes, then set fallback
counter on cr50 to the value of 6 (rw 0x40000128 1; rw
0x4000012c 6) and put the AP into deep sleep by hitting
Alt-H-VolUp.
In five minutes press the power button on the device to bring
it back from s5. Observe cr50 fall back to an older image and
console lock and wp disabled.
Change-Id: Ie7e62cb0b2eda49b04a592ee1d0903e83246b045
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420812
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are plans to extend use of the LONG_LIFE_SCRATCH1 register for
other purposes than keeping board properties. Just as the board
properties, the new use is also very board specific. This patch moves
the board properties code from chip/g to board/cr50, where it belongs.
Instead of reading board properties bitmap and checking if various
bits are set, api functions are now provided to allow determining
various properties settings without actually looking at the properties
bitmap.
CQ-DEPEND=CL:*313057
BRANCH=none
BUG=chrome-os-partner:58961
TEST=verified that both Gru and Reef boot with the new image,
additionally, on Reef confirmed that it is possible to
communicate with the H1 over USB, and that plt_reset signal is
handled properly.
Change-Id: Id0dd2dc16389f773a149fb01eee1ce7bb99c4547
Reviewed-on: https://chromium-review.googlesource.com/422081
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
This adds a vendor command to invalidate the old rw. It should be used
when the tpm has been validated.
BUG=chrome-os-partner:55667
BRANCH=none
TEST=manual
run the vendor command
run 'ver' on the cr50 console and verify the inactive RW version
is Error
reboot cr50 10 times and make sure there is no rollback.
Change-Id: Ibec3dde77d6b1ab921e43613d54638b7318f3f57
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420407
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In some cases, the virtual battery code creates
transactions that violate SB spec.
One example:
If the host command is structured as two messages -
a write to 0x03 (reg addr), followed by two bytes of write data,
the first byte of the second message (write data) will be sent to
virtual_battery_read(), as if it were a reg read request.
Let's do the following change for virtual battery:
1. Parse the command more carefully with state machines.
2. Support write caching for some critical registers.
3. Cache more attributes (0x03 and 0x0f).
BUG=chrome-os-partner:59239, chromium:659819
BRANCH=none
TEST='power_supply_info' works on kevin
Change-Id: Icdeb12b21f0dc3c329f29b206b7b9395ca4c9998
Reviewed-on: https://chromium-review.googlesource.com/407987
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
During discovery, if adapter requests vconn power in the AMA flags,
make sure that we provide vconn.
This, for example, is necessary for the Apple HDMI adapter to work
on boot, when connected in S5. In that case, adapter does request
vconn swap, but we reject that as the system is off, and, therefore
5V supply is off. On boot, we send another discovery request, which
will detect this case and swap the power.
BRANCH=none
BUG=chromium:644663
TEST=On elm, S5. Plug adapter with power+HDMI. Switch on elm,
type "pd 0 vdm ident" in console, display works.
Change-Id: I55b6658c2bc0574b8427ae086f61daf03730a725
Reviewed-on: https://chromium-review.googlesource.com/415697
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rename the variable to actually tell us what it does (it sends a
Discover Identity command), instead of littering the code with
comments explaining why we set DATA_SWAPPED when the data roles
have not really been swapped.
BRANCH=none
BUG=chromium:644663
TEST=make buildall -j
Change-Id: Idbad38e48a55d6518ef82b32a4d96fee65264aae
Reviewed-on: https://chromium-review.googlesource.com/415696
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
* Include trng.h from trng.c before any other header to verify that the
header is self-contained.
* Add inclusion of stdint.h to trng.h to provide definition for uint32_t.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I78fb6d915c357236ca0fed2a57f093f0eec07fe9
Reviewed-on: https://chromium-review.googlesource.com/417424
Commit-Ready: Carl Hamilton <carlh@chromium.org>
Tested-by: Carl Hamilton <carlh@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Modified the SPI NOR flash driver to implement
and expose a read JEDEC ID command as well as
support block (64KiB) erase operations.
BUG=None
BRANCH=None
TEST=Built all targets. Tested on two different EEPROMs.
Before:
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0x1940ef
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 4m0.440s
user 0m6.674s
sys 0m11.998s
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0xc21a20c2
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 5m57.291s
user 0m9.964s
sys 0m18.363s
-------------------------------------------
After:
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0x1940ef
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 1m33.176s
user 0m2.327s
sys 0m5.050s
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0xc21a20c2
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 2m41.923s
user 0m4.191s
sys 0m8.576s
-------------------------------------------
Change-Id: Ic20372ca9966499977a52a700d6492d3f648d7b2
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/416903
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
gru has circuitrythat selects the charge LED color based on the
frequency of the PWM.
By adjusting the PWM frequency instead of just the duty, we gain more
control over the brightness of the charge LED.
BUG=chrome-os-partner:54155
BRANCH=gru
TEST=activate each LED in turn and confirm color and brightness
Change-Id: Ie653125a528595c1ec68aea4d02cb70595a1b151
Signed-off-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/415517
Reviewed-by: Shawn N <shawnn@chromium.org>
If battery is not present, input current is set to PD_MAX_CURRENT_MA.
If the input power set is greater than the maximum allowed system power,
system might get damaged. Hence, limit the input current to meet maximum
allowed input system power.
BUG=chrome-os-partner:58498
BRANCH=none
TEST=Manually tested on Reef. Removed the battery & using 'charger'
console command observed the following.
With Zinger charger at 20V - Input current is set to 2.25A
With Type-C & other chargers - Input current is set to 3A
Change-Id: Ife8686f322e095aa74b740a7c469bfe87107fb9a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/397865
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Upon requesting a PD power contract at a new voltage, keep the input
current limit at 500mA until PD_RDY is received.
BUG=b:30744563,chrome-os-partner:59311,chrome-os-partner:44340
BRANCH=ryu, gru, glados
TEST=Manual on kevin, set ilim to 5V through `chglim` console command,
attach zinger. Set ilim to 20V through `chglim`, verify that ilim goes
from 3A to 500mA to 3A.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I452f183cfb958780e336a9f99dc6398356de17a0
Reviewed-on: https://chromium-review.googlesource.com/399918
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When a WAIT is received in response to a request, wait SinkRequestTime
before resending the request.
BUG=chrome-os-partner:34984
TEST=make -j buildall
BRANCH=none
Change-Id: I5c8429c4a7b9cf06609996f924b8d9d535ab6b5f
Reviewed-on: https://chromium-review.googlesource.com/414533
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Common code is more flexible and supports more parts, so delete the
npcx-only register translation code.
BUG=chrome-os-partner:60029
BRANCH=gru
TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28
gets written to SR1, which matches our desired 'protect botton 128KB',
according to the datasheet. Also run 'flashrom -p ec --erase' then read
back EC SPI contents, verify ROM is erased except for first 128KB
region.
Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413228
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365)
Reviewed-on: https://chromium-review.googlesource.com/415498
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
On the bd9995*, back boosting may occur when actual battery voltage
drops below VBAT register setting. Maintain the VBAT register at the
battery-requested charge voltage even when not charging to ensure the
bd9995* doesn't become a back boosted animal.
BUG=chrome-os-partner:56139,chrome-os-partner:54248
BRANCH=gru
TEST=Manual on kevin, unplug AC, run 'charger', verify that 'V_batt' is
maintained at 8688 mV. Attach charger, verify 'V_batt' stays at 8688 mV
and device charges.
Change-Id: Ia0cc7f9279cb460e20a8faf332ad432067dc5482
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400087
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Enabling and disabling sleep in the rdd interrupt is redundant because
USB already takes care of that. When USB is initialized it will disable
sleep. If it is released or suspended then it will re-enable sleep. This
change removes the sleep enable and disable from the rdd interrupt. With
this change now sleep can be enabled while suzyq is still plugged in
using the command 'ccd disable'.
BUG=none
BRANCH=none
TEST=manual
The consoles still work
Updating the EC, AP and Cr50 still works
After running 'reboot ap-off' in the EC console and 'ccd
disable' in the Cr50 console Cr50 will go to sleep.
Change-Id: Ie8e6201e9fd611c514e93bc70d298d3b0d228611
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413606
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Let's make sure that both embedded and host side use the same command
definitions. To avoid host compilation problems move the definitions
into a separate file.
BRANCH=none
BUG=none
TEST=compilation still works.
Change-Id: Id0d85a51aebabed0637965b3b19d7ed42c46e75e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414945
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Cr50 updates in development environment should allow resetting the
device immediately after update (without the need for SYS_RST_L to be
toggled).
This patch adds a vendor command to do just that.
BRANCH=none
BUG=chrome-os-partner:60013. chrome-os-partner:60321
TEST=none yet, with the rest of the patches applied the target gets
rebooted immediately after a cr50 code update. Also, observed
that flashing the console does not quite work, opend
crosbug.com/p/60321 to address this.
Change-Id: Ia6f99ad6d22004347ad02aac2cbf4dd6c5594928
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414442
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This reverts commit c459c8278e
as the fix is not straightforwad, some host command codes in
private repos are expressed using C preprecessor which
breaks the assumption of this patch that all host commands
are expressed as four digit hex numbers.
Change-Id: I922de9ae8dbab6eef048463c5c09b1f338152083
Reviewed-on: https://chromium-review.googlesource.com/414492
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chrome-os-partner:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
100bca94 R __hcmds
100bca94 R __host_cmd_0x0000
100bcaa0 R __host_cmd_0x0001
100bcaac R __host_cmd_0x0002
100bcab8 R __host_cmd_0x0003
100bcac4 R __host_cmd_0x0004
100bcad0 R __host_cmd_0x0005
100bcadc R __host_cmd_0x0006
100bcae8 R __host_cmd_0x0007
100bcaf4 R __host_cmd_0x0008
100bcb00 R __host_cmd_0x0009
100bcb0c R __host_cmd_0x000a
100bcb18 R __host_cmd_0x000b
100bcb24 R __host_cmd_0x000d
100bcb30 R __host_cmd_0x0010
100bcb3c R __host_cmd_0x0011
100bcb48 R __host_cmd_0x0012
100bcb54 R __host_cmd_0x0013
100bcb60 R __host_cmd_0x0015
100bcb6c R __host_cmd_0x0016
100bcb78 R __host_cmd_0x0017
100bcb84 R __host_cmd_0x0025
100bcb90 R __host_cmd_0x0026
100bcb9c R __host_cmd_0x0029
100bcba8 R __host_cmd_0x002a
100bcbb4 R __host_cmd_0x002b
100bcbc0 R __host_cmd_0x002c
100bcbcc R __host_cmd_0x0044
100bcbd8 R __host_cmd_0x0045
100bcbe4 R __host_cmd_0x0046
100bcbf0 R __host_cmd_0x0047
100bcbfc R __host_cmd_0x0061
100bcc08 R __host_cmd_0x0062
100bcc14 R __host_cmd_0x0064
100bcc20 R __host_cmd_0x0065
100bcc2c R __host_cmd_0x0067
100bcc38 R __host_cmd_0x0087
100bcc44 R __host_cmd_0x008c
100bcc50 R __host_cmd_0x008d
100bcc5c R __host_cmd_0x008f
100bcc68 R __host_cmd_0x0092
100bcc74 R __host_cmd_0x0093
100bcc80 R __host_cmd_0x0096
100bcc8c R __host_cmd_0x0097
100bcc98 R __host_cmd_0x0098
100bcca4 R __host_cmd_0x0099
100bccb0 R __host_cmd_0x009e
100bccbc R __host_cmd_0x00a0
100bccc8 R __host_cmd_0x00a1
100bccd4 R __host_cmd_0x00a8
100bcce0 R __host_cmd_0x00a9
100bccec R __host_cmd_0x00b6
100bccf8 R __host_cmd_0x00b7
100bcd04 R __host_cmd_0x00d2
100bcd10 R __host_cmd_0x00d3
100bcd1c R __host_cmd_0x00db
100bcd28 R __host_cmd_0x0101
100bcd34 R __host_cmd_0x0102
100bcd40 R __host_cmd_0x0103
100bcd4c R __host_cmd_0x0104
100bcd58 R __host_cmd_0x0110
100bcd64 R __host_cmd_0x0111
100bcd70 R __host_cmd_0x0112
100bcd7c R __host_cmd_0x0113
100bcd88 R __host_cmd_0x0114
100bcd94 R __host_cmd_0x0115
100bcda0 R __host_cmd_0x0116
100bcdac R __host_cmd_0x0117
100bcdb8 R __host_cmd_0x0118
100bcdc4 R __host_cmd_0x011a
100bcdd0 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX
100bcdd0 R __hcmds_end
BRANCH=none
Change-Id: Ideb9951b318763f71915e2c4e5052f4b4bfab173
Reviewed-on: https://chromium-review.googlesource.com/405528
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This describes a 5-finger touchpad. The physical/logical dimensions
of the trackpad are hardcoded for the time being.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
Change-Id: I04a0833a28c013395974104ebdd6fcb29e5d6680
Reviewed-on: https://chromium-review.googlesource.com/407742
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This first cleans up the code:
- Define report as a structure.
- Fix USB interval from 40 ms to 32 ms (Linux kernel complains
otherwise).
Then, this removes the old set_keyboard_report interface, and
replaces it by the interface used by the keyboard scanner
(i.e. keyboard_state_changed and keyboard_clear_buffer).
This also means we need a keycode table to translate from
row/column to USB HID keycode.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make buildall -j
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
With evtest and "hid 0-7" in console, check that key are
reported correctly.
Change-Id: I5d526db1568c29c7f28fc5e962e213e44303cc16
Reviewed-on: https://chromium-review.googlesource.com/411571
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This returns the system information that is needed to determine the
correct signing keys for firmware updates.
BUG=chrome-os-partner:59747
BUG=chrome-os-partner:59705
BRANCH=none
TEST=make buildall; test on Reef
Run the "sysinfo" command on the Cr50 console:
> sysinfo
Reset flags: 0x00000800 (hard)
Chip: g cr50 B2
RO keyid: 0x3716ee6b(dev)
RW keyid: 0xb93d6539(dev)
DEV_ID: 0x017950ab 0x04656742
>
Send the raw command bytes from the Reef AP, observe the result:
# /tmp/trunks_send --raw 80 01 00 00 00 0C 20 00 00 00 00 12
80010000001C0000000000123716EE6BB93D6539017950AB04656742
#
The result contains the same information from the console command:
8001 TPM_ST_NO_SESSIONS
0000001C responseSize (28 bytes)
00000000 RC_SUCCESS
0012 vendor-specific subcommand
3716EE6B RO keyid
B93D6539 RW keyid
017950AB DEV_ID0
04656742 DEV_ID1
Change-Id: I82de3ebfb3e9be3b707583bc825d2efbcf851c5c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413106
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When the console is unlocked, the function nvmem_wipe_or_reboot()
is called. This holds the EC in reset, clears nvmem, resets the
TPM task, then releases the EC. Nothing about that should cause
the Cr50 to reboot, but it was happening anyway.
This CL addresses several subtle problems.
First, holding the EC in reset invoked the sys_rst_asserted()
interrupt handler, triggering extra (and early) calls to
tpm_reset(). That should wait until after nvmem is cleared, and
only be called once.
Second, the intentional call to tpm_reset() caused the current
(HOOKS) task to wait for the operation to finish, but it didn't
wait long enough (recreating the endorsement certs can take over
a second). When the task_wake_event() returned, a timeout was
indicated in addition to the completion event.
Third, because we checked for the timeout first, we reported an
error even though tpm_reset() completed successfully, just slower
than we expected. We didn't get the timeout event before it
completed because the TPM task runs at a higher priority.
This CL addresses all of these cases, and makes wiping nvmem the
responsibility of the TPM task as well, so that it can do it when it's
ready.
Note that the EC (and thus AP too) will be held in reset while nvmem is
erased.
BUG=chrome-os-partner:59902
BRANCH=none
TEST=make buildall, manual tests
From the Cr50 console, run the "lock on" and "lock off" commands.
Try it both with and without the battery present. Observe that
the Cr50 no longer reboots just because the console unlocks.
Change-Id: I65a342502718acc5b9bda8c6f28dcd27e8f027f7
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/411379
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Charger BGATE is off on POR hence the voltage to the battery pack is
not applied immediately from the VBUS. To overcome this issue, BGATE
is turned on (CHG_EN) at charger initialization. If the voltage across
VBATT is high but I2C is still failing, battery is booting from ship
mode hence overwrite the battery as not present till I2C on battery
is success and INIT bit is set.
BUG=chrome-os-partner:59308
BRANCH=none
TEST=Reef can boot to OS from shipmode battery.
Change-Id: If1b212612e27fd65a822675a9609f0a8c03d8add
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/411360
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
________ ________
SLP_S0 |______________________|
_____ ________
HC |___________________________|
BRANCH=none
BUG=chrome-os-partner:58740
TEST=Build/flash EC and check 'echo freeze > /sys/power/state'
command in OS shell. Verify idle state transitions during display off
and periodic wakes from S0ix do not lead to state transitions in EC.
Change-Id: Ie18c6c2ac8998f59141641567d1d740cd72c2d2e
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401072
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
In the future, we'd like to have different HID devices on different
endpoints (keyboard, trackpad, etc.), so we'd like to separate the
keyboard handling.
For other chip implementing usb_hid.c (namely, chip/g), we, for now
just rename the config option and endpoint/interface definitions.
Making the code more generic can be done at a later stage.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make buildall -j
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
Change-Id: Iad1b00fa226f7635c0f34aae6a435dc53a3ea555
Reviewed-on: https://chromium-review.googlesource.com/409256
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Some functions are only defined if CONFIG_HOSTCMD_EVENTS is set,
leading to link-time failures.
In particular, do not call these functions from keyboard_scan,
and do not define PD host event commands if the configuration
option is not set.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make buildall -j
Change-Id: I0da31cdec08f86f148aa883698a44f462de46d8e
Reviewed-on: https://chromium-review.googlesource.com/410923
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This add basics for acc and gyro sensor ST lsm6dsm
Still need to add interrupt management for embedded
functions and FIFO
BUG=none
BRANCH=master
TEST=Tested on discovery BOARD with sensor connected on
EC i2c master bus. Added motion sense task on discovery
board task list, added gpio info in board configuration
file and tested with motion sense console commands. Data
for acc/gyro seems ok, can successfully change ODR and
full scale range for acc and gyro.
Change-Id: Ie50c8c0ee366994ed97f7ff3252633893b813ac2
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/406947
Commit-Ready: mario tesi <mario.tesi@st.com>
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This allows custom TPM commands to be declared using the a
DECLARE_VENDOR_COMMAND macro instead of the original (and still
unchanged) DECLARE_EXTENSION_COMMAND macro.
The new commands are nearly identical, but they are encapsulated
using the vendor-specific protocols described in the TPMv2 spec.
Our original extensions use a non-standard command code, and
return a non-standard struct on completion, which can be
confusing to standard TPM drivers and tools.
Demonstrating the use of the new macros, this adds commands to
obtain the state of the Cr50 restricted console lock, or to set
the lock. There is intentionally no command to unlock the
console.
Note that this CL just adds the commands to the Cr50. We still
need to provide a nice userspace utility for the AP to use.
BUG=chrome-os-partner:58230
BUG=chrome-os-partner:57940
BRANCH=none
TEST=make buildall; load, boot, test, and update again on Reef
On Reef, I can use the trunks_send tool to send the raw TPM bytes
to invoke these commands:
Get the lock state:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000D00000000001000
The last byte 00 indicates that the lock is NOT set, so set it:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000C000000000011
Success. On the Cr50 console, I see it take effect:
[480.080444 The console is locked]
Query the state again:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000D00000000001001
and now the last byte 01 indicates that the console is locked.
And of course the existing extension commands still work as
before. In addition to uploading firmware, I can use the
usb_updater from my build machine to query the running firmware
version:
$ ./extra/usb_updater/usb_updater -f
open_device 18d1:5014
found interface 4 endpoint 5, chunk_len 64
READY
-------
start
Target running protocol version 5
Offsets: backup RO at 0x40000, backup RW at 0x4000
Keyids: RO 0x3716ee6b, RW 0xb93d6539
Current versions:
RO 0.0.10
RW 0.0.9
$
Change-Id: I7fb1d888bf808c2ef0b2b07c782e926063cc2cc4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409692
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890
BRANCH=none
TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption
Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/399882
Reviewed-by: David Hendricks <dhendrix@chromium.org>
These keys are much quicker to verify (259ms to 51ms on a -M0 at
48 Mhz), so they can be used when timing is critical and
verification needs to be performed on the board.
BRANCH=none
BUG=chromium:663631
TEST=make buildall -j && make run-rsa
TEST=make run-rsa3 (next commit)
Change-Id: I0da4b3e21543bb6f7b18e8b6ddc5e153046a61b8
Reviewed-on: https://chromium-review.googlesource.com/408006
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since we are out of host event bits, add a bit to indicate extended host
event exists. This is put in as a placeholder for now so that we don't
lose out the last available hostevent bit.
BUG=chrome-os-partner:59352
BRANCH=None
TEST=Compiles successfully
Change-Id: If35a246f3da511fde9f8c0bba419afb76a1a9827
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407804
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds new key combination (Left_Shift+Esc+Refresh+Power) that triggers
recovery mode by setting a new host event
EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT. This host event can be used
whenever user wants to request entry into recovery mode by
reinitializing all the hardware state (e.g. memory retraining).
BUG=chrome-os-partner:56643,chrome-os-partner:59352
BRANCH=None
TEST=Verified that device retrains memory in recovery mode
with (Left_Shift+Esc+Refresh+Power) on reef.
Change-Id: I2e08997acfd9e22270b8ce7a5b589cd5630645f8
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407827
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Simple API to set/get the tablet mode. It can be set via lid angle
calculation or if a board has a dedicated HAL sensor/GPIO.
Merged from glados branch, add MKBP switch support.
BUG=chromium:606718
BRANCH=gru
TEST=Check with Cave that both mode works.
Reviewed-on: https://chromium-review.googlesource.com/402089
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c940f36ceabcf2425284001298f03ebdb4c3079e)
Change-Id: I2ee5130f3e0a1307ec3ea543f7a32d66bc32b31d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404915
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Don't queue non-wake events, and ensure wake events (and all subsequent
events) always get queued.
BUG=chrome-os-partner:59248, chrome-os-partner:59336
BRANCH=gru
TEST=Manual on kevin, go to suspend, press volume keys dozens of times,
press 'shift', verify device wakes. Place cursor on URL bar, go to
suspend, type "google" quickly, verify device wakes and "google" appears
on URL bar. Go to suspend, press 'VolUp' key 5 times, press keyboard,
verify device wakes and no volume meter is seen on display.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibe761187fbcefd686776a512786550970a6fc067
Reviewed-on: https://chromium-review.googlesource.com/405717
Commit-Queue: Douglas Anderson <dianders@chromium.org>
Tested-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
(cherry picked from commit aa2f01566314604404e104d7975c6c755c22a601)
Reviewed-on: https://chromium-review.googlesource.com/407958
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
