RO does not need touchpad/keyboard driver or I2C passthru, RW does
not need RW verification, let's shrink both images by only including
required config options.
BRANCH=none
BUG=b:35582031
TEST=Build and flash hammer: still functional.
build/hammer/RO/ec.RO.flat shrank by 10144 bytes: (45868 to 35724)
build/hammer/RW/ec.RW.flat shrank by 2764 bytes: (45332 to 42568)
Change-Id: Iff0feb4e8446cc9f2e32103cd383fddae3234fec
Reviewed-on: https://chromium-review.googlesource.com/479492
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds new macros for tasks (_RO and _RW), which allows to
enable a task only for RO or RW section.
We also create a new task_filter.h include file, that helps
pre-filter those tasks, and can be used either from Makefile,
or included from task_id.h.
BRANCH=none
BUG=b:35582031
TEST=make buildall -j; make savesizes
Apply this CL
make buildall -j; make newsizes => No size change
Change-Id: I472bc6d4ab250a0a0e1fa6aeb4b748ba6968bedf
Reviewed-on: https://chromium-review.googlesource.com/479491
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nick Sanders <nsanders@google.com>
To configure 1 MHz speed when the APB clock is 15 MHz, the firmware
currently sets the SCLHT register to 4. However, we found out that
writing 4 to this register (and to SCLLT register) is illegal and
results in unexpected results. So there is a need to write 5 in that
case. However, this means that the actual i2c frequency will be 750 KHz.
To get a higher i2c clock frequency, there is a need to run with a
higher APB clock (and a higher core clock). For example, with APB set to
20 MHz, the i2c clock frequency is 833 KHz.
In this CL, the i2c freq setting for APB clock=20 MHz is also added which
may be used for NPCX7 in the future.
BRANCH=none
BUG=chromium:714314
TEST=No build error for make buildall(except gru). Use scope to capture
SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz.
Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/484202
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
These are options for features can be implemented if they are required.
BRANCH=none
BUG=none
TEST=build 'it83xx_evb' board with pd modules.
Change-Id: I1afb7d9c2d764728a375563a6739544032394c54
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/483319
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This timeout is described in SMBus specification (25ms).
Some I2C devices may required longer clock stretch
(The I2C specification does not specify any timeout conditions
for clock stretching).
So we increase this timeout to maximum.
NOTE:
Because this codebase already handle timeout of an I2C transfer,
so maybe we can disable this mechanism.
But we don't have any register to execute this,
so we maximize the timeout.
BRANCH=none
BUG=none
TEST=console commands: i2cscan, battery, charger, and accelinfo.
Change-Id: I5025f640c027105152247212fc688388f645c5ba
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/485203
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL includes:
1. Add gpio_chip-npcx5/7.h files and move all macro functions
related to chip family to them. (Move wui macro func from
gpio_wui.h to them.)
2. Replace alternative and low-voltage mapping table with macro
function NPCX_ALT_TABLE and NPCX_LVOL_TABLE.
3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR.
4. Add gpio register definitions of npcx7 family in registers.h.
5. Add GPIO_LOCKED flag for lock functionality.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Passed validation for all GPIO functionalities on npcx5m6g
and npcx796f evb.
Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481561
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL includes:
1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish
which npcx's ec is used on the board.
2. Add config_chip-npcx5/7.h files and move features depend on chip
family into them.
3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and
NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on
npcx7 ec. We'll use them later in gpio/system/flash drivers.
4. Add ram size checking for all npcx ec series.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481560
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Allow EC to take Lid Accelerometer readings in S0 to support rotation,
but disable taking Gyro readings unless requested by AP.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
BRANCH=none
BUG=b:36668539
TEST=in ec console: accelinfo on
=> confirm Lid Accel values are non-zero
=> confirm Gyro values are zero
Change-Id: Ie0bf466a5877cf8d20fb3d5cd223696fbdc9c271
Reviewed-on: https://chromium-review.googlesource.com/484140
Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Tested-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
cr50 and hammer/common code are such different chips that reusing the
same first_response_pdu does not make much sense.
Instead, we can use 2 different headers, the updater knows which
response to expect based on USB product ID.
In the common code answer, we can reply with the EC version string,
as well as rollback information and key version ID, which will
be required for reliable updating.
BRANCH=none
BUG=b:35587171
BUG=b:36375666
TEST=usb_updater2 can update hammer, and read its version, rollback
version and key version.
Change-Id: I20b04070606767c71df3e6286d53e238e13375c0
Reviewed-on: https://chromium-review.googlesource.com/476452
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
In npcx's fan driver, ec selected mode 5 and capturer A as tachometer's
input. Choosing TB2 as the second tachometer source is not correct since
we didn't initialize the registers for TB2. This patch modified the
second tachometer's input from TB2 to TA2 and passed the verification by
following changes.
1. Add the second fan settings in pwm_channels, fans, and mft_channels
arraies.
2. Modified ALTERNATE marco for pwm-type fans.
3. Set CONFIG_FAN from 1 to 2.
4. Set NPCX_TACH_SEL2 to 1 to test tachometer input 2. (ie.GPIO73/A6)
BRANCH=none
BUG=none
TEST=test dual fans with fanset command on npcx_evb and use faninfo for
verifying. Measure the actual rpm by scope.
Change-Id: Ia1af2732d9a64e24285d12371223eb0e77e53357
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/472310
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL simplified TACH_TO_RPM formula and abstracted two definitions
(PULSES_ROUND and RPM_DEVIATION) for the pwm-type fan used on boards.
The developers can modify them in board-level driver if fan doesn't meet
the default spec.
In this CL, it also fixed:
1. Declare rpm_pre as array if FAN_CH_COUNT > 1.
2. Add checking for the value of next duty of pwm.
3. Use TAPND pending bit to make sure TCRA is valid.
BRANCH=none
BUG=none
TEST=test fan used in kahlee and Sunon fan with fanset command on
npcx_evb and use faninfo for verifying. Measure the actual rpm by scope.
Change-Id: Ieb07482eb359912286414ccb9738341d98ea99e4
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/472289
Reviewed-by: Randall Spangler <rspangler@chromium.org>
ecst adds the support for npcx7 series in this CL. (The name of npcx7m6f
is fixed. The others are TBD.) It also includes:
1. Fix few typos and replace tab with spaces in ecst.h for better
alignment.
2. Add -spiclkratio parameter for the ratio between core and spi flash
clock in npcx7. (default ratio is 1.)
3. Add -unlimburst parameter for burst mode of spi flash accesses.
(default is disable)
BRANCH=none
BUG=none
TEST=No build errors for npcx7 and npcx5 series. Build poppy board with
ecst 1.0.3 and upload FW to platfomr. No sympton found.
Change-Id: I004edc068c6496390e03d8ee5e39e4f23e4b835f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/476413
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Power button pulse is disabled by the host whenever it wants to treat
the power button as an input and not trigger SMI. Clear this setting
whenever there is a chipset state transition to default pulse
enabled.
BUG=b:37277943
BRANCH=None
TEST=make -j buildall
Change-Id: Id0cb3748bf7e25ad9111170116113151d9bed69e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/476090
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Change pwm freq of fan from 100 to 25kHz. Normally, the operating freq
of pwm fan is around 25kHz. The inappropriate pwm freq will cause the
response time of fan spped is too long. Please notice the source clock
of pwm is apb2 now. The clock will be gating if ec enters deep sleep.
It should not enalbe CONFIG_LOW_POWER_S0 in board-level driver if fan is
used.
BRANCH=none
BUG=none
TEST=test fan used in kahlee and Sunon fan with fanset command on
npcx_evb and use faninfo for verifying.
Change-Id: Ic0e7509d9cdb2758bc6e674c207ac3dfbdc59dbe
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/472647
Reviewed-by: Shawn N <shawnn@chromium.org>
rw_sections is defined in the exact same way on all common code
boards, let's remove it, and hard-code the values in update_fw.c
instead.
Take this as an opportunity to fold set_valid_section in
fw_update_start (this will be useful later on, as we also
want to return the inactive region version).
BRANCH=none
BUG=b:35587171
TEST=make buildall -j
TEST=Can update hammer over USB using usb_updater2
Change-Id: I4dd3224f17f89c1851c379255f1195dc54528b3d
Reviewed-on: https://chromium-review.googlesource.com/476451
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Let's move to protocol version 6, which provides most of the new features
we want to update generic EC firmware.
Note that this matches chip/g version as of commit 0e5497db6,
plus the following uncommited chip/g patches (CL:458364):
c73af7dd2 chip/g/upgrade: Clarify pdu/frame terminology
baea0a8c7 chip/g/upgrade: Rename SIGNED_TRANSFER_SIZE to UPDATE_PDU_SIZE
d6e41b75c chip/g/upgrade: Remove cr50-specific upgrade subclass and
protocol
3dc0b9a25 chip/g/upgrade: Rename upgrade to update
13436f9b9 chip/g/upgrade: Split rdpu initialization to a separate function
fab9a0936 chip/g/upgrade: Minor formatting fixups
8161ef7c0 chip/g/upgrade: Fix valid_transfer_start logic
bd6d79434 chip/g/upgrade: Fix logic for short USB packets within frames
b09e252ed chip/g/upgrade: Improve error handling
Then:
diff -u include/update_fw.h chip/g/upgrade_fw.h
diff -u common/usb_update.c chip/g/usb_upgrade.c
diff -u common/update_fw.c chip/g/upgrade_fw.c
Only shows chip/g specific differences.
BRANCH=none
BUG=b:36375666
BUG=b:35587171
TEST=make buildall -j
TEST=Can update hammer over USB using usb_updater2
Change-Id: I5b0f0281d844972dab572955d5495f808127e523
Reviewed-on: https://chromium-review.googlesource.com/458321
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The led is control by HOOK_SECOND, but if dut press ALT+VOL_UP+H, enter
hibernate mode when system in s0, there is no one second to turn off the
power led, so the power led is still on when system enter hibernate.
BUG=b:36328757
BRANCH=gru
TEST=press ALT+VOL UP+H, the power led turn off and system enter
hibernate mode.
Change-Id: I72d18876aa5468131bae7ad42203982d123db8ba
Signed-off-by: james_chao <james_chao@asus.com>
Reviewed-on: https://chromium-review.googlesource.com/476850
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
1. PD vender suggests to use chip default address setting (0x16).
2. Clean up board_print_tcpc_fw version function and related define.
BRANCH=None
BUG=None
TEST=Plug in type-c device and check behavior
Change-Id: I44b7156c914b8de67630696e4534147cc3b7f2c3
Reviewed-on: https://chromium-review.googlesource.com/469449
Commit-Ready: Lin Cloud <cloud_lin@compal.com>
Tested-by: Lin Cloud <cloud_lin@compal.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Before entering standby mode, bit 7 (cable_det) or analog_ctrl_0 is
cleared. This allows a new cable detect event to trigger the EC to
put the ANX4329 into normal mode. However, in some cases such as when
in S3/S5/G3 chipset power states a port will be in sink only mode and
therefore won't attach when a sink only adapter is connected to the
port. This results in the an indefinite toggle of standby<->normal
mode transitions. This constant toggle floods the EC console and more
importantly prevents the ANX4329 from remaining in standby mode and
the power consumption remains at ~9.5 mW instead of ~1.2 mW when no
adapter is connected.
This CL adds logic around clearing the cable_det bit so that it's only
cleared if both CC lines are open or if an Emark cable is
attached. Emark cable is determined from the presence of Ra on one CC
line and no Rd on the other CC line. The special consideration for an
Emark cable is reqiured because when an Emark cable is connected, the
USB PD auto toggle state may require some number of iterations until
the attach event is recognized.
In order to support handle cases where the drp mode is changed via
either the EC console command or host command, added a call to
tcpm_set_drp_toggle whenever the drp state is updated. Since the drp
mode is updated upon chipset resume events, the chipset resume hook in
board.c for anx74xx_cable_det_handler() became redundant and hence it
was removed.
BUG=b:35775019,b:35586188
BRANCH=reef
TEST=Tested the following cases:
- Sink, source adapters in chipset S0. Verified that adapters
connected as expected. Also, used Emark cable to connect to both USB
PD chargers (source) and Pixel phone (sink).
- Run 'lidclose' on EC console then connect Type C -> A adatper
[3490.370125 TCPC p0 reset!]
[3490.389588 TCPC p0 Low Power Mode]
It no longer toggles indefintely and after running 'lidopen' verified
that port 0 is now in SRC_DISCOVERY.
- In S3/G3 connected USB PD charger with regular and Emark typeC
cable. Verified that port 0 is in SNK_READY state.
- use 'pd dualrole sink' and test with Type C -> A adatper. Verified
that tcpc wakes up, but goes into standby mode until entering 'pd
dualrole on'.
- When sink only adapter is connected in S3/G3, measure power level
~1.2 mW as opposed to ~10 mW in S0.
- Repeated similar tests on port 1 (parade tcpc) to verify that
adapters connected as expected.
Change-Id: Ib8de666f72723934186fee7869f9dda01381c7a8
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/463991
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: S Wang <swang@analogix.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The cable_det signal is used to signal to the EC that the tcpc has
detected a cable being connected when low power mode is
configured. The driver then needs to take the tcpc out of suspend
state by setting PWR_EN and RESET_N high. Then bit 7 of analog_ctrl_0
needs to be set properly.
The code that is handling this transition was attempting to access the
tcpc via I2C before putting the chip in normal mode when
transitioning from suspend to normal. In addition there are issues
with calling the driver function directly from the hook task (in the
delayed ISR handler) and from the USB PD task.
This CL changes the delay ISR handler to only set the TCPC_RESET
indication so that the call to put the ANX3429 into normal from
standby to normal mode only happens in the USB PD task. The TCPC_RESET
event is only set if cable_det is high, but reset_n (to the ANX3429)
is low which indicates that the ANX3429 is currently in standby mode.
BUG=b:35775019
BRANCH=reef
TEST=Manual
Tested with various adapters in both S0 and S3/G3 chipset
states. Verified that adapters connected as expected. When in S3/G3
connecting a sink only adapter still causes an indefinite toggle, but
all calls into the driver are executed from within the USB PD 0 task
and all ANX3429 I2C accesses work as expected.
Change-Id: I6e4843e43f59afbf5ca3251feb68981b815c1c78
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457103
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
(Optionally) split rwsig verification into a separate task. This
allows us to initialize other components (e.g. USB) while the
verification is in progress, speeding up the boot process to active
USB in RO case.
After CONFIG_RWSIG_JUMP_TIMEOUT, the EC will jump to the RW section
if no action is taken by the AP (such as a forced request to jump
to RW, or starting an update).
Note: This comes with a ~36ms boot time regression, as other code
gets to run before verification starts.
BRANCH=none
BUG=b:35587171
TEST=Flash, board boots to RW after 1s
TEST=Change jump timeout to 5s, add 5s delay in check_signature,
add console command to manually abort/continue rwsig verification.
'rwsig continue' works => Board jumps to RW after check_signature
is completed (or immediately while waiting for timeout)
'rwsig abort' works => Board does not jump to RW.
Change-Id: Ica5732b9298bb4d3b743cae2ba78df259db915ef
Reviewed-on: https://chromium-review.googlesource.com/468709
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is done at RO stage. If the rollback region is unprotected, update
it to match the version in the RW image.
If the rollback region is protected, we can't do that update, so we wait
for RW to unlock that region (presumably after AP has verified that image
is somewhat functional) before updating it.
BRANCH=none
BUG=b:35586219
TEST=flashwp true; reboot => hammer reboots twice
flashinfo shows RO+rollback protected:
Flags: wp_gpio_asserted ro_at_boot ro_now rollback_at_boot rollback_now
Protected now:
YYYYYYYY YYYYYYYY Y....... ........
TEST=Hack version.c to add "+1" to rollback_version, check that RO updates
ROLLBACK info block on first boot.
TEST=Use hack above, convert rwsig to separate task, add 5000 ms delay in
rwsig just before rollback information is updated. Then:
Quickly type: flashwp true; reboot; flashwp all; reboot
=> Wait for system to jump to RW
rollbackinfo => minimum version 0
flashwp norb; reboot; wait for jump to RW
rollbackinfo => minimum version 1
Change-Id: I78e502315c611c5edaf34b8d70a12fedd3e57bdf
Reviewed-on: https://chromium-review.googlesource.com/452816
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If Cr50 does not have support for invalidating the RW header and
restoring it, then upstart should still post a reset. This changes
usb_updater to post a restart during upstart if the RW minor version is
less than 19.
BUG=none
BRANCH=cr50
TEST=manual
Copy new usb_updater onto the DUT. run 'sync'
Build two cr50 debug images one with 0.0.19 and one with 0.1.12
verify update process works
test_that $DUT_IP -b $BOARD firmware_Cr50Update
--args="old_release_image=$PATH_TO_PROD_13
release_image=$PATH_TO_PROD_18 dev_image=$DBG_IMAGE_19"
Build a firmware image with
https://review.coreboot.org/#/c/18946/3
test_that $DUT_IP -b $BOARD firmware_Cr50Update
--args="old_release_image=$PATH_TO_PROD_18
release_image=$DBG_IMAGE_19 dev_image=$DBG_IMAGE_1_12"
Change-Id: I811977de26999b1d26bd2d4126b88b1c55a93931
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/470326
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added a new static variable disable_dts_mode. By default, DUT port
will attempt to connect as a DTS source. However, if disable_dts_mode
is set via a console command, the DUT port will connect as a regular
source device. Charging behavior is identical between the two modes.
In DTS mode, Rp is presented on both CC lines. When it's disabled Rp
is presented only on CC1. Added tables to support the appropriate VNC
and RD voltage thresholds.
BUG=b:36908939
BRANCH=servo
TEST=Tested with new console command 'dts on|off'. If new mode equals
the current mode, no action is taken. If the mode is different, then
verified that DUT port connects as DTS following 'dts on' and regular
SRC following 'dts off'. Verifed this when the command is issued when
connected to the DUT or disconnected. Validated that the H1 console is
present for DTS mode and not present when DTS mode is disabled.
Change-Id: Ie649709d6b2bbe947708d05eac42fde61d2677a8
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/468447
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There's leakage through EC_INT when in S3 to the APs P3300_A rail.
Changing the GPIO config to be an input all EC_INT and all the SPI slave
pins during S3 removes the leakage.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=none
BUG=b:35648259
TEST=on Eve, run int_test before & after suspend/resume successfully.
Change-Id: I68e286c4770831544bea0d58ffa98185fd7ba788
Reviewed-on: https://chromium-review.googlesource.com/469527
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Follow-up to CL:456520, addressing a few more comments.
BRANCH=none
BUG=b:35775099
TEST=sysrq available in EC console
TEST=sysrq h => help message in AP console
TEST=sysrq b => AP reboots
Change-Id: I692afa7c911882f00d92b8e6d83889c52821e171
Reviewed-on: https://chromium-review.googlesource.com/468506
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
show_fw_ver runs send_done on both usb and tpm transfers. This changes
usb_update, so it will only run send_done on usb transfers
BUG=none
BRANCH=cr50
TEST=copy to dut. stop trunksd. Run 'usb_updater -f -s && usb_updater -f
&& usb_updater -f'
Change-Id: I3a09c003ae41a4651c9961092552d7807656a68a
Reviewed-on: https://chromium-review.googlesource.com/470169
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Right now there is no way to verify cr50 is asleep just by looking at
the UART output. You can check by running taskinfo and seeing that the
GC_IRQNUM_PMU_INTR_WAKEUP_INT irq count has increased or by measuring
cr50 power.
In the past we have had Cr50 issues that we think are related to sleep.
Devices like poppy will have the Cr50 uart connected to servo, so we can
capture the Cr50 console output. It would be helpful if there was an
easy way to tell that cr50 is asleep from the UART output to more easily
confirm issues might be related to sleep. This change will print '.'
every time Cr50 resumes from sleep. Cr50 wakes up every half second for
HOOK_TICK, so with this change '.' prints every half second while cr50
is asleep.
BUG=none
BRANCH=none
TEST=boot a device, wait a while, and verify cr50 starts printing '.'
every half second. Turn off the device and verify the '.'s stop.
Change-Id: I94a82db00076062dbba2c3bc273cbe0731430520
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/463990
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Implement actual rollback protection. First, we add a new field
in the version structure, which is an incrementing integer
(we'll start by shipping images with version 0, and gradually
increase the number as required). This allows us to release
new versions of the EC without necessarily bumping the rollback
protection.
For the rollback protection block itself, it contains 2 sub-blocks
of equal size (normally, 2k), that are individually erasable.
The rollback code looks at both, and takes the most restrictive one
to determine the desired rollback minimum version. The blocks
are also allowed to be erased (full of 1's), in which case the
rollback minimum version is assumed to be 0.
We also add an FMAP entry, in case we later decide to allow the
signer to increment the rollback version.
Also note that, like any version_data struct change, this change
breaks compatibility between old and new RO/RW.
Follow-up code will take care of auto-updating the rollback block
as required, and properly manage block protection.
BRANCH=none
BUG=b:35586219
TEST=Flash hammer
rollbackinfo => 1 version 0 block, 1 empty block, RW verifies
correctly.
rollbackupdate 0; rollbackinfo => No change
rollbackupdate 1; reboot => RO refuses to jump to RW
rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate
between the 2 blocks.
rollbackupdate 2 => Refuses to downgrade version
Change-Id: Ia969afb481a93deb912b9153bdd95ace01ad8fa7
Reviewed-on: https://chromium-review.googlesource.com/452815
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The accelerometer sensors are not needed in S5, and having them get
enabled early in boot is causing issues on a subset of boards.
Similarly, the magnatometer is supposed to be disabled in S3/S5.
BUG=b:36919184
BRANCH=none
TEST=successfully boot on board that was previously failing
Change-Id: I3c079a83b21b2f1875330ac16ef8d3f9da267f9f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/468686
Reviewed-by: Todd Broch <tbroch@chromium.org>
When a USB PD connection is made, servo_v4 senses the polarity of the
SBU signals and sets the SBU mux for the deteted polarity. If the DUT
is reset, the SBU mux needs to retain the same state so the H1 console
USB endpoint is not disrupted.
Modified the CCD_MODE_DISABLED case to no longer disable the SBU
mux. In addition, removed the static variable ccd_mode as it was being
set, but not ever being checked, so wasn't serving any purpose.
BUG=b:36561120
BRANCH=servo_v4
TEST=Connect servo_v4 to Electro. On Electro EC console enter 'reboot'
verify the H1 USB console remains connected.
Change-Id: I4f0f5167221c04314ca5be063411f200896bbdf6
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/464068
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
