Pull floating pins high, don't duplicate external pull ups, and make a
few other minor changes.
BUG=chrome-os-partner:48109
TEST=Verify chell continues to boot and S5 power is reduced to
~5.5 mW.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaee0cc926149dae1f4189e6b9e4f7e3a4da6ba1c
Reviewed-on: https://chromium-review.googlesource.com/319165
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Use custom charging profile to enable charging at a faster rate.
BUG=chrome-os-partner:48662
BRANCH=none
TEST=load on lucid and charge at room temp. Use "chgstate" command to
verify that battery current matches the expected fast charging current
for the given temp range and voltage.
Change-Id: Ie508d29db091593ff2cfda9d135c73f6a3de5a9a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/319493
Commit-Ready: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In 0% battery case, if the charger can provide power at least
15 Watt(CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW), will allow system to
boot up.
BUG=chrome-os-partner:48339
BRANCH=none
TEST=Verified in Kunimitsu system, system with 0% battery can boot up
normally once charger power is 15 Watt.
Change-Id: I0c7b23d4ac1e7bd2807ceeb068fc9018a99a03c4
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/318891
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
1. KSO[0-15] and KSI[0-7] can be used as GPIO input if they are not set for
keyboard scan function.
2. Critical section for gpio_set_level().
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: gpioset, gpioget, and version.
Change-Id: I8edae122525e6dcebaa3489116642d8e48520569
Reviewed-on: https://chromium-review.googlesource.com/318112
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
stm32f03x and stm32f070 officially do not support an HSI48 clock, so
configure our 48MHz clock using HSI8 and PLL.
BUG=chromium:568717
BRANCH=None
TEST=Verify snoball 1us timer is accurate and we can execute
approximately 48 million NOPs in a second.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347
Reviewed-on: https://chromium-review.googlesource.com/317459
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable the RSA verification of the RW partition,
so we are using the RW partition by default and
the USB PD flashing VDMs are able to update
the firmware over the Control Channel.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:47823
TEST=run the following sequence on a Samus connected to Honeybuns :
ectool --name=cros_pd infopddev 1
ectool --name=cros_pd flashpd 5 1 ec.RW.bin
ectool --name=cros_pd version
and see the honeybuns properly updated and running the new version.
Change-Id: I8f1612ee153a412620bae5822d1b354ad8072916
Reviewed-on: https://chromium-review.googlesource.com/312998
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
A typical EC image includes two similar in their functionality
subsections, RO and RW. CR50 has a small RO subsection, all it does -
detects a proper RW image to run and starts it up. To provide for
reliable firmware updates, the CR50 image needs to include two RW
sections, while the code is running from one RW subsection, the other
one can be upgraded.
This patch adds the ability to generate two identical RW sections,
mapped half flash size apart, and include them into the resulting EC
image.
To keep things simple the previously existing RW section's name is not
being changed, while the new (identical) RW section is named RW_B.
Two configuration options need to be defined to enable building of the
new image type: CONFIG_RW_B to enable the feature and
CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the
flash.
A new rule added to Makefile.rules allows to generate a different lds
file from the same source (core/cortex-m/ec.lds.S) by defining a
compile time variable to pick a different base address for the
rewritable section, when RW_B is built.
BRANCH=none
BUG=chromium:43025
TEST=as follows:
- make buildall -j still succeeds
- verified that regular CR50 image starts successfully
- modified chip/g/loader/main.c to launch RW_B first, re-built and
re-run the image, observed on the console:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
cr50 bootloader, 20151118_11218@80881, no USB, full crypto
Valid image found at 0x00084000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com]
[0.001148 Inits done]
This FPGA image has no USB support
Console is enabled; type HELP for help.
> [0.002212 task 2 waiting for events...]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(note that the image base address is 0x840000, which is RW_B).
Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316703
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If deep sleep S5 is supported RSMRST to the PCH should not be high
when the PCH is in S5 unless the board is sequencing out of deep sleep
and S5 state. Therefore, ensure RSMRST is low when the EC goes into
hibernate. This assumes deep sleep S5 is employed. A more appropriate
fix is to honor RMSRST state prior to going into hibernate state.
Without this change the behavior on certain platforms do not sequence
out of S5 when coming out of hibernate.
BUG=chrome-os-partner:48133
BRANCH=none
TEST=tested on a failing EVT chell board at the factory
Change-Id: Ia4a1cdb59c25a3fc704c64fbe6beb01ede90d777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
two port PD will keep interrupt low, and cause
EC.PDCMD task stuck with exchange status loop before
entering task-while-loop
BUG=chrome-os-partner:48232
BRANCH=lars
TEST=`make BOARD=lars -j`, OS can boot up normally
Change-Id: I493c6d02170c731af430f28abf8ade38b47aff0f
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/315362
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previous HW didn't correctly support 20V charging. The HW has been
corrected and now there is no need to keep 20V mode disabled in FW.
BUG=chrome-os-partner:48217
BRANCH=none
TEST=Tested in the lab by jguerin@ against Samus
Change-Id: I952872affb302c7aa2ddb97466cd5ce459d2ac54
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315219
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rather than having various PWM module groups initialized from various
HOOK_INIT functions, group them all into a single module and initialize
them all from a common function in pwm.c.
BUG=chromium:563708
TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that
samus fan + KB backlight control is functional and samus_pd correctly
sets PWM output.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941
Reviewed-on: https://chromium-review.googlesource.com/314882
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
A new extended subcommand code (1) is being added to handle hash
testing.
The new subcommand handler keeps track of multiple sha1 and sha256
contexts the host might want to exercise. The number of available
contexts is limited by the amount of available free memory.
One of four hash operations could be requested by the host: 'Start',
'Continue', 'Finish' - when hashing a single stream over multiple
extended command messages, and 'Single' when the entire message to be
hashed is included in one extended command payload.
The command payload had the following format:
* field | size | note
* ===================================================================
* mode | 1 | 0 - start, 1 - cont., 2 - finish, 3 - single
* hash_mode | 1 | 0 - sha1, 1 - sha256
* handle | 1 | seassion handle, ignored in 'single' mode
* text_len | 2 | size of the text to process, big endian
* text | text_len | text to hash
As soon as the first 'Start' message is encountered, the handler tries
to allocate shared memory to keep track of the test contexts, the
amount of available memory determines how many contexts the handler
can support concurrently.
As soon as the last 'Finish' command is encountered, the handler
returns the shared memory to the 'heap'.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=after adding the host side implementation and fixing a couple of
bugs, hash tests pass (see upcoming patches).
Change-Id: Iae18552d6220d670d1c6f32294f0af1a8d0d5c90
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314692
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Stack space is pretty tight on cr50, and since there is no need to
support SHA digest sizes in excess of 256 bits, the digest buffer size
should be reduced.
This patch makes the maximum expected digest size dependent on the set
of configured hash algorithms, moves hash size related asserts from
run time to compile time, and passes compile time definition to the
TPM2 library to increase its hash state container (it became too small
when SHA384 was disabled).
The sw context requirements should be reduced, but this is a task for
another day. We also do not have to store a local digest copy if the
API allowed reading a partial digest.
CQ-DEPEND=CL:314883
BRANCH=none
BUG=chrome-os-partner:43025, chromium:564862
TEST=all tests pass:
$ ./test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
SUCCESS: AES:ECB common
SUCCESS: AES:ECB128 1
SUCCESS: AES:ECB192 1
SUCCESS: AES:ECB256 1
SUCCESS: AES:ECB256 2
SUCCESS: AES:CTR128I 1
SUCCESS: AES:CTR256I 1
SUCCESS: sha1:single 0
SUCCESS: sha256:single 0
/New max timeout: 1 s
SUCCESS: sha256:finish 1
SUCCESS: sha1:finish 3
SUCCESS: sha256:finish 2
Change-Id: Iaef3a230469de129e72418814e1d113b447c0137
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314695
Reviewed-by: Nagendra Modadugu <ngm@google.com>
If pulled up the backlight will be at 100% brightness instead of off.
BUG=chrome-os-partner:48130
BRANCH=none
TEST=hibernate on chell, see keyboard backlight stay off
Change-Id: I30cd289b9492356407aa54e6a84b04add647bd9a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314936
Reviewed-by: Shawn N <shawnn@chromium.org>
Stack of PDCMD task may be overflow during plug/unplug stree test
with Apple's AV Multiport Adapter. Enlarge the stack size to avoid
system reboot.
BUG=chrome-os-partner:47728
BRANCH=none
TEST=Manual
1.Connect DUT to sink monitor via HDMI dongle.
2.Unplug HDMI USB from DUT side.
3.Plug HDMI USB cable to DUT USB socket.
4.Repeat (Plug and unplug) USB from DUT for 10 times.
Change-Id: Ib6a1fbd0a552b2c6d4656c12554e1306c21adb8a
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/315020
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When Link Time Optimization is turned on, functions that set
task_waiting multiple times have one of the sets removed
by the linker leading to undesired results.
Marking task_waiting volatile alleviates this issue.
BUG=chrome-os-partner:46063
TEST=Manually tested on Kunimitsu.
Console command adc shows correct value of approx
20000 mV for VBUS.
BRANCH=none
Change-Id: I85a6e5c9688ae72c45d90fb58296f94b74a301aa
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/314233
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
refer to commit 75f740fa, enabling the option on oak too.
BUG=none
BRANCH=none
TEST=plug in CDP, SDP, DCP, type-C, and PD charger. Make sure
we ramp to a reasonable value for the correct suppliers.
Make sure we don't ramp for type-C and PD chargers.
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Change-Id: I9c6a0726e9cb23af59d5841c63a81897ae624998
Reviewed-on: https://chromium-review.googlesource.com/314436
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add i2cscan and kbpress commands for FAFT.
Remove unnecessary i2c reading since there is no race condition.
Bugs fixed:
Fixed i2c_read_string bug since we shouldn't enable NACK if flag doesn't
contain I2C_XFER_STOP.
Fixed i2c_unwedge bug since the parameter should be port not controller.
Fixed state machine bug since we should restore bus state back to idle
if bus encountered timeout.
Modified drivers:
1. board.h: Add i2cscan and kbpress commands for FAFT.
2. i2c.c: Remove unnecessary reading since there is no race condition.
3. i2c.c: Fixed i2c_read_string and i2c_unwedge bugs.
4. i2c.c: Restore to idle state if bus encountered timeout.
5. board.h: Add CONFIG_LOW_POWER_IDLE for better power consumption.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I98974f852cbbaec270c697feb8016b52550005bc
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/313393
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since two port may cause some unexpected problem in a
one port board.
I've cloned this from glados_pd without any code changes
and I'll remove the second port settings at another CL.
BUG=None
BRANCH=lars
TEST=`make BOARD=lars_pd -j`
Change-Id: I84b3d2fa705ff089aabd52ab71d9fb59eecdd027
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/314637
Reviewed-by: Shawn N <shawnn@chromium.org>
Send power change event to AP whenever input power is changed,
ensure that AP gets the latest power charging info.
BUG=chrome-os-partner:47677
BRANCH=none
TEST=tested on Oak by plug/unplug AC adapter to type-C ports and
verifying the UI battery icon shows the correct status instantly.
Change-Id: I7465afcd8bc9b1c56ecf70fc74446866a8ab1b9a
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/313926
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If multiple TCPCs are present on a system then we may have multiple
alert signals, each of which alerts us to the status of a different
TCPC. Make boards with external non cros-ec TCPCs define
tcpc_get_alert_status, which returns alert status based upon any alert
GPIOs present, and then service only ports which are alerting.
BUG=chromium:551683,chrome-os-partner:47851
TEST=Verify snoball PDCMD task sleeps appropriately when no devices are
inserted, and verify ports go to PD_DISCOVERY state when we attach
samus. Also verify that glados / glados_pd can still negotiate PD.
BRANCH=None
Change-Id: Iae6c4e1ef4d6685cb5bf7feef713505925a07c8c
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313209
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
These functions are mostly no-ops it turns out, maybe something will
be needed to be done for RSA and ECC initialization, for now leaving
those functions commented out as a reminder.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=tests passing before this change still pass.
Change-Id: Iee9aaf133a55a6197c9896ed48efb34a4b3340c6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314096
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Let's increase it to 4K, this seems to be adequate for tests so far,
but with the enabled stack size monitoring we should find out quickly
if in certain cases this is not enough.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=the test involving the use of SHA hardware does not fail in
mysterious ways any more.
Change-Id: I86da89ccca42d1a60ce7c1dfef08d21bf44f1eee
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314095
Reviewed-by: Randall Spangler <rspangler@chromium.org>
