This gives us better control over the execution state of lighting
engine.
BUG=chromium:233832
TEST=Build success
BRANCH=spring
Change-Id: Ibfa86be0eef2b7dff8495f770649577295d4cb6f
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48773
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Link uses LID_SWITCH_L but it means the same thing as LID_OPEN. Changing
it to LID_OPEN so that all boards use the same name.
No functional changes, just renaming.
BUG=chrome-os-partner:18343
TEST=build link, bds
BRANCH=none
Change-Id: I74893e1365ad3068f13e7fe948f1a54c6c6301bb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48893
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This adds software flow control handling (a.k.a X-on/X-off). When Ctrl-Q
is received, UART transmitting is paused until Ctrl-S is received. If
the FIFO or buffer fill up during this period, console output is lost.
BUG=chrome-os-partner:18680
TEST=Press Ctrl-Q and see console stopped. Press Ctrl-S and see buffered
messages.
BRANCH=spring
Change-Id: I9ce1198a1119dadc558bb522c48037bb83bba415
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48887
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There is a 4% difference between the kernel's view of battery level and the
actual battery level, to give userspace a chance to shut down cleanly. The
EC should turn the lightbar red when the battery drops below 10%, so this
change makes that happen when the kernel says it's 10%, instead of the real
10%.
Note: We don't have to cherry-pick this to the Link branch. Although it
affects the EC, we already patch the EC lightbar parameters at boot and
that's done in userspace.
BUG=chromium:225500
BRANCH=none
TEST=manual
Unplug Link, let the battery run down. The lightbar should pulse red when
the battery level reported by the UI drops to 9% (there may be a little
delay due to rounding). Note that it's only red when on battery.
Change-Id: If3d335c54ceb37c86da59e4a66f8ecd46ce15664
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This is now consistent with other boards.
No functional changes, just renaming,
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build link, bds
Change-Id: Ifd7c1ec608ab61f5f66800e91803ffafe1d944b6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48804
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The 3.3V rails powers some of the buck supplies, so must be turned on
1ms after the 5V rail.
BUG=chrome-os-partner:18657
BRANCH=none
TEST=build pit, snow
Change-Id: I18a165744352ae375080824fecfeb56f6ac81a9c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48729
Reviewed-by: Vic Yang <victoryang@chromium.org>
Also changes utils test to use EC_SUCCESS to indicate test success.
BUG=chrome-os-partner:18598
TEST=Run on Spring
BRANCH=None
Change-Id: I4a9b08550c15f09cd467706b6a3c0142dd06a558
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48751
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Pit uses GPIO PA2=TIM2_CH3 instead of Snow's PB3=TIM2_CH2. Other than
that, the timer setup is identical (STM32F and STM32L are compatible
in this respect, anyway).
BUG=chrome-os-partner:18657
BRANCH=none
TEST=build snow, pit; no pit boards to test on yet
Change-Id: I8ba68f99641038e12c9a9c9dd29e3b64410a5eef
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48403
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
No need for it to be a separate file.
Just moving code, no functional changes.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build link
Change-Id: I25f84c73401929bce4ac76ebdcf6c86ad4852594
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48684
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
CPU creates an exception frame on the main stack instead of the process
stack when the exception happens in a handler's context. So, we need to
save both msp and psp, and pick the right one to locate the exception frame.
Tested by marking the stack (as you see in the dump below) then triggering
divzero in svc_handler.
> crash svc
=== HANDLER EXCEPTION: 03 ====== xPSR: 6100000b ===
r0 :00000000 r1 :0000e237 r2 :000015cf r3 :000015cf
r4 :00000001 r5 :22222222 r6 :11111111 r7 :0000df01
r8 :00000000 r9 :2000545e r10:00000000 r11:00000000
r12:0000000d sp :20000fb8 lr :000055d7 pc :00000b40
Divide by 0, Forced hard fault
mmfs = 2000000, shcsr = 70080, hfsr = 40000000, dfsr = 0
=========== Process Stack Contents ===========
20002738: 11111111 22222222 33333333 44444444
20002748: 00000000 000003ad 000003c0 81000000
20002758: 00000000 0000557d 0000557c 21000000
20002768: 00000000 00000000 00000000 00000000
Rebooting...
BUG=chrome-os-partner:16901
BRANCH=none
TEST=mentioned above
Change-Id: I3ca08a1df20375953552b3dc926350e262b78b2a
Signed-off-by: Daisuke Nojiri <dnojiri@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/47495
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is a struct representation of the STM32 timer registers, so
belongs in registers.h instead of the platform-independent hwtimer.h.
Note that there are other problems with the use of this struct. It
should be volatile, and if it's a win vs. the macros we should replace
ALL macro'd timer register accesses with the struct instead of just
those in hwtimer.c (that is, we shouldn't do things both ways). I'll
address those in a subsequent CL after testing which way generates the
most compact code.
No functional changes, just moving the struct definition.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: If29d008fb38b9cc847b69eda1ee7c05e67f6e5e7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48415
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Hello test should be a setup step for every test. This should be
implemented on the test server side. Remove it to reduce number of test
binaries.
BUG=chrome-os-partner:18598
TEST=None
BRANCH=None
Change-Id: I462156f6d7affdf7ceb67e4354804fedb18a5424
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48196
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a function which handles translation of PWROK from logical level
to physical level.
Also implement chipset_force_shutdown() in gaia_power.c, so PMU code
doesn't need to know about PWROK physical level.
BUG=chrome-os-partner:18738
BRANCH=none
TEST=build all platforms; boot spring
Change-Id: I360266ef89b6ead49a633cd57b7530f791b04c9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48251
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The latest schematics move a few signals between GPIOs. Update the
GPIO map to match.
BUG=chrome-os-partner:18657
BRANCH=pit
TEST=build pit (can't test the binary yet; no hardware)
Change-Id: I2d135412723fbe5cf4e7c1dbeb05fc68e6bb8c9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48231
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is left over from when we had a pair of macros for each GPIO
register, one which concatenated its base address name and one which
took a base address. Only the latter has survived, but its naming is
longer than it needs to be and isn't consistent with other register
banks (USART, TIM, etc.).
No code changes, just renaming macros.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I15a282fd01db2a25219970e28ce551d8dc80193f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48226
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add support for flashing Spring board through the Toad cable (given the
Write Protect screw is not on).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=spring
BUG=chrome-os-partner:17570
TEST=with both a Toad cable and a servo v2, flash EC on Spring EVT
with the following command:
./util/flash_ec --board=spring
and check the state of the servo/toad before and after.
Change-Id: Ia4e0d32b062d58b4e906d3f006003fa6097add83
Reviewed-on: https://gerrit.chromium.org/gerrit/48031
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This merges flash_overwrite and flash_rw_erase to a single test binary.
BUG=chrome-os-partner:18598
TEST=Run on Spring
BRANCH=None
Change-Id: I1da7577cb5dc196178930dda3a07bb942d959866
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48090
Reviewed-by: Randall Spangler <rspangler@chromium.org>
gpio_set_level() now allows setting the pin level if GPIO_LOW or
GPIO_HIGH is specified. Previously, stm32 platforms did this even
though the definition of gpio_set_level() said it wouldn't work.
Fixed gpio_set_level() not setting level after warm reboot on stm32
because it was checking the GPIO_DEFAULT flag in the wrong place.
Fixed LM4 still mucking with alternate function settings and levels
even if GPIO_DEFAULT was specified.
And checked gpio_list[] and all of the calls to gpio_set_flags() to
make sure everything still behaves the same way it did before (or
better, in the case of actual bugs).
BUG=chrome-os-partner:18718
BRANCH=none
TEST=build all platforms; boot spring and link
Change-Id: I4b84815f76060252df235ff9a37da52c54a8eac5
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48058
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Now pingpong and mutex tests compile. Still need some more work to
handle the i8042-specific KEYPROTO task for keyboard tests.
BUG=chrome-os-partner:18598
TEST=Build tests for link
BRANCH=None
Change-Id: I9ee35d4edb811f17b9a81beb799484a07c0bef14
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47981
To minimize the number of test binaries, we should put as many tests in
a single binary as possible. This CL merges kb_debouncing and
kb_deghosting and renames them to kb_scan.
BUG=chrome-os-partner:18598
TEST=Run on Spring
BRANCH=None
Change-Id: I876363ba68c692a7af10badfa474a2ea9a9d002c
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47980
Those mock files were used by QEMU-based test. Now that we moved to
hardware test, we can remove them.
BUG=chrome-os-partner:18598
TEST=Run on Spring
BRANCH=None
Change-Id: I1600b39132c598a07d3d6439fd837c0d78ea8820
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47968
All accesses use the _OFF variants. No need to have 2 ways of doing
the same thing.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I914e6dd9027bcf2268e33ae2e8cfb41093b0b05d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48032
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The MODER register is used to set (alt-func | analog | gpio-in |
gpio-out). So there's no need to force things to be normal GPIOs in
board config, since gpio_pre_init() will clear the alternate
function-ness as part of setting the GPIO direction.
BUG=chrome-os-partner:18657
BRANCH=none
TEST=build pit and test-boot on daisy
Change-Id: I82db9d9f4d8877464d62c1ff2efaef36822fc0ca
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47904
So there's no need to check for BOARD_daisy there
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I518e4a091d279fc6b23d1c9448362c3b315a6905
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47894
gpio_set_alternate_function() used 0 to mean "normal GPIO function".
But on chips like STM32L, alternate function 0 is actually a function
on some pins. So change "normal GPIO function" to -1.
Also add support for this on STM32L.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build and boot link and daisy
Change-Id: I9cdd9ad91a315b616e373a0dc9a50545cf9d20fa
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47903
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Its implementation is the same on all platforms.
No functional changes, just renaming/moving.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I78741c6587ea61e7ac8edae5a509502b7ab5078b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47898
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Nothing has used this since link EVT, so it's just dead code at this point.
BUG=chrome-os-partner:13213
BRANCH=none
TEST=manual
- Update ectool but leave old firmware
- ectool version -> works
- ectool flashread 0 0x10000 foo -> puts the first 64KB of EC flash into foo
- Update firmware
- ectool version -> works
- ectool flashread 0 0x10000 foo -> puts the first 64KB of EC flash into foo
- power+esc+refresh -> recovery mode
Change-Id: Ib25a705bcd8280d5295c8e7890969d796542b6c9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47866
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Puts test behind a console command and also fix uart_printf calls. Also
reduces stack size to fit tasks into STM32 memory.
BUG=chrome-os-partner:18598
TEST=Run mutex test on Spring.
BRANCH=none
Change-Id: Icac77876ae01fc98b4e38f27e07f788b6c9bdd70
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47834
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
For most tests, we don't need to power the AP. Let's exclude chipset
task to save memory space.
BUG=chrome-os-partner:18598
TEST=Run pingpong test on Spring
BRANCH=none
Change-Id: I545c5b3e1c27b0067d4ffe09a7971d32b75d6039
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47833
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This fixes outdated uart_printf calls and also put the test behind a
console command 'runtest'. The console command returns 'Pass' or 'Fail'.
BUG=chrome-os-partner:18598
TEST=Run pingpong test on Spring
BRANCH=none
Change-Id: Ia2c439685447e42b278556ca66c9f080d4cafe11
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47831
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Make internal APIs static, and remove board_ prefix for clarity.
Move TSU6721 calls from charger task to extpower_usb functions for
better encapsulation.
No functional changes, just moving code. Yes, this will make
cherry-picking back from spring to TOT less convenient, but now the
code is more readable and it will make maintaining the PMU code easier
as we add boards.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build spring
Change-Id: I52b37e57fc8519859996a110b0503277c6f0bbc8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47657
This only needs to be defined if CONFIG_USB_CHARGE is defined (that
is, if the board has a USB charge controller.
(Note the difference between providing power over USB vs. receiving
power over USB; the names are confusing and I'll rename one of the two
imminently.)
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I7355b4248bb2d4f5f71cc9f8d9d8f9d6c0069f2b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47658
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
And use them for LM4 as well as STM32. Consistency is good.
No functional changes, just moving/renaming code.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms
Change-Id: I029a21fadb50726500255219dc38615874a369e7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47700
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This removes all tasks defined in board tasklist and changes syntax to
CONFIG_TEST_TASK_LIST and TASK_TEST.
BUG=chrome-os-partner:18598
TEST=None
BRANCH=None
Change-Id: Ie56c8edcb1dbf0ba0d0426ffce2a525594602a91
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the system is turned off and then back on, we need to re-enable
3.3V output from TPS65090. Also, when we see 5V input, we should shut
down 3.3V output and re-enable it when 5V input goes away.
BUG=chrome-os-partner:18186, chrome-os-partner:18482
TEST=Manual
BRANCH=spring
Change-Id: I0cf0597a60988cc9ec28282eea54908c81e5eabc
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47736
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This changes current TASK() syntax to TASK_BASE() and TASK_NORMAL(),
where TASK_BASE is necessary for the EC to boot on a board and
TASK_NORMAL represents the task that can be removed in a test binary.
Tasks introduced by a test should be listed as TASK_TEST().
Note that this CL breaks current tests (many of them are broken anyway),
which will be fixed in up coming CLs.
BUG=chrome-os-partner:18598
TEST=Build link/bds/spring/snow/daisy/mccroskey. (mccroskey failed for
unrelated issue)
BRANCH=none
Change-Id: Ic645cdae0906ed21dc473553f1f43c2537ec4bb9
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47531
This makes gaia_power.c compile when keyscan task is not present.
BUG=chrome-os-partner:18598
TEST=Build spring without keyscan task.
BRANCH=none
Change-Id: I70823fb562a2542d92929b9219d034216f636938
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47630
This more clearly indicates what it does - it manages external power
supplied by USB. This code will be common to multiple boards which
take power via USB, so it might as well move now.
No code changes, just moving the file.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build spring
Change-Id: Iae74122db38666bc346104a5096fa82df8cb0c19
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47656
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
There's no chipset for mccroskey, so its keyboard code stopped compiling.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build mccroskey, spring, link
Change-Id: If94dfaf2819f047a6aa825ee10aa1d320c8ca882
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47566
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
GPIO mapping is correct for current schematics.
Things to fix are #ifdef'd out with PORT_TO_PIT, but those require
changing other files (which is most tidily done in separate CLs).
BUG=chrome-os-partner:18657
BRANCH=pit
TEST=build pit (can't test the binary yet; no hardware)
Change-Id: Id1d1bb0c2925cfc0c21ee2d91666028aa6d2a707
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47599
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
When unit testing, we may need to disable key scan task but leave
keyboard protocol code for testing.
Also fix a bug in determining if ENABLE flag is set.
BUG=chrome-os-partner:18598
TEST=Remove KEYSCAN task and build for spring.
BRANCH=none
Change-Id: I3b3adf1257e8446fd1f57bce50b4c7a029b1ce3b
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47539
Much of the board init duplicated stuff already done in gpio init, so remove it.
Powering the SPI module should be done in spi.c, not board.c.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; boot EC on daisy
Change-Id: I9a99eeeb971ebbf7de5b9c0548153684fbb7fff6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/47469
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
