Boards Rev1 and Rev2 will lose VBAT on power cycle and therefore
cannot successfully save the reset flag state.
Implement workaround that will allow these boards to continue to
work for FAFT testing by indicating to the skylake chipset power code
that it should skip the PMIC reset when doing 'reboot ap-off'.
BUG=b:62504451
BRANCH=None
TEST=Verified that "reboot ap-off" works fine on Rev1.
Change-Id: I97ee346c0e8796375dc295cfa7a86cd0d57d4e4f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/530515
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This patch makes a few changes to gpio.inc.
- When pre-initialize GPIOs, set default level to low:
ENTERING_RW and USB2_OTG_VBUSSENSE.
- Disable internal pull-up (not necessary if
output type is push-pull):
USB_Cx_5V_EN.
- Set output type to open-drain:
EN_USB_Cx_3A and USB_C0_CCx_VCONN_EN.
The USB_C0_CCx_VCONN_EN is externally pulled up to PP3300_PD_A.
The EN_USB_Cx_3A is pulled to EN_USB_Cx_5V_OUT and connected
to base of BJT directly. The output current will be huge
if it is set as push-pull.
BRANCH=none
BUG=none
TEST=1. built and booted on reef_it8320.
2. plug-in a device on one port and add load current
on vbus to check if current limit sit at 3A.
Change-Id: I71fec59cd1696fff417d9cddc287e993988aea33
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/528034
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This CL locks VCC_RST# alternative bit, NO_VCC1_RST, of DEVALTA
in case the developers switch it to GPO77 unexpectedly by setting
VCC1_RST_LK bit in DEV_CTL4.
BRANCH=none
BUG=none
TEST=Use rw console command to make sure NO_VCC1_RST bit is
locked on npcx7_evb.
Change-Id: Ic7882ef1c8050c3daca85bd241d5368f009e4e2e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/522206
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In this CL, we add selecting LFCLK sources functionality for npcx7 ec
series. (Please notice not all of npcx7 ec series support this feature.)
Beside internal LFCLK source, ec also can choose the external 32kHz
crystal oscillator as LFCLK source for the specific application. We also
introduce a new definition, CONFIG_CLOCK_SRC_EXTERNAL, to switch this
feature in the board level driver.
This CL also adds:
1. LFCG register definitions in registers.h.
2. Change the order of each npcx modules by memory address.
BRANCH=none
BUG=none
TEST=Output LFCLK source through GPIO75. Compare with external 32kHz
crystal osc. on npcx7_evb and make sure the sources are the same.
Change-Id: I137146bf51ccb51266b9aac1e2e28bcea87dc4f5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/520745
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Adds a mechanism that allows a board to disable interrupting the AP /
kernel when the status of any one of the EC_HOST_EVENTS included in
CONFIG_HOST_EVENT_REPORT_MASK changes state. Default state enables
reporting of all events; a board can override this by defining
CONFIG_HOST_EVENT_REPORT_MASK in its board.h file.
NOTE: The host_set_events() and host_clear_events() routines no longer
interrupt the AP if none of the host events the AP is interested in
changed state.
BRANCH=none
BUG=chromium:637061
TEST=make buildall passes
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Change-Id: I678fb9d9dab6890848b94b314efd711842b1fd48
Reviewed-on: https://chromium-review.googlesource.com/502078
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When specifying board ID to program, it is convenient to be able to
specify the ID as a string, as reported by the RLZ stored in the VPD.
With this patch the first component of the board_id command line
option is considered a string if it is no longer than 4 bytes.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=ran the following commands (interleaved with erasing INFO1 on the
target):
localhost ~ # usb_updater -s -i
Board ID space: ffffffff:ffffffff:ffffffff
localhost ~ # usb_updater -s -i ABCD
localhost ~ # usb_updater -s -i
Board ID space: 41424344:bebdbcbb:0000ff00
localhost ~ # usb_updater -s -i
Board ID space: ffffffff:ffffffff:ffffffff
localhost ~ # usb_updater -s -i 0x41424344:0x1234
localhost ~ # usb_updater -s -i
Board ID space: 41424344:bebdbcbb:00001234
localhost ~ # usb_updater -s -i
Board ID space: ffffffff:ffffffff:ffffffff
localhost ~ # usb_updater -s -i ABCD:0x1234
localhost ~ # usb_updater -s -i
Board ID space: 41424344:bebdbcbb:00001234
Change-Id: Ied8b240d60ea50f6fc8633f919ce4bc81ac17727
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/528440
Reviewed-by: Randall Spangler <rspangler@chromium.org>
poppy uses an ISL charger, which, unlike bd9995* charger based
systems, cannot provide an interrupt when VBUS falls below/rises
above a certain threshold.
On poppy rev2 onwards, we have a precise VBUS detection pin coming
from BC1.2 detection chip (PI3USB9281C), we a threshold between
3.1-3.7 V (3.5V typical) so we can use that to
enable discharge, according to this logic:
- When VBUS voltage falls below ~3.5V, and we're not sourcing 5V
to the port, enable discharge.
- When VBUS voltage rises above ~3.5V, disable discharge.
- When we source 5V to the port, disable discharge.
BRANCH=none
BUG=b:37525769
TEST=Charge out to device (Galaxy S8), and verify that VBUS
drops to 0.8V much faster than without this patch.
TEST=pd 0 swap power: 28ms (vs 496ms)
TEST=pd 1 swap power: 24ms to 0.875v, 202ms to 0.8v (vs 410ms)
TEST=Disconnect cable (port 0): 65ms (vs 721ms)
TEST=Disconnect cable (port 1): 13ms (vs 515ms)
Change-Id: Ibf2dcf5de31514fa0ce0ebd0c6db53d421a586fe
Reviewed-on: https://chromium-review.googlesource.com/481562
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Invoking signer with sudo is required only when signing requires a USB
fob. Let's not use it in unless necessary.
BRANCH=cr50
BUG=chromium:728751
TEST=verified that Cr50 build succeeds when both using and not using
the signing fob.
Change-Id: I8f40bd52f1752bfd88ec002f298b991faf7a2512
Reviewed-on: https://chromium-review.googlesource.com/528373
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This CL adds:
1. Fixed the incorrect address of BKUP_STS register.
2. Cleared the IBBR bit of BKUP_STS register at initial because
its default value is 1(means the content of BBRAM is invalid) whenever
VBAT is powered up.
3. Add debug msg when IBBR bit is set to indicate the BBRAM's
corruption.
4. Modified the valid BBRAM offset from 1 to 0 and size from 63 to 64.
BRANCH=none
BUG=b:38187362
TEST=No build error for make buildall; Check IBBR is cleared at initial.
Check IBBR is set by changing the VBAT voltage below VBAT MIN.
Test console command "reboot ap-off" on poppy.
Change-Id: I69d98b50d4e0aec17b55a4a9b5e8f1a412a3fe45
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505861
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The recent change of the code signer is not backwards compatible, a
new command line parameter must be added.
BRANCH=cr50
BUG=none
TEST=verified that
H1_DEVIDS='xxxx yyyyy' ./util/signer/bs
succeeds again.
Change-Id: I9a8e03c20aa4b7b689b1f5e4a1f786cf5857483f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/527317
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Cr50 needs to be able to bit bang the EC UART in order to flash certain
ECs such as the STM32 family. This is because the UART block on the
chip has no provision to change the parity which is necessary for the
STM32 bootloader protocol.
This commit adds a configuration to bit bang the EC UART. It's been
tested at 9600 baud.
BUG=b:35648297
BRANCH=cr50
TEST=With a logic analyzer, verify that TX to the EC can be bit banged
with no issues at 9600.
TEST=With some other changes, verify that cr50 is able to flash an EC
image to an STM32 EC.
Change-Id: Ice72aff133f268b5b7f0868aeec590a21404d1af
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/503474
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There are some useful UART bitbang commands, statistics, and logs and
such. These shouldn't be enabled by default, and this commit makes it
so.
BUG=b:35648297
BRANCH=cr50
TEST=Build an image that enables UART bit banging with BITBANG_DEBUG set
to 0. Verify that the associated debug commands and statistics are not
present.
Change-Id: Ic0348a6fb1620229e2ed601e0ff549596d814e1e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/527605
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This reverts commit 9565b8ba06.
Reason for revert: This is causing memory test failure under specific
reset conditions that is triggered by a specific FAFT test.
BUG=b:35581264
BRANCH=eve
TEST=pass FAFT test firmware_FwScreenPressPower
Original change's description:
> eve: Set VCCIO rail to 0.85 and disable low power
>
> Set the VCCIO rail to 0.85V where it should be for Y-series parts
> instead of forcing it to 1.0V. The EDS is pretty clear that pushing
> this voltage higher on Y-series parts will have significant power penalty.
> (up to 250mW at 0.95V)
>
> We also don't want this rail dropping in low power mode, which shoudln't
> be happening as S0ix is disabled so SLP_S0 shouldn't assert, but just in
> case disable this as well.
>
> BUG=b:35587084
> BRANCH=eve
> TEST=stress testing on Eve EVT units
>
> Change-Id: I5535fe0d894f283a8d453d61101dfeb6b9287b7c
> Signed-off-by: Duncan Laurie <dlaurie@google.com>
> Reviewed-on: https://chromium-review.googlesource.com/525836
> Reviewed-by: Todd Broch <tbroch@chromium.org>
Change-Id: Ie60ad319421c00df5bf41b9eca03047a37defb88
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/527513
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Add touchpad related host commands:
1) EC_CMD_TP_SELF_TEST: run open short test.
2) EC_CMD_TP_FRAME_INFO: get number of frame and frame size.
3) EC_CMD_TP_FRAME_SNAPSHOT: make a snapshot of the frame.
4) EC_CMD_TP_FRAME_GET: get frame data.
BRANCH=none
BUG=b:62077098
TEST=`make BOARD=rose -j`
`ectool --name=cros_tp tpselftest` and
`ectool --name=cros_tp tpframeget` works
Change-Id: I43db82278e556b1e6f6301fe88233fe7c4a18a14
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/515282
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
This patch enhances the Cr50 usb_updater to allow to get and set Board
ID value saved in the Cr50's INFO1 space using the earlier introduced
dedicated vendor commands.
Getting or Setting the board ID does not require establishing a
connection with the Cr50, the new option is --board_id/-i. When
specified without a parameter, the new option will cause the Board ID
to be read. When specified with a parameter, the board ID value will
be set. The parameter includes one or two values in a single string,
the values separated by a colon.
The first value is a 4 byte board ID, and the second value is the
flags field. The default flags field is set to 0xff00.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=verified that it is possible to get and set the board ID value
using usb_updater, both over USB and TPM.
verified that it is not possible to set a new board ID value is
the INFO1 space has been already programmed.
verified that it is not possible to set a board ID value which
would not allow the currently running image to start (even
though there is no run time check yet).
Change-Id: Ief175d8b2ef3177db13fa86f831914088d9447b0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/525096
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Initial version of battery.c for coral is just a straight copy from
Reef. Updated this file to include the battery being used for the
first HW build. Removed the profile override config for the starting
point as well.
BUG=b:62272260
BRANCH=none
TEST=Run 'make BOARD=coral' and verify it builds. Can't test on actual
HW yet as the boards aren't build yet.
Change-Id: I15fcf438918c03bf1d459f5806dff04c82fe8b46
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/521756
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add nucleo-f411re for testing STM32F411.
Fix registers.h to include F411 specific features.
TEST=Check uart,gpio works. Check BMI160 accel/gyro sensor works over
i2c
Install firmware with "make BOARD=nucleo-f411re flash"
BUG=b:38018926
BRANCH=none
Change-Id: I8514d1aa48e06708053e72f8d4be15738eda6cf4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/249994
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
There are only two usb_updater actions which require establishing a
connection with the Cr50: transferring the firmware image during
update and reporting the version of the running image (because the
version is reported when the connection is established).
This patch refactors usb_updater code to establish the connection only
when necessary.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=verified that 'usb_updater -c' succeeds both issued over USB and
TPM
Change-Id: I6a0c82eb440c092263d4802f124f458f148a8ab5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/525095
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The upcoming changes in usb_updater will allow to issue vendor
commands to set and get board ID value. It is also useful to be able
to corrupt the alternative RW header over Suzy-Q when Cr50 is running
a debug image.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=not yet.
Change-Id: I54ac6eb4cebd85f97407211c5212b868d61e560f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/524894
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
So far vendor command processing has been a second class citizen in
the Cr50 usb_updater: return codes were mostly ignored even when using
TPM, when using USB there was no way to communicate return codes at
all.
This patch refactors the source code to use a single function to
process vendor commands over both USB and TPM, adding proper passing
of the result codes back to the caller in both cases, retrieving the
return code from the response header when using TPM and from the first
byte of the response payload when using USB.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=verified that it is possible to update rw13, rw18 and rw20 both
over TPM and USB, which indicates that vendor commands are
properly handled.
Change-Id: I837e17b29d3b025fbca5b1ef49463cfb1729fe6c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/525094
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
To port Scarlet from firmware-gru-8785.B to master, we need
some change in naming/definition of variables/functions.
BUG=b:62307687
CQ-DEPEND=CL:524034, CL:524973, CL:524981
BRANCH=gru
TEST=build image and boot Scarlet
Change-Id: I20c1a4f311c9250a3bf1a2a5b0c70dd0f7c7e45b
Reviewed-on: https://chromium-review.googlesource.com/524987
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Set the VCCIO rail to 0.85V where it should be for Y-series parts
instead of forcing it to 1.0V. The EDS is pretty clear that pushing
this voltage higher on Y-series parts will have significant power penalty.
(up to 250mW at 0.95V)
We also don't want this rail dropping in low power mode, which shoudln't
be happening as S0ix is disabled so SLP_S0 shouldn't assert, but just in
case disable this as well.
BUG=b:35587084
BRANCH=eve
TEST=stress testing on Eve EVT units
Change-Id: I5535fe0d894f283a8d453d61101dfeb6b9287b7c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/525836
Reviewed-by: Todd Broch <tbroch@chromium.org>
When vendor commands are processed by the TPM device, the result of
the command execution is communicated through the TPM response header.
When vendor commands are sent through USB the command execution result
value is lost, as the USB reply includes only the response payload,
(if any), but not the result value.
With this patch the single byte result value is prepended to the USB
response payload. The recipient will always look for the value in the
first byte of the response to find the vendor command execution
status.
The corresponding change to the Cr50 usb_updater will remove the
response code from the payload before considering the command's return
data.
BRANCH=cr50
BUG=b:35587387,b:35587053
TEST=verified proper existing extension commands processing (post
reset, turn update on) by the new version of usb_updater and
backwards compatibility with earlier Cr50 RW version (down to
0.0.13).
Change-Id: I5c8b3ea71d3cbbaccc06c909754944b3ab04675d
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/525093
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When invoking vendor command handlers in try_vendor_command(), the
buffer containing the command is passed to the handler to communicate
the command contents and to hold the command execution return data. It
was fine when invoking vendor command handlers from the TPM stack, as
the receive buffer is 4K in size and is large enough for any expected
vendor command response.
It is different in case of USB: the command is in the receive buffer
of the USB queue, and the response data could easily exceed the
command size, which would cause corruption of the USB receive queue
contents when the response data is placed into the same buffer where
the command is.
Let's introduce a local storage to pass the command and receive the
response data from the handler. 32 bytes is enough for the foreseeable
future, should a need arise for a larger buffer, testing would result
in an error (a new error type is added to indicate insufficient buffer
space for command processing).
BRANCH=none
BUG=b:35587387,b:35587053
TEST=with the rest of the patches applied verified proper processing
of the 'Get Board ID' command for which response size exceeds the
request size.
Change-Id: I2131496f3a99c7f3a1869905120a453d75efbdce
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/525092
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Mix in board-generated entropy with the externally provided one,
which should help make the per-device secret stronger.
BRANCH=none
BUG=b:38486828
TEST=reboot; rollbackaddent Hello => works fine when USB is connected,
fails otherwise, as board-generated entropy relies on USB timing.
Change-Id: I314f44759c5f8b859913a748db95e9d42b5cdd11
Reviewed-on: https://chromium-review.googlesource.com/518609
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Mattias Nissler <mnissler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This function will be used to generate some entropy using the
Clock Recovery System.
BRANCH=none
BUG=b:38486828
TEST=make BOARD=hammer -j tests
./util/flash_ec --board=hammer --image=build/hammer/test-entropy.bin
EC console: runtest
TEST=Test fails when no USB connection is active
TEST=Test passes when USB connection is active
TEST=Pasting the values into:
tr ';' '\n' | awk 'BEGIN { e = 0; tot=16384.0 }
{ p = $1/tot; if (p > 0) { e -= p*log(p)/log(2) } }
END { print e }'
shows an entropy > 4 bits per sample.
Change-Id: I2363c7bce42c72c33ef0bf3f099d709ee9c13d13
Reviewed-on: https://chromium-review.googlesource.com/518608
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The system power monitor function, aka. PSYS, of the ISL9238 chip
is disabled by default, this patch enables PSYS monitor in the
EC driver.
BUG=b:62041842
BRANCH=none
TEST=Able to read non-zero value at the MSR of
MSR_PLATFORM_ENERGY_STATUS (0x64D) by iotools;
Also, kernel powercap driver probes PSYS domain correctly;
Such that the kernel exports the sysfs node of intel-rapl:1
Change-Id: I7a533032815e873ae74dca42ec07041be0d0f975
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/520549
Tested-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Cr50 has different gpio configurations for different boards. They cannot
be determined until board_init. We want a way to delay enabling the gpio
interrupts until the board type can be determined.
This change adds a gpio flag, GPIO_INT_DISABLE. When set gpio_pre_init
will setup the interrupt, but not enable it. board_init then enables all
of the interrupts with init_interrupts.
BUG=b:35587228
BRANCH=cr50
TEST=use 'gpiocfg' to verify the setup hasn't changed. Add print
statements to verify that gpio_pre_init skips enabling the interrupt on
any gpio that has GPIO_INT_DISABLE set
Change-Id: I91f73297ab80781b99aa82eda479ae311c13cb77
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/523808
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
