Use two suitable GPIOs to implement a simple arbitration scheme.
Each side owns one of the GPIOs, which are normally pulled high.
When one side wants to use I2C as a master, it pulls its GPIO low,
waits for a short period to make sure that the other side is not
also pulling its GPIO low, and then goes ahead with the transaction.
When the transaction is over, the GPIO is released, thus freeing the
I2C bus up for use by the other end.
For simplicity the terminolgy used here is EC for us, and AP for the
other end.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow (cannot test i2c as it is broken)
Change-Id: I97d9fbd5aba8248c8c1240baaec17db22860665c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26142
This drives the power LED for Snow (PB3) using TIM2 in PWM mode.
Since timer setup and manipulation is STM32-specific, the power LED
logic moved to to chip/stm32/power_led.c.
This also adds a "powerled" console command for testing.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=chrome-os-partner:10647
TEST=Tested on Snow with powerled command, compiled for Daisy
Change-Id: I5a7dc20d201ea058767e3e76d54e7c8567a3b83c
Reviewed-on: https://gerrit.chromium.org/gerrit/26267
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
This change fixes mutiple snow charging issues. Including:
- disable i2c host auto selection
- i2c_read8 got wrong output value
- pmu CHARGE_EN control workaround
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:11010
TEST=Only test on snow dvt with AP turned off
plug/unplug ac adapter and check charging led
check console command 'battery'
Change-Id: I29d554b3daa4cfc538bd5bf5ba5233976d381861
Reviewed-on: https://gerrit.chromium.org/gerrit/26529
Tested-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
We plan to use two of the SPI ports (NSS and MISO) for arbitration
on the i2c host interface. In preparation for this, add the extra
GPIO to the table, and change NSS to a pull-up.
BUG=chrome-os-partner:10888
TEST=manual:
build for all boards
boot on snow
Change-Id: I70962b25f371a4ca54f0ce67dcf0bc33b1cc8c47
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/26139
This change contains a basic charging loop that follows Chromium
battery charging flow. The temperature range constants, loop delay
time will be move to battery pack later.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:9724,9757,9759
TEST=manual, uart console
Plug AC adapter:
> pmu event: 0000000000001110
[batt] state discharging -> idle
[batt] state idle -> charging
> battery
I: 0x04fd = 1277 mA(CHG)a
Unplug AC adapter:
> pmu event: 0000000000000110
[batt] state charging -> idle
[batt] state idle -> discharging
> battery
I: 0xffcb = -53 mA(DISCHG)
Change-Id: Ifed594d78c0ed08c5e4821a9c8581c1a87526729
Reviewed-on: https://gerrit.chromium.org/gerrit/25618
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
And if RW B isn't enabled, it's not even linked.
BUG=chrome-os-partner:10881
TEST=on link, should be no B image, and 'sysjump B' should fail
On BDS, still should be A and B images
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: Icb2af07881cc7e28b9b877f45824486a22fde8d7
Reviewed-on: https://gerrit.chromium.org/gerrit/26116
EC computes a SHA-256 hash of its RW code on boot. Also adds host and
console commands to tell the EC to recompute the hash, or hash a
different section of flash memory.
BUG=chrome-os-partner:10777
TEST=manual
1) ectool echash -> should match what the EC precomputed
2a) ectool echash recalc 0 0x10000 5
2b) on EC console, 'hash 0 0x10000 5'
2c) results should agree
3a) on ec console, 'hash 0 0x3e000' then quickly 'hash abort'
3b) ectool echash -> status should be unavailable
4) ectool echash start 0 0x3e000 6 && ectool echash && ectool echash abort && sleep 2 && ectool echash
status should be busy, then unavailable
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I6806d7b4d4dca3a74f476092551b4dba875d558e
Reviewed-on: https://gerrit.chromium.org/gerrit/26023
At this point, EC code requires EVT. If you still have a proto1,
here's what'll break:
1) Keyboard recovery mode checks refresh key, and may read unreliably due
to proto1 silego reset circuit.
2) Lightbar may not start in the correct state.
3) EC 'hibernate' command will not work.
4) Board version may read incorrectly.
BUG=chrome-os-partner:9661
TEST=manual
1) powerbtn -> system powers on, lightbar displays proper sequence
2) version -> board version 1 (EVT)
3) power+refresh+esc -> system boots into recovery mode
4) power+refresh, then power button -> system reboots, then boots normally
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I699946e365d15ae38622b69da1a0241e72d05f61
Reviewed-on: https://gerrit.chromium.org/gerrit/26053
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This forces the fan PWM duty cycle to a fixed percentage (0-100). It's only
used for airflow testing.
BUG=chrome-os-partner:10747
TEST=manual
Using this ectool, try
ectool fanduty 0
ectool pwmgetfanrpm
ectool fanduty 50
ectool pwmgetfanrpm
ectool fanduty 100
ectool pwmgetfanrpm
You should see (and hear) the fan speed up. If you have an EC console, you
can run
faninfo
and it should show that the 'Target:' is unrelated to the 'Actual:' value.
Change-Id: Iac332fb3ba63f96726cf7f64061b3ce22d2e76fd
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25965
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If the EC shares the I2C-2 bus with the battery and the charger, we
don't want to be a master on that bus when the AP is ON and can send us
I2C messages.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=none
TEST=on Lucas DVT, check we can read battery info when AP is OFF and we
cannot when AP is ON.
Change-Id: I920a10ae9eff31bd00e4d3a5aec19d6f03b65a33
Reviewed-on: https://gerrit.chromium.org/gerrit/25959
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
add function read/write the IR3570/71 voltage regulator settings.
This includes new settings for the IR3571 to avoid the freeze observed
on new Link boards.
Currently, these settings are not flashed permanently inside the IR3571,
they are just applied at CPU startup (when the VR powered).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10171
TEST=on Link EVT, check in the kernel log that we are longer seeing the
warnings from the GPU driver and the jankyness.
on Link proto-1, check the IR chip version detection.
Change-Id: I0781f5285aac7a9f03c7c4eb953bf97273c6d404
Reviewed-on: https://gerrit.chromium.org/gerrit/24674
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Put the power LED in the right state (off, on, breathing) depending on
the AP state (off, running, suspending).
The power LED is connected to GPIO B3.
The AP suspend detection is done through GPIO A7.
(so we no longer configure it as SPI alternate function)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10647
TEST=on Lucas DVT, boot/stop the board and see the LED on and off.
Change-Id: I42121aacab35e9da7a751dc9f56bcc5af7850783
Reviewed-on: https://gerrit.chromium.org/gerrit/25880
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
This sensor doesn't provide accurate case temperature. Let's
disable thermal thresholds for the object tempearture reading from this
sensor.
BUG=chrome-os-partner:9599
TEST=Build success. System works fine.
Change-Id: I9408de59a3349f944c5e215085da93f23965ebc9
Reviewed-on: https://gerrit.chromium.org/gerrit/25824
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
These options are useful for devs, so enable them.
BUG=none
TEST=manual:
build and boot on snow; See that the taskinfo command now shows non-zero
data. Type help and see command help.
Change-Id: I6bba1cc22498924ea6f151f2fe7e819ae7560e3c
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25414
We want our friendly ASSERT() messages.
BUG=chrome-os-partner:10149
TEST=manual
Enable the option for snow, add a failing ASSERT() to the rw command
and see the a nice message is printed now.
Change-Id: I84587b209dc4a9d72310456ed2aca178256c5811
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25412
BUG=chrome-os-partner:10747
TEST=manual
Boot the CPU (the fan is off otherwise). From the EC console run
faninfo
It should show the fan duty cycle changing to maintain a specific RPM.
Run
fanduty 50
faninfo
Now the fan duty cycle should be fixed around 50%.
Change-Id: I13e4b0a7e5b2661769d64bf93342483d0419545d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25900
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add this option to make panics easier to decode.
Also put panics in a new stack for snow.
BUG=chrome-os-partner:10146
TEST=manual:
build for all boards
On snow, cause a panic and see that it is reported correctly.
Change-Id: If0b90ec0cec4ccb10041bd12bc21b342581e7f62
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24506
This change is picked from daisy change:
I70f66581d0e921c83bc2051b2a521b332e18aa50
It should be reverted after rework all dev boards to new I2C config.
Issue filed against this hack: http://crosbug.com/p/10622
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:10622
TEST=manual
Console commands:
'i2c r 0x90 4' - single byte pmu read
'battery' - double bytes battery read
Change-Id: I3185d872dc5ef6673fcd7efddf8394fe73f11813
Reviewed-on: https://gerrit.chromium.org/gerrit/25743
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This change adds battery and PMU driver to snow board configuration.
Charging is enabled in init function. EC I2C host is set to I2C2.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:10608
TEST=manual
Run uart console command 'i2c r 0x90 4'.
Change-Id: Ie09749c33c6093a46ba0ea44d42910417a67f37a
Reviewed-on: https://gerrit.chromium.org/gerrit/25501
Tested-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This change is a temperary hack. And it should be reverted after
finalize daisy board design.
The host port on daisy can be configured as I2C1 or I2C2. PMU is
connected directly to the host port, hence the host port can be
detected. This change unifies ec firmware image for different I2C
configurations.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:10612
TEST=manual
Build daisy ec firmware. Flash it to daisy boards with different
I2C port config. Check uart console commands:
'i2c r 0x90 4' - single byte pmu read
'battery' - double bytes battery read
Change-Id: I70f66581d0e921c83bc2051b2a521b332e18aa50
Reviewed-on: https://gerrit.chromium.org/gerrit/25502
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Mark Hayter <mdhayter@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
The current delay is set to 0 second, which causes unexpected shut down
whenever we get an erroneous value. Since 2 seconds is short enough for
EC to respond to CPU overheating event, let's lengthen it to 2 seconds to
prevent this.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10382
TEST=none
Change-Id: I7f971108943d74310b69b97c5f082fb2478f273b
Reviewed-on: https://gerrit.chromium.org/gerrit/25186
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Previously, the host could write to this space and corrupt the memmap data.
BUG=chrome-os-partner:10210
TEST=manual
From a root shell:
localhost ~ # io_read32 0x960
0x574e5553
localhost ~ # io_write32 0x960 0x1234
localhost ~ # io_read32 0x960
0x574e5553
That verifies that the EC is rejecting host writes on the memmap range
localhost ~ # ectool hello
EC says hello!
That verifies the host is still able to write to the user param range
Change-Id: I8c29571f439a14f308ed73f4c641264e17f944e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25115
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Perviously we have a 10-second delay for all temperature sensor. This is
not suitable for CPU temperature. Let's change that to have an option to
set the delay length for each temperature sensor. And also shorten the
delay of TMP006 sensor to 7 seconds, that of EC internal temperature to
4 seconds, and that of PECI CPU temperature to 0 second.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10233
TEST=Check EC issued warning as soon as CPU temperature reached the
threshold.
(cherry picked from commit cf24df7f3ee24eaa5dbeae3b304d11ddada9a914)
Change-Id: Id2cc4a437bde15697afe4020b6153e5d13466759
Reviewed-on: https://gerrit.chromium.org/gerrit/24694
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
This is an initial commit of tps65090 pmu driver. An empty charging
task added.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:9756
TEST=manual
When connected to a battery, the EC uart console will display
battery status on value change.
Check pmu register with 'i2c r 0x90 4'. Output should be '0x03'.
Change-Id: I99e243d203c438751af0c3647556cbf9a94e928f
A polling mode I2C master driver. Interfaces for read/write byte
and word are implemented. i2c_read_string() is currently an empty
function.
CONFIG_SMART_BATTERY added to daisy board for testing.
Move smart_battery.o back to CONFIG_SMART_BATTERY since it is not
depended on charging state machine.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:9724
TEST=manual/host commands
> battery
Temp: 0x0bad = 298.9 K (25.8 C)
Manuf:
Device:
Chem:
Serial: 0x0001
V: 0x1cb7 = 7351 mV
V-desired: 0x20d0 = 8400 mV
V-design: 0x1c20 = 7200 mV
I: 0x0000 = 0 mA
I-desired: 0x0bb8 = 3000 mA
Mode: 0x6001
Charge: 49 %
Abs: 47 %
Remaining: 2705 mAh
Cap-full: 5575 mAh
Design: 5800 mAh
Time-full: 0h:0
Empty: 0h:0
Change-Id: I9f4e9e8819955ad1b107fb3b70ac2559d9b02b55
Using low level trigger interrupt rather than falling edge is more
robust since we avoid detecting glitches or missing interrupts.
This is backward compatible with the AP software expecting falling edge.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8869
TEST=On Daisy, check we can still enter text in U-Boot console and
Chrome browser (and check interrupt count increase as expected).
Change-Id: Ide2b27f9129173530d137b5d70d998ebd8f8e669
This adds SPI transaction support, and a debug command to read a few
values from the SPI EEPROM.
Note that the SPI controller is normally *disabled* with all its I/Os
high-Z, so this will not interfere with main processor or Servo on the
SPI bus. The bus is only enabled during the SPIROM command itself.
BUG=chrome-os-partner:7844
TEST=manual
1) Reboot system
2) on EC console, 'spirom'. Should print
Man/Dev ID : 0xef 0x16
JEDEC ID : 0xef 0x40 0x17
Unique ID : 0xd1 0x61 0x44 0xb0 0x63 0x5d 0x40 0x32
Status reg 1: 0x00
Status reg 2: 0x00
Note that unique ID is, well, unique, so it won't match my value. But
it should still be something not all 0xff's.
3) Power on the system. x86 should still boot normally, indicating
that the EC isn't interfering with the SPI bus.
Change-Id: I53bf5fdbbe7a37949375d0463e30e408cc6fb6a8
Each TMP006 temperature sensor has different sensitivity factor. Let's
add a field to set different sensitivity factor for each sensor. Also
update the factors to get more reasonable temperature readings, but
still need more precise calibration.
BUG=chrome-os-partner:9599
TEST=Build and read tempearture succeeded.
Change-Id: Ib4feea3b78b71f6d37c9a02668ffa7bd9e63d390
This returns true when both HW and SW write protect are enabled.
Once WP is enabled, sysjump will be locked out.
system_is_locked() can be used to gate other dangerous-ish commands too.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7468
TEST=manual
sysinfo -> unlocked, copy A
sysjump B -> works
flashwp lock
reboot
(make sure flashinfo shows WP asserted and flash locked; note there is a
HW bug on proto1 which makes this flaky)
sysinfo -> locked, copy A
sysjump B -> fails
(remove WP screw)
reboot hard
flashwp unlock
Change-Id: I849b573675c2c1cb4c44b9a05d6973e38247ca23
Additional help messages and usage are gated by
CONFIG_CONSOLE_CMDHELP, so we can turn it on if there's space (adds
about 3KB to image size) and turn it off when there isn't.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual
1) help
2) help list
3) help gpioset
4) gpioset -> wrong number of params
5) gpioset fred 0 -> param1 bad
6) gpioset cpu_prochot fred -> param2 bad
Change-Id: Ibe99f37212020f763ebe65a068e6aa83a809a370
When the FIFO is empty, returns the last read entry not the next one.
also rewrite the FIFO index increment to generate slightly better code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8869
TEST=On Snow, in U-Boot using "stdin=mkbp-keyb" type on internal
keyboard and see the correct text.
Change-Id: I189d230053de40dd563ce672db82dd6217e545e3
This simplifies the re-flashing for stm32 based platforms.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=On Daisy, flashrom -p internal:bus=lpc -w ec.bin
Change-Id: I66860383c34110b1edf852929c244a2b682bc105
Implementation of the flash driver for the stm32f100 chip used on Snow board.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8865
TEST=On Snow board, use "flashwrite/flasherase" commands from EC console
and verify result with "rw" command.
Change-Id: Ie8b8be3d549ff9ec8c3036d5f4a97480daa5e03e
This also updates the communication protocol between the EC and the AP in a
non backward compatible way.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9614
TEST=on Daisy with updated kernel driver, use the keyboard in ChromeOS
Change-Id: I5a50e9a74b9891153a37ea79318c8a66a1b0c5ca
This cleans up I2C init and debug commands across boards.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=on link and bds:
i2cscan
lightbar run
powerbtn (to power on system)
temps (to read i2c temp sensors)
battery (to read battery)
charger (to read charger)
Change-Id: If3fb0cdb8d3178592bf68cbb2e72bc4b7f71dec5
This was used on the hybrid Badger-Lumpy systems for one-off testing.
It wouldn't necessarily work on a bare Badger board, and maintaining
it resulted in frequent build breaks.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=build link, bds, daisy; boot link and bds
Change-Id: Ib64ccad9f38d76832ab57f7254dbf32f3d5e4a5e
And start wiring to x86_power so it can detect AC state changes
(needed to enable/disable turbo).
*YES*, this compiles for BDS/Daisy now...
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9069
TEST=plug/unplug AC power and look for "x86 AC on" / "x86 AC off" in debug log
Change-Id: I8399fab9637d6635a1c615f07448fd45b86bc25f
This patch splits apart EC_INT and CODEC_INT handling for two reasons:
1. Allow other tasks to interrupt the AP without triggering
the keyboard noise suppression.
2. Allow more work to be done after a keystroke is detected but
before interrupting the AP. This is intended to prevent latency
issues with the noise suppression.
Also, Snow does not currently have CODEC_INT hooked up, so it
does not need the extra function for suppressing keystroke noise.
BUG=chrome-os-partner:9594
TEST=tested on daisy (keys still respond), locally compiled for snow.
Change-Id: I73bd42bb7263005b11724337162646092292556f
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Charging state machine doesn't need to be able to preempt everybody.
Keyboard scanning and power button should preempt, because they need
to debounce/scan at a stable rate.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=system still boots
Change-Id: Id57c680b9fa4652bc10d19270620d63788a7b269
The recovery switch is the DOWN button.
BUG=none
TEST=manual
Install on BDS, open console.
Press the reset button, it should boot to firmware A.
Hold the DOWN button, press the reset button. It should stay in RO.
Change-Id: I82f72a56df463c7cc67bde7e09f3be1545c76129
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
An upcoming CL will use the number of keyboard outputs (currently
and incorrectly called KB_COLS) in another file. So this is a good
time to clean up the naming to remove some column/row ambiguity and
move the #define to board-specific configuration.
BUG=none
TEST=locally compiled for link and daisy
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I155e3d6f2069c582517016c1116eaf668ffca86a
This would throttle proto1 systems, if it weren't for a HW bug which
means we don't have prochot control over proto1 systems at all.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8982
TEST=system still boots
Change-Id: Ie42c034141f24795ec2bfee592e194001d3cd174
BUG=chrome-os-partner:7459
TEST=manual
In the chroot:
cd src/platform/ec
make BOARD=link
The firmware image (build/link/ec.bin) is signed with dev-keys. Reflash the
EC and try it, and it should verify and reboot into RW A.
Additional tests (setting USE_RO_NORMAL, poking random values into VBLOCK_A
or FW_MAIN_A to force RW B to run, etc.) are left as an exercise for the
reader. I've done them and they work, though.
Change-Id: I29a23ea69aef02a11aebd4af3b043f6864723523
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
