Simple API to set/get the tablet mode. It can be set via lid angle
calculation or if a board has a dedicated HAL sensor/GPIO.
Merged from glados branch, add MKBP switch support.
BUG=chromium:606718
BRANCH=gru
TEST=Check with Cave that both mode works.
Reviewed-on: https://chromium-review.googlesource.com/402089
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c940f36ceabcf2425284001298f03ebdb4c3079e)
Change-Id: I2ee5130f3e0a1307ec3ea543f7a32d66bc32b31d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404915
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
We were getting occasional stack overflow and watchdog timeouts
when clearing NVMEM. Bump up the stack size a bit in the HOOKS
task, and pet the watchdog before invoking the tpm2 init
functions.
BUG=chrome-os-partner:59419
BRANCH=none
TEST=make buildall, manual
Lock the console, then unlock it. This will reboot the EC & AP,
but should never reboot the Cr50.
Before this CL, it did about half the time.
After, it doesn't.
Change-Id: I33adfeb7360bf7d146a55ef16c923a1a0416393d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/407847
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The jittery clock and trng security features require high permissions to
be initialized. In the future these initializations and the permission
level drop may be moved to RO.
This change adds permission level checks before trying to access any
registers that require high permission, so when we update RO to change
the permission RW can still function fine.
BUG=chrome-os-partner:59107
BRANCH=none
TEST=Move the permission drop to the beginning of main and verify the
system still boots.
Change-Id: I5b7cb856decd0640288ad3476f875ec9edc42635
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/405840
Let sensor be powered on in S3. It is useful for Android and if we want to
disable keyboard wakeup based on lid angle.
Allow EC to disable touchpad and not send keyboard events when lid angle
is greater than 180.
BUG=chrome-os-partner:57510,chromium:620633
BRANCH=gru
TEST=In S3, check the sensors are readable.
Check that when in S3 and lid angle is < 180 EC sends keyboard events.
Check that when in S3 and lid angle is > 180 EC does not send keyboard
events.
Change-Id: I4e7959ed37bc5dfdf9c105ecae94c314b253d77f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/406739
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In the current implementation, it's hard to tell
when led turns from amber to green.
BUG=chrome-os-partner:57079
BRANCH=None
TEST=Verify LED is green when charging w/ nearly full battery.
Also verify LED control host commands work as expected:
ectool led battery green=1 // green
ectool led battery amber=1 // amber
ectool led battery red=1 // red
ectool led battery red=0 // off
Change-Id: Ie18162fd1608a0548e25472faeca026f1995fc8d
Reviewed-on: https://chromium-review.googlesource.com/406471
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This combines stm32 and chip/g usb_i2c interfaces so they
will not diverge. Note that this fixes the chip/g implementation
to use 8-bit i2c addresses.
BUG=chrome-os-partner:57059
BRANCH=none
TEST=servod interacts with servo_micro and servo_v4
Change-Id: Ibff217d84b132556202c8a71e3d42c07d546c634
Reviewed-on: https://chromium-review.googlesource.com/405108
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
BUG=chrome-os-partner:54668
BRANCH=none
TEST=Verified SNK is detected in S0 (toggle on), S3 (toggle off),
and S5 (force sink). SRC is detect in S0 only, stays detected when
entered S3, but unplug/plug while in S3 will not re-detect until
system back in S0. When go to S5, SRC will get disconnected until
back in S0, and hotplug SRC in S5 will not get detected. Checked
power role swap with another chromebook in the above scenario also.
Change-Id: I2a487fca5cb04c45524aa3efde84fcd10ff0579e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/396918
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added necessary CONFIG options and board specific info to enable the
following sensors:
1. KXCJ9 Lid motion sensor
2. BMI160 motion sensor
3. BMI160 gyro sensor
4. BMM150 magnetometer sensor
BRANCH=none
BUG=chrome-os-partner:58894
TEST=manual
accelrate 2 10000 -> enable gyro
accelrate 3 10000 -> enable magnetometer
accelinfo on 1000 -> display sensor outputs once per second
See outputs like the following:
Base Accel=3022 , 1685 , -15925
Base Gyro=188 , -1404, -300
Base Mag=-253 , 218 , 1004
Moved eve board around and saw the readings change accordingly.
Have not tested lid motion sensor at this stage.
Change-Id: Ia658de4cbf441759482a053358230793550ef5ab
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404987
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
When sourcing current on the type-C port, set the OCP limit on the VBUS
load switch according to current dynamic capability.
(3.0A when only one port is a power source, 1.5A else)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=gru
BUG=chrome-os-partner:56110
TEST=manual: connect Caroline to Kevin with Twinkie in between,
ask Caroline to sink current through the UI.
without anything else connected on Kevin, see 3A flowing when measuring
with Twinkie ('tw vbus'), plug a dangling C-to-A receptacle dongle on
the other Kevin port and see 1.5A flowing through Twinkie.
Force the input current limit on Caroline to 3.0A and see Kevin cutting
VBUS.
Change-Id: Ib879b1ed720b20aa702c5f3643948ba0575d1193
Reviewed-on: https://chromium-review.googlesource.com/403869
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Turn off the charger BGATE when the system is hibernated to
save maximum power.
BUG=chrome-os-partner:59001
BRANCH=none
TEST=Manually verified on the Reef.
System can boot from hibernate wake sources.
Following are the power measurement values at Battery
voltage = 8.3V & temperature = 23 deg C.
a. Normal operation 540uA, 3.500mW
b. BGATE OFF 80uA, 0.592mW
Change-Id: Ia30655ccefbf0dded623246150d53b2a815df2de
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/404685
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
PD alternate mode is covered in tcpc interface. So tcpci_tcpm_init()
doesn't reset HPD. If keeping HDMI/DP type-C cable connected, doing
sysjump sets HPD signal to high while it's already high(this high comes
from previous state), then OS doesn't output to HDMI/DP monitor.
Reef Type-C port 1 follows TCPCI and has this issue.
BUG=chrome-os-partner:57689
BRANCH=none
TEST=Connect HDMI/DP type-C dongle, boot up system, OS detects HDMI/DP
monitor and extends screen to it; in console doing "sysjump RO"
or "sysjump RW", display goes out then comes back.
Change-Id: I12239a86490f29d0123fe8bad1b813d3be28d041
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/398444
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
POR has both VCC & VBUS enabled. If the port is sourcing VBUS it will
also act as sync and AC_OK pin gets enabled. Hence disable the input
to the port when sourcing.
BUG=chrome-os-partner:59020
BRANCH=none
TEST=Manually verified on Reef. Connected HoHo and AC_OK is not
enabled.
Change-Id: Ic51b81f45759d7dddb2c9744d1c24dbafd1e1293
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/404168
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Turn on CONFIG_HOSTCMD_ALIGNED and
CONFIG_COMMON_GPIO_SHORTNAMES to squeeze more
space for the upcoming sensor code.
BUG=chrome-os-partner:59084
BRANCH=gru, kevin
TEST=Check the map to confirm the size reduction
Change-Id: I7a9ca8fccf6d57a797c391dc76cacb0b929e14df
Reviewed-on: https://chromium-review.googlesource.com/403485
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The tpm is supposed to report its firmware version when
TPM_PT_FIRMWARE_VERSION_1 and TPM_PT_FIRMWARE_VERSION_2 capabilities
are requested.
This patch retrieves form the build info string SHA1s of the ec and
tpm2 repositories and returns them to the caller.
BRANCH=none
BUG=chrome-os-partner:58177
TEST=with the appropriate tpm2 source tree changes the ec and tpm
SHA1s are now reported:
localhost ~ # tpm_version
TPM 2.0 Version Info:
Chip Version: 2.0.0.0
....
Firmware Version: 0a92ec7c01b9c924
(the first half is the zero prepended 7 characters of the ec SHA1,
and the second half is the zero prepended 7 characters of the tpm2
SHA1).
Change-Id: I01e4fffdafbbdc4668342ea511ca9c4a555e20a9
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/403115
Reviewed-by: Andrey Pronin <apronin@chromium.org>
When the board is using dynamic source PDOs, we need to ensure that we
are checking the incoming sink power request against the right set of
PDOs else we might reject a valid request (e.g. with high-power source,
we need to check against the 3.0A limit if we only have one port
connected).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=gru
BUG=chrome-os-partner:56110
TEST=Connect Kevin to Caroline, ask Caroline to charge from the other
side and see it negotiating successfully a 5V/3A contract.
Change-Id: Ie1aa5746776be5946422bf07c08ae0f22faddd8c
Reviewed-on: https://chromium-review.googlesource.com/403088
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable write protect based on the type of image being built. Write
protect will be enabled on production images and disabled on dev images.
BUG=chrome-os-partner:49959
BUG=chrome-os-partner:55604
BUG=chrome-os-partner:58961
BRANCH=none
TEST=verify wp is enabled unless the image is built with CR50_DEV=1
Change-Id: Ibcd7f35fb4b33142c94e59e8c103624fce4e0b10
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/403308
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Till the charger task is initialized port is not set for the BD9995X
users and a false battery critical message is printed. Removed the
false message printed for BD9995X users to avoid confusion.
BUG=chrome-os-partner:58972
BRANCH=none
TEST=Manually tested on Reef.
False battery critical message is not printed on the EC console.
Change-Id: Iec8d0f354c4f6dc17efa9da8db38b125e57addab
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/402668
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add the default undefined state for CONFIG_ESPI and rename
CONFIG_VW_SIGNALS to CONFIG_ESPI_VW_SIGNALS.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=pass presubmit checks
Change-Id: I45242d545915c16bb46f751532a01ab937cee5f0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400032
Reviewed-by: Shawn N <shawnn@chromium.org>
This change introduces a 'fixed' endorsement seed,
and corresponding certificates. This fixed seed
is used in the endorsement process when a production
mode chip is running dev-signed firmware (or vice-versa).
The fixed certificates are untrusted by production
services, and are suitable for use in a development
environment.
BRANCH=none
BUG=none
TEST=build succeeds
Change-Id: Ifad0b361413a10f88c4977b03033a30a750cd536
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/401634
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When the kernel reads sensor data via LPC, it expects the order to be:
- ACCEL
- ACCEL
- GYRO
(other sensors data are read through EC commands)
BMI160 expects ACCEL, GYRO and MAG to be next to each other.
Reorganize motion_sensor array to fit these 2 requirements:
If BMI160 in the lid:
- BASE_ACCEL
- LID_ACCEL
- LID_GYRO
...
If BMI160 in the base:
- LID_ACCEL
- BASE_ACCEL
- BASE_GRYO
...
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: If89cf29d28b70e9a46dde8a3301a1942b3a1dd8b
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/401206
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The host command parameter and response buffers should be explicitly
aligned by the LPC/SPI/I2C drivers. But the host command handlers don't
know that, and the structs are all __packed, so the compiler generates
horribly inefficient ARM Cortex-M code to cope with unaligned accesses.
Add __ec_align{1,2,4} to force the param / response structs to be
aligned. Use it in a few structs now which were straightforward to
test. It should be added to more structs as space is needed, but that
would make this change unwieldy to review and test.
Add CONFIG_HOSTCMD_ALIGNED to enable the additional alignment.
Currently, this is enabled only for LM4 and samus_pd, so that EC code
can be tested without affecting other non-samus ToT development (none of
which uses LM4).
Fix the two handlers that weren't actually aligned (despite one of
them having comments to the contrary).
Also, add a CHROMIUM_EC define that can be used to determine if a file
is being compiled for an EC target. We need that so that we only force
structure alignment for EC binaries. On the AP side, buffers may not be
aligned, so we should not force alignment.
BUG=chromium:647727
BRANCH=none
TEST=Flash samus and samus_pd. Boot samus and run a bunch of ectool
commands (with and without --dev=1, so it tests both EC and PD).
System boots and all commands return expected results.
Change-Id: I4537d61a75cf087647e24281288392eb85f22eba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387126
Shifted pd_task debug level by 1 so that debug level 1 will
enable printing the pd state name.
Added a CONFIG flag to remove ability to change debug_level
during runtime and debug print level will be fixed.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I545813bafa8084355cedc2d8334c3aec5a2b6739
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/339935
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
