This patch adds USB_CHG_TYPE_DEDICATED to enum usb_chg_type. It's
for dedicated AC adapters like a barrel jack adapter used for Fizz.
BUG=b:65591971
BRANCH=none
TEST=make buildall
Change-Id: Ib883c97eb5e468753c73453d7dedd228547ae025
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/665327
Reviewed-by: Shawn N <shawnn@chromium.org>
lsusb scans for USB_DT_DEBUG, which produces logspam
on the cr50 console. This isn't an error, just unimplemented.
Remove the printout.
BRANCH=cr50
BUG=b:65407184
TEST=no logspam on lsusb
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: Ib4fc7105015506927f45ee02f587f97e46e1ad9b
Reviewed-on: https://chromium-review.googlesource.com/663786
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch gives the highest priority to dedicated chargers. It
means if a dedicated power supply is being connected, other power
supplies such as USB-C adapters will not be recognized as a new
charger.
BUG=b:65059574
BRANCH=none
TEST=Boot Fizz on BJ adapter. Verify plugging in Type-C adapter
doesn't shut down the system.
Change-Id: Ie49b128ae64f917a227f9081148565a3f5356212
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/655638
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch makes EC refuse PR swap when the system is powered
through the USB-C port because switching from SNK to SRC will
cause the system to shut down.
BUG=b:65481832
BRANCH=none
TEST=Boot Fizz on USB-C and BJ.
Change-Id: I52c5813adc1ea9b4e69e65599c1794ae43192a1e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/655643
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
1. Add a new config option CONFIG_PORT80_PRINT_IN_INT which is
disabled by default to disable printing of port80 messages in
interrupt context.
2. If CONFIG_BRINGUP is defined, redefine CONFIG_PORT80_PRINT_IN_INT
to enable printing of port80 messages in interrupt context for boards
that are in bringup phase.
3. If print_in_int is disabled, add a deferred call to dump port80
buffer to EC console 4 seconds after the last port80 message is
received.
BUG=b:64196191
BRANCH=None
TEST=Verified following:
1. make -j buildall
2. Port80 messages are not printed by default on Soraka
3. Port80 buffer is dumped 4 seconds after last port80 message, if
BIOS is stuck for 4 seconds, in recovery mode and when reboot from AP
console.
4. Boot time on soraka went down from ~1.59seconds to ~1.45 seconds in
EC reboot case (savings of ~140ms).
Change-Id: I9aee0987765f905b4ac49d04ffc54d71ee3a04f9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/661880
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Messages generated using the CPRINTS macro include a newline in the
end by design, no need to explicitly include it in the message.
BRANCH=cr50
BUG=none
TEST=verified that the message is printed without the extra newline
Change-Id: I01994bcb95c78e2deaa2dc3617bea9ca8a6d1381
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/663668
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The modified CRC8 implementation didn't detect some errors. For
example, using the modified CRC8: CC5QQLALU and DC5QQLALU calculates
to the same value.
BUG=b:37952913
BRANCH=none
TEST=make buildall
Used online CRC-5-USB calculator to test several values against
this implementation.
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: I5a17941e25691872a25b41525f65f36e2ed1d4fa
Reviewed-on: https://chromium-review.googlesource.com/660812
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Michael Tang <ntang@chromium.org>
The manufacturer names for the Robo LG and Simplo batteries were
incorrect. Both of them had an '/011' which is not actually part of
the name. This has been fixed. In addition, the ship mode command
needs to be 0x0000 followed by 0x1000, but it was using 0x0000 and 0x0001.
BUG=b:64821365
BRANCH=None
TEST=manual
Tested Celpext, SMP, and LG batteries with EVT systems. Verified that
'cutoff' from EC console and 'ectool batterycuttof' from AP console
caused the battery cutoff to take effect. Also verified the
manufacturer name from the batteries matched the what's stored in the
battery info table.
Change-Id: I48369da4d2c6137b50614b003df57a359a49c4f4
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/662137
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We use address 0x80000000, which is not mapped to anything in
STM32F0 address space.
BRANCH=none
BUG=b:63993173, b:65188846
TEST=./usb_updater2 -p 144.0_2.0.bin
CQ-DEPEND=CL:601814
Change-Id: I9a9044d29ebe058d3792dc984cac4051a005cf8f
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/597468
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Provides touchpad_update_write functions that fw_update.c uses
to update the FW over the USB updater interface.
BRANCH=none
BUG=b:63993173, b:65188846
TEST=./usb_updater2 -t touchpad.bin
CQ-DEPEND=CL:593373
Change-Id: I5246cbfa65311cd6f0b1872f9bbc164f3a972153
Signed-off-by: Chun-Ta Lin <itspeter@google.com>
Reviewed-on: https://chromium-review.googlesource.com/601814
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Chromebox ECs performs EFS: verifying firmware before the AP boots.
This patch updates host commands which are required for the EFS.
The change includes:
* Update EC_CMD_FLASH_REGION_INFO to accept EC_FLASH_REGION_UPDATE
* Update EC_CMD_VBOOT_HASH to accept EC_VBOOT_HASH_OFFSET_UPDATE
When EC_FLASHS_REGION_UPDATE is specified, EC_CMD_FLASH_REGION_INFO
returns the slot which currently is not hosting a running RW copy.
When EC_VBOOT_HASH_OFFSET_UPDATE is specified, EC_CMD_VBOOT_HASH
computs the hash of the update slot. This hash covers the entire
region, including the signature at the end.
This patch undefines CONFIG_CMD_USBMUX and CONFIG_CMD_TYPEC
for gru to create space.
BUG=b:65028930
BRANCH=none
CQ-DEPEND=CL:648071
TEST=On Fizz, verify:
1. RW_B is old and updated by soft sync. RW_B is activated and
executed after reboot. System continues to boot to OS.
2. RW_A is old and updated by soft sync. RW_A is activated and
executed after reboot. System continues to boot to OS.
Change-Id: I9ece907b764d07ce94054ba27996e048c665a80a
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648448
In case of battery cut-off on Soraka, there is a battery requirement
that AC power should not be applied for at least 9 seconds after the
cut-off is performed. Performing battery cut-off when battery is at
critical level results in a bad user experience if the user connects
AC power within the 9-second window. Thus, instead of performing a
battery cut-off, make the EC hibernate in critical battery conditions.
BUG=b:64703097
BRANCH=None
TEST=make -j buildall
Change-Id: I40827faccd52c8628b69773cb22ccc6ed19915ed
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656609
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
If the PD state machine remains in SRC_DISCOVERY for an extended period
of time, it's likely that a non-PD USB peripheral is attached. In this
case, we don't need to inhibit deep sleep, since we're not likely to
receive PD packets.
This change will cause us to enter deep sleep slightly more
aggressively, not inhibiting deep sleep until source caps are received
or replied with GoodCRC by the port partner. We can accommodate
additional task latency up to this point, since the spec calls for
source caps to be sent up to 50 times before failure.
BUG=b:35582718,chromium:763002
TEST=Test with `sleepmask 1` on kevin.
- Go to S3 with USB-C flash drive plugged, verify `sleepmask` shows 0.
- Go to S3 with zinger + USB C flash drive plugged
- Unplug zinger, verify `sleepmask` shows 0.
- Plug zinger, verify PD negotiates to 20V @ 2A.
- Plug OEM kevin charger, verify same.
BRANCH=gru
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib8e1bc94bdbcfddea004d572edf1ccadc8c8c1ce
Reviewed-on: https://chromium-review.googlesource.com/655919
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reworked suzy-q and suzy-qable all provide Rp, so there is no need for
special detection handling in S5. Also, CONFIG_USB_PD_QUIRK_SLOW_CC_STATUS
is no longer relevant, since we no longer take special action when VBUS
is seen without Rp.
BUG=chromium:737755
BRANCH=None
TEST=On kevin, verify reworked suzy-q and suzy-qable are detected in S5.
Also, verify zinger works in S5 on reef.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I50967bd6415d964a038b2e7d134374132eda11ec
Reviewed-on: https://chromium-review.googlesource.com/656067
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Due to the power timing v2 had defined the S3_USB_WAKE,
We need enable the PP900_S0 for power timing v2.
Fixes: 098bde322f ("power/rk3399: Don't turn off the pp900_s0 during s3")
CQ-DEPEND=CL:647053
BRANCH=none
BUG=b:65270978
TEST=build and bring up on scarlet board
Change-Id: If8aedc03d54e9f4953ab994da426272137440d36
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/656858
Tested-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Servo / Suzy-Q related debugging methods is a big challenge
in factory especially after servo debug header is removed.
Expose some information to OS from EC will do a great help
for massive production.
+ expose charge/battery related state to ectool
1. chg_ctl_mode
2. manual_mode
3. battery_seems_to_be_dead
4. battery_seems_to_be_disconnected
5. battery_was_removed
6. disch_on_ac (learn mode state)
BUG=b:65265543
BRANCH=master
TEST=`ectool chargestate param 0x20000~0x20006 get correct state`
Change-Id: Ic2ed38e2eb9def01be29729fa1fe1959eb73fe43
Signed-off-by: Ryan Zhang <ryan.zhang@quanta.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/646412
Reviewed-by: Shawn N <shawnn@chromium.org>
Minor cleanup to the 'ccd help' command.
Add 'ccd get' as a clearer alias to print the config.
Change CONFIG_CMD_CCDDISABLE to CONFIG_CMD_CCD_DISABLE to indicate
that it's a sub-command for 'ccd'.
BUG=b:65407395
BRANCH=cr50
TEST=manual
ccd -> see clue for 'ccd help'
ccd help -> see 'get' command
ccd get -> prints config
ccd disable -> error (config option isn't defined by default)
Change-Id: Icbcaa178171ca948cfaae58ab1a1e73ab3d95243
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/654380
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
For historical reasons, CCD, reset, and power button control were
scattered around several files. Consolidate the code in more sensible
(in retrospect) places.
No functional changes, just moving code.
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50
Change-Id: Ic381a5a5d0627753cc771189aa377e88b81b155e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/653766
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
SYSTEM_IMAGE_RW_B hasn't been globally treated as a RW copy.
This change makes EC treat it also as a RW copy.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: Iae5a9090cdf30f980014daca44cdf8f2a65ea1f2
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/656337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We found a potential risk that voltage might fed back into EC Vcore.
If the CC pin voltage detector is enabled and there is an unexpected
voltage source over 3.3v fed back into EC, this might cause an
exception or unknown reset.
BRANCH=none
BUG=none
TEST=The voltage detector is enabled after vconn is offed.
Change-Id: I78975fa195eef0b96056a39ee3c6d92c3bb6f8c0
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/647673
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We disable i2c interface immediately after stop bit is set.
This might caused bus busy bit of status register unable to clear
(bus busy bit will be set at start condition and cleared at
stop condition).
So the next transaction, we won't get a good state to start.
This change also fix incorrect stop bit for write transaction:
IT83XX_I2C_CTR(p_ch) = xx
BRANCH=none
BUG=none
TEST=Ensure i2c interface is disabled after i2c stop condition.
Change-Id: I5416bfcef3f95357c6771dead6b0611b908f787e
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/645407
Reviewed-by: Randall Spangler <rspangler@chromium.org>
- This CL adds the infrastructre needed to support different battery
types for the Coral project.
- This includes adding a battery_check_disconnect common function
that's used folloiwng battery cutoff events to ensure that the
battery is able to provide power before reporting it as present.
When the battery is not present, there is a 1 second delay used
before allowing the battery to report as present. This specific
change is motivated by an issue discovered on Eve which resulted in
H1 power rail issues and could lock up the H1.
https://chromium-review.googlesource.com/c/592717https://chromium-review.googlesource.com/c/585837
- This includes a battery_cutt_off_battery common function that can
be used by all battery types using the register and regiseter data
required for each battery's ship mode.
BUG=b:64772598,b:64728711,b:64821365
BRANCH=None
TEST=manual testing on Coral proto with Sanyo battery and tested on
Nasher with BYD and LGC-LGC.593 batteries. Verified that battery
cutoff command via EC console works. Verified that can start up as
expected following battery cutoff. Also tested battery cutoff
initiated by removing the battery from the system while it's powered
up. Also tested 'ectool batterycutoff at-shutdown' from the AP console
and verifed that battery cutoff was successful following 'apshutdown'
on the EC console.
Change-Id: I9d884efa9d64fb94d46447feb028c5d9ae82a20f
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/627496
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Default setting of embedded flash's clock is 24 or 32 MHz
and PLL is 48 or 96 MHz correspondingly.
And it8320 supports e-flash clock up to 48 MHz,so we add
a new config option to support it.
BRANCH=none
BUG=none
TEST=Run FAFT with e-flash 48MHz and test results are passed.
Change-Id: I096ae3abc8fec9bd7e0556c57605e87a31ac3b07
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/645466
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In USB FS on a bulk/interrupt endpoint, the transactions normally toggles
between DATA0 and DATA1 PIDs.
After a USB suspend/resume cycle, we need to restart from the PID we
were at before suspend.
In our current code, when going to deep-sleep during USB suspend, we are
re-initializing everything when the MCU restarts at each resume. So we set
implicitly the PID to DATA0. The USB Hardware IP just silently discards the
packet when the PID of an incoming OUT packet is not matching the
expectation in the endpoint register.
In order to preserve DATA PIDS, record the state of the PID toggling on
each endpoint when going to deep-sleep and restore it during the USB
initialization.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual, plug a HG proto2 on a Linux host machine and enable
'auto-suspend' for this USB device. Let it go to sleep and wake-it up by
sending a U2FHID request. Repeat the process several times and see that
the key answers every time (while it was failing after the second cycle
before).
Change-Id: I75e2cfc39f22483d9e9b32c5f8b887dbafc37108
Reviewed-on: https://chromium-review.googlesource.com/655238
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
It is necessary to be able to access Cr50 using usb_updater without
stopping trunksd services. This patch adds another option for
usb_updater to communicate with Cr50, using the trunks_send command.
A new command line option '-t' is added to allow to choose the new
interface.
When communicating over trunks_send the same processing is used as
when communicating over /dev/tpm0, just instead of talking to the
hardware device, popen() function is used to run trunks_send --raw
command and to gain access to its console output.
BRANCH=none
BUG=none
TEST=ran various commands using the new '-t' option:
# ./usb_updater -t /opt/google/cr50/firmware/cr50.bin.prod
read 524288(0x80000) bytes from /opt/google/cr50/firmware/cr50.bin.prod
start
target running protocol version 6
keyids: RO 0xaa66150f, RW 0xb93d6539
offsets: backup RO at 0x40000, backup RW at 0x4000
sending 0x32288 bytes to 0x4000
-------
update complete
reboot requested
image updated
[reboot...]
# ./usb_updater -t -f
start
target running protocol version 6
keyids: RO 0xaa66150f, RW 0xb93d6539
offsets: backup RO at 0x40000, backup RW at 0x4000
Current versions:
RO 0.0.10
RW 0.0.23
Change-Id: I9c7481c30c2f6908e0d1ac4f204654d2fd1b3b2e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/634629
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
The PP900_LOGIC can't be disabled for now, maybe we will disable it in
later, since the ATF hadn't done it.
In order to the suspend to resume function is fine, let's keep it first.
BRANCH=none
BUG=b:65270978
TEST=build and run the S2R stress tests on nefario board
Change-Id: I932ee2b7667115df7516729f60faa71598f36d93
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/647053
Reviewed-by: Shawn N <shawnn@chromium.org>
Servo v4 monitors the SBU lines on USB-C connects in order to determine
which direction to set the orientation of the SBU mux. However, when
there's traffic on the lines, for example when the EC is rebooting, it
can lead to the wrong conclusions and terminate the USB connection.
This commit adds a CCD keepalive console command.
Additonally, when the Type-C cable is unplugged from the DUT for at
least 900ms, the CCD keepalive will be cleared. This is such that if
the cable is unplugged and then replugged in a different orientation,
the detection will still work.
BUG=b:64903997
BRANCH=servo
TEST=Flash servo_v4; `keepalive enable`. Run `dut-control
power_state:reset` > 100 times and verify that the USB connection stays
alive.
Change-Id: I5c8f9ab3361d4f52f906161ab5da471a36725a4e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/647031
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Somewhere this lost a call to ccd_save_config(). Put that back.
Also, make it so 'ccd testlab' prints the current state.
BUG=b:65407184
BRANCH=cr50
TEST=manual with CR50_DEV=1 image
ccd oops
ccd testlab -> disabled
ccd testlab enable
ppresence (or tap power button)
ppresence
ppresence
ccd testlab -> enabled
reboot
ccd testlab -> enabled
ccd lock
ccd -> state=locked
ccd testlab open
ccd -> state=opened
ccd testlab disable
ppresence (or tap power button)
ppresence
ppresence
ccd testlab -> disabled
reboot
ccd testlab -> disabled
ccd testlab open -> acces denied
Change-Id: Iffdd84e8e0df3222b8762638b8a613f146c15f13
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/653765
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously, all CCD config commands were their own distinct commands.
This led to accidental side-effects when someone would type 'ccdlock'
thinking it would print the lock state when it would actually lock the
device.
Make them all sub-commands of 'ccd'. So, 'ccd lock', not 'ccdlock'.
Just 'ccd' by itself will print the current config.
No changes to how the sub-commands themselves work.
BUG=b:65407395
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
gpioget # make sure GPIO_BATT_PRES_L=0
ccd help # prints help
ccd lock # lock, because CR50_DEV=1 builds start unlocked
ccd # locked, flags=0, all capabilities default
ccd pass # access denied (we're locked)
ccd reset # access denied
ccd set flashap always # access denied
ccd unlock
ccd # unlocked
ccd pass foo
ccd # flags=2 (password set when unlocked)
ccd set flashap always # access denied
ccd set uartectx unlesslocked
ccd # yes, uartectx permission changed
ccd lock
ccd unlock # fails without password
ccd unlock bar # wrong password
ccd unlock foo # busy
(wait 3 sec)
ccd unlock foo
ccd reset
ccd # no password, flags 0, capabilities all default
ccd open # requires physical presence; tap power or use 'pp'
ccd set uartgsctxecrx unlesslocked
ccd set batterybypasspp ifopened
ccd pass baz
ccd # password set, flag 0, ccdset changes worked
ccd unlock
ccd reset
ccd # uartgsctxecrx back to ifopened, password still set
ccd open baz # still requires physical presence
ccd set opennolongpp always
ccd lock
ccd open baz # no pp required
ccd set unlocknoshortpp unlesslocked
ccd lock
ccd open baz # short pp sequence required (3 taps)
ccd lock
ccd unlock baz # short pp sequence required
ccd open baz # pp not required
ccd set unlocknoshortpp always
ccd lock
ccd testlab open # access denied
ccd testlab enable # access denied
ccd unlock baz
ccd testlab open # access denied
ccd testlab enable # access denied
ccd open baz
ccd testlab enable # requires short pp
ccd # flags 1
ccd reset
ccd # no password, flags=1, caps all default
ccd lock
ccd testlab open
ccd # opened
ccd testlab disable # requires short pp; let it time out
ccd # still opened, flags=1
ccd lock
ccd oops # backdoor in CR50_DEV images to force-reset CCD
ccd # opened, flags=0, all defaults (yes, oops wipes out testlab)
ccd reset rma
ccd # flags = 0x400000, everything but GscFullConsole always
ccd reset # back to flags=0, all default
Change-Id: Ib2905cb7cbeb79a7f4d0fb44151bfd53af361e2e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/653719
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, the Cr50 state machines (EC, AP, RDD, bitbang, etc.) manage
their own enabling and disabling of the ports (UART, SPI, etc.) This
is tricky because the rules for when ports should be enabled are
non-trivial and must be applied in the correct order. In additionl
the changes all need to be serialized, so that the hardware ends up in
the correct state even if multiple state machines are changing
simultaneously.
Consolidate all of that into chip/g/rdd.c. The debug command for it
is now 'ccdstate', which just prints the state machines. This will
allow subsequent renaming of the 'ccdopen', etc. commands to 'ccd
open', etc.
Also include UART bit-banging into that state which must be
consistent. Previously, it was possible for bit-banging to leave UART
TX connected, instead of returning it to the previous state.
Use better names for CCD config fields for UART. I'd had them backwards.
BUG=b:62537474
BRANCH=cr50
TEST=manual, with a CR50_DEV=1 image
1) No servo or CCD
Pull SERVO_DETECT low (disconnected)
Pull CCD_MODE_L high (disabled)
Pull EC_DETECT and AP_DETECT high (on)
Reboot. RX is enabled even if cables are disconnected so we buffer.
ccdstate -> UARTAP UARTEC
Pull EC_DETECT low.
ccdstate -> UARTAP
Pull EC_DETECT high and AP_DETECT low.
ccdstate -> UARTEC
Pull AP_DETECT high.
ccdstate -> UARTAP UARTEC
2) Servo only still allows UART RX
Pull SERVO_DETECT high (connected).
ccdstate -> UARTAP UARTEC
3) Both servo and CCD prioritizes servo.
Pull CCD_MODE_L low (enabled).
ccdstate -> UARTAP UARTEC
Reboot, to make sure servo wins at boot time.
ccdstate -> UARTAP UARTEC
Bit-banging doesn't work when servo is connected.
bitbang 2 9600 even -> superseded by servo
bitbang -> disabled
ccdstate -> UARTAP UARTEC
4) CCD only allows more ports and remembers we wanted to bit-bang
Pull SERVO_DETECT low.
ccdstate --> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI
Reboot and see we don't take over servo ports until we're
sure servo isn't present.
ccdstate --> UARTAP UARTEC (for first second)
ccdstate --> UARTAP+TX UARTEC+TX I2C SPI (after that)
5) Bit-banging takes over ECTX
bitbang 2 9600 even
bitbang -> baud rate 9600, parity even
ccdstate -> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate -> UARTAP+TX UARTEC+TX I2C SPI
6) Permissions work. Allow easy access to full console and ccdopen:
ccdset OpenNoTPMWipe always
ccdset OpenNoLongPP always
ccdset GscFullConsole always
Default when locked is full AP UART EC RO, no I2C or SPI
ccdlock
ccdstate -> UARTAP+TX UARTEC
No EC transmit permission means no bit-banging
bitbang 2 9600 even
bitbang -> disabled
ccdstate -> UARTAP+TX UARTEC
But it remembers that we wanted to
ccdopen
ccdstate -> UARTAP+TX UARTEC+BB I2C SPI
bitbang 2 disable
ccdstate -> UARTAP+TX UARTEC+TX I2C SPI
Try turning on/off permissions
ccdset UartGscTxECRx always
ccdlock
ccdstate -> UARTAP+TX UARTEC+TX
No read means no write either
ccdset UartGscRxECTx ifopened
ccdlock
ccdstate -> UARTAP+TX
ccdopen
ccdset UartGscRXAPTx ifopened
ccdlock
ccdstate -> (nothing)
Check AP transmit permissions too
ccdopen
ccdset UartGscRxAPTx always
ccdset UartGscTxAPRx ifopened
ccdlock
ccdstate -> UARTAP
Check I2C
ccdopen
ccdset I2C always
ccdlock
ccdstate -> UARTAP I2C
SPI port is enabled if either EC or AP flash is allowed
ccdopen
ccdset flashap always
ccdlock
ccdstate -> UARTAP I2C SPI
ccdopen
ccdset flashec always
ccdset flashap ifopened
ccdlock
ccdstate -> UARTAP I2C SPI
Back to defaults
ccdoops
Change-Id: I641f7ab2354570812e3fb37b470de32e5bd10db7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/615928
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
export_taskinfo is a utility used by the stack analyzer.
This patch makes sure it will be recompiled when the EC code changed.
BUG=none
BRANCH=none
TEST=make BOARD=eve -j && make BOARD=eve analyzestack
Add a fake task in board/eve/ec.tasklist
make BOARD=eve -j && make BOARD=eve analyzestack
The fake task shows in the report
Change-Id: I57c2700610680975571d254e0059571556f184fe
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/651449
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There is no point in updating the Cr50 to an image which will not be
allowed to run due to board ID settings mismatch.
This patch modifies the prototype of check_board_id_mismatch() to
allow to pass to this function an arbitrary pointer to an image
header, so that the function can check not only the image in the flash
memory, but also the image which just arrived over the line.
The contents_allowed() function now checks if the new image is
compatible with the Board ID value in Info1 and rejects the new image
if there is a mismatch.
BRANCH=cr50
BUG=none
TEST=tried updating a Cr50 to an image which is incompatible with the
Info1 fields contents. The update attempt is rejected. Verified
that updating to a compatible image still works as designed.
Change-Id: I3d6c16df11fcabd05888f3cbf5e9a81dc51fe66f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/650812
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Make the size of extra stack needed by exceptions configurable.
It can be set in the annotation file.
BUG=chromium:648840
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
make BOARD=elm SECTION=RW \
ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \
analyzestack
Change-Id: Idf2a59650dd20257a0291f89d788c0c83b91a7c9
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/649454
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
There are lots of invalid paths have common segments.
In this patch, each vertex of an invalid path can be a function set.
Examples can be found in extra/stack_analyzer/example_annotation.yaml
BUG=chromium:648840
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
make BOARD=elm SECTION=RW \
ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \
analyzestack
Change-Id: Ib10d68edd04725af4d803f54f7e208e55d574c7d
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/649453
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When checking if the new contents are allowed the updater can reject
the image for different reasons, let's make it possible to pass the
actual rejection reason to the caller of the contents_allowed()
function.
BRANCH=cr50
BUG=none
TEST=verified that attempts to update to an older image are still
being rejected with the proper error code (as generated by
contents_allowed() now).
Change-Id: I24ac7671c4f461ec089f272581723ec2c3a232ff
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/650811
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Add the extra dependencies to "deps-y" and include it in "deps".
BUG=chromium:761922
BRANCH=none
TEST=Add "$(info $(deps))" before "-include $(deps)" in Makefile.rules
make BOARD=eve utils | grep "build/eve/util/usb_pd_policy.o.d"
There is "build/eve/util/usb_pd_policy.o.d"
Change-Id: I77670a8e90a1a913943fcba143402318aaf7d274
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/649455
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In order to prevent keeping the CSAE bit at 1 forever impacts the eSPI
performance, the npcx driver enables host access wakeup functionality
before ec enters deep sleep or wfi. But this bypass also should be added
in __idle() of core/cortex-m/task.c if CONFIG_LOW_POWER_IDLE is
disabled.
This CL also narrows the bypass only when host interface is eSPI.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Disable CONFIG_LOW_POWER_IDLE
functionality on poppy and use following script "count=0; while :;
do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep
1; count=$((${count}+1)); done" to test eSPI performances over 300
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: I8b6b69e37318208c185747151c06b3e6bdfd2f4e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/644967
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
