Very similar to CL:424846, enable sensor FIFO, accel interrupt.
BUG=chrome-os-partner:61098
TEST=Not test on actual hardware.
BRANCH=none
Change-Id: Ie5c7304fcc00919cce62ed47a548104e8d0ac454
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426880
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Fix cros_workon_make --board eve chromeos-ec --install
The test phase would fail at compilation because TASK_ID_MOTIONSENSE
is not defined.
BUG=chromium:61748
TEST=Check that with the change cros_workon_make pass.
BRANCH=none
Change-Id: Ib50aad492e9cfb38c56a3c6c8d4f2bb2b297ea85
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426879
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Callers may not need computation of the public key.
Making this optional speeds this routine up.
Cr50 never passes in NULL for any argument, so is not affected.
BUG=none
TEST=build
BRANCH=none
Change-Id: Ia0077a35064f53b53f51867254aaa51eac6c55d8
Reviewed-on: https://chromium-review.googlesource.com/427058
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
We don't need to loop and waiting ADC's data valid flag
after the change was made.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. We build a EC binary for PD EVB (declared two ADC channels
for VBUS measurement of PD task and priority is highest)
2. Use console command "adc" continually to read ADC channels
and check if any error.
Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b
Reviewed-on: https://chromium-review.googlesource.com/421307
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When depthcharge invokes a Host command that needs EC to access
flash, the response is delayed by approx 150 ms because EC is
busy with another flash operation to determine size of RW image
for computing hash. We can eliminate this delay and also speed up the
flash operation by using the same mechanism that is used for mec1322
based designs which also use external SPI flash.
The changes are:
a) We access 4 bytes from SPI flash at a time instead of a single byte
b) We split flash accesses into smaller parts which means that mutex lock
is acquired for a short duration.
BUG=chrome-os-partner:59875
BRANCH=none
TEST=make buildall -j
After sysjump to RW, in EC Log the "hash start" is printed approx
120 ms earlier.
Change-Id: Icb633379c992e795ba40eaf54fe9ec31747d4be6
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/426016
Reviewed-by: Shawn N <shawnn@chromium.org>
We have hard timing requirements once we begin to output our host
command response, and most of the time is spent copying our response to
OBUF. Optimize our copy loops to remove needless increments and to avoid
needless struct dereference.
BUG=chrome-os-partner:61304
BRANCH=gru
TEST=Manual on kevin, verify the following performance metrics:
Time spent in shi_fill_out_status(): Was 40us, now 28us
Time spent in shi_write_half_obuf(): Was 60us, now 31us
Time spent in shi_write_first_pkg_outbuf:
Was 90us, now 37us (bad case)
Was 26us, now 16us (better case / less data copied)
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I04075c92744eeefe8f2be009e6598718c45143c4
Reviewed-on: https://chromium-review.googlesource.com/425330
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Follow reef setting.
This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
________ ________
SLP_S0 |______________________|
_____ ________
HC |___________________________|
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: I1073b5cb2cbb8492cec0967f2a6004c5ce368ecb
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426558
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Follow reef setting.
On the bd9995*, back boosting may occur when actual battery voltage
drops below VBAT register setting. Maintain the VBAT register at the
battery-requested charge voltage even when not charging to ensure the
bd9995* doesn't become a back boosted animal.
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: Ie7aaffc38fef65721886d00be3d6827e9e124efa
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/426499
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When we switch to a state where the sensor is not powered,
we don't call set_data_rate(0), because we may trigger an i2c/spi access
to a sensor already powered off. It has the side effect to leave
data->odr to the last set sensor frequency.
When we init the BMI160, it starts in suspend mode. We will set it to
normal mode only if data->odr is 0. Therefore, we must set odr to 0 in
the init routine.
BUG=chrome-os-partner:61502
BRANCH=reef,kevin
TEST=On reef, without this change. When going to S5 (shutdown -h 0) and
power back up, sensor is stuck (on EC, accelread 1 reads old value).
With this fix, sensor is active and working.
This fix a regression due to CL:411964.
Check others driver do not check odr for setting suspend/normal mode.
Change-Id: Ibc7519d49e55a0b43b4c12ed545bd75ab0260766
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426766
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It is not proper to use SET_BIT macro to clear a "write 1 to clear" bit
in a register. It will also clear other bits if they are also set.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; boot up on gru, run ectool stress test for a while
without problem.
Change-Id: I0c5a850e85e41820515b1a8f15bb43d77397737f
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/425589
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
HW change led power rail, so the battery led and logo led will
light in hibernate state. I modify battery led pin (gpio84,
gpioC4) and logo led pin (pwm3) setting in hibernate, let them
will not light in hibernate.
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: I6c75694cf92fe05b5afc0d2a399e15c5bff6b7f8
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/425563
Commit-Ready: Bruce Wan <Bruce.Wan@quantatw.com>
Tested-by: Bruce Wan <Bruce.Wan@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- CHG port can connect as SNK at different voltage levels
- DUT port presents as SNK only
- DUT port uses fixed polarity since it has a fixed cable
- Not supporting ALT or ALT_DP modes in terms of svdm messages at
this point.
- No support yet for USB mux.
BUG=chromium:571476
BRANCH=None
TEST=Manual
CHG port: Tested with Zinger and Plankton and 5/12/20V VBUS levels.
DUT port: Tested against Reef and verified that port reached SNK_READY.
Change-Id: Ib645872790912f9e0a0d4adddc10345a59145d3e
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424413
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
change inline assembly for fsqrt and fabs
BUG=none
BRANCH=None
TEST=`make buildall -j`
1. Compare sqareroot(2) from calculator and from sqrtf(2.0f) by multiplying
1.0 x 10E8 for both values to convert int32_t and check the difference.
2. read timestampt before and after 'sqrtf()' and calculate execution
time.
Change-Id: I62694d8b084a3a74040dc298354b4fd685e77729
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/404927
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
To avoid SRAM footprint, let's use dynamic memory allocation in
nvram_vars. No one is using this module yet, but the cr50 use case is
coming up.
BRANCH=none
BUG=chrome-os-partner:61107
TEST=make buildall -j passes
Change-Id: I21534430217ad387a3787fcc127da596a1b48e03
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/426088
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Extracted Intel x86 power sequencing common code from skylake.c
and apollolake.c to implement common code for power sequencing.
BUG=chrome-os-partner:59141
BRANCH=none
TEST=make buildall -j
Reef can boot to OS. S3, S5, hibernate are working.
Change-Id: I73478fcabb24d6d98cd474bae3586ce5b02986fe
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/406486
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit adds a "spoof" mode feature to the motionsense stack. It
allows the user to arbitrarily set the outputs of the sensor in order to
"spoof" the readings of the sensor. This can be useful in emulating
tablet mode or device rotations. A command is available from the EC
console named `accelspoof` and there is a corresponding motionsense
command in ectool called `spoof`.
The usage is as follows:
- EC console
> accelspoof [id] [on/off] [X Y Z]
- ectool
# ectool motionsense spoof -- [id] [0/1] [X Y Z]
If on or off(or 0/1) is not specified, the current spoof mode status of
the sensor is returned. If on is specified, but no components are
provided, the sensor will lock the current values and provide those as
the spoofed values. If the components are provided, those will be used
as the spoofed values.
BUG=chromium:675263
BRANCH=cyan,glados,gru,oak
TEST=Flash a DUT with accels. From AP console, run `ectool motionsense
lid_angle` in a loop, use 'accelspoof' EC console command to set spoofed
values. Verify that the angle is fixed regardless of the actual angle
of the DUT.
TEST=Flash a DUT with accels. From AP console, use `ectool motionsense
spoof` to spoof values and verify that `ectool motionsense` reflects the
spoofed values. Test with both provided component values and no
component values.
Change-Id: Ie30688d22f38054e7243b1af493a3092b2cdfb72
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/421280
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
AverageTimeToFull() and AverageTimeToEmpty() are the predicted time based
on the AverageCurrent(), these do not reflect the instant time of charging
or discharging. Hence we observe huge number of time (1092h because
register has 65535) to full time when battery starts accepting current
upon reaching 100%. To overcome this issue, explicitly checking if the
AverageTimeToFull() and AverageTimeToEmpty() register values are updated
with the valid data.
BUG=chrome-os-partner:60802
BRANCH=none
TEST=Manually tested on Reef. Charge the battery to 100%, once the
battery starts accepting current again observed time to full
is not huge number.
Change-Id: I6d6c21b72ab824dbe47e44e1e77f1c5319ac2720
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/425324
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chromium:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
BOARD with host commands and private host commands
0004d0ec R __hcmds
0004d0ec R __host_cmd_0x00000x0000
0004d0f8 R __host_cmd_0x00000x0001
0004d104 R __host_cmd_0x00000x0002
0004d110 R __host_cmd_0x00000x0003
0004d11c R __host_cmd_0x00000x0004
0004d128 R __host_cmd_0x00000x0005
0004d134 R __host_cmd_0x00000x0007
0004d140 R __host_cmd_0x00000x0008
0004d14c R __host_cmd_0x00000x000a
0004d158 R __host_cmd_0x00000x000d
0004d164 R __host_cmd_0x00000x0010
0004d170 R __host_cmd_0x00000x0011
0004d17c R __host_cmd_0x00000x0012
0004d188 R __host_cmd_0x00000x0013
0004d194 R __host_cmd_0x00000x0015
0004d1a0 R __host_cmd_0x00000x0016
0004d1ac R __host_cmd_0x00000x0017
0004d1b8 R __host_cmd_0x00000x0087
0004d1c4 R __host_cmd_0x00000x008c
0004d1d0 R __host_cmd_0x00000x008f
0004d1dc R __host_cmd_0x00000x0092
0004d1e8 R __host_cmd_0x00000x0093
0004d1f4 R __host_cmd_0x00000x0097
0004d200 R __host_cmd_0x00000x0098
0004d20c R __host_cmd_0x00000x00b6
0004d218 R __host_cmd_0x00000x00d2
0004d224 R __host_cmd_0x00000x00d3
0004d230 R __host_cmd_0x3E000x0000
0004d23c R __host_cmd_0x3E000x0002
0004d248 R __evt_src_EC_MKBP_EVENT_HOST_EVENT
0004d248 R __hcmds_end
BOARD with host commands only
100bc888 R __hcmds
100bc888 R __host_cmd_0x00000x0000
100bc894 R __host_cmd_0x00000x0001
100bc8a0 R __host_cmd_0x00000x0002
100bc8ac R __host_cmd_0x00000x0003
100bc8b8 R __host_cmd_0x00000x0004
100bc8c4 R __host_cmd_0x00000x0005
100bc8d0 R __host_cmd_0x00000x0006
100bc8dc R __host_cmd_0x00000x0007
100bc8e8 R __host_cmd_0x00000x0008
100bc8f4 R __host_cmd_0x00000x0009
100bc900 R __host_cmd_0x00000x000a
100bc90c R __host_cmd_0x00000x000b
100bc918 R __host_cmd_0x00000x000d
100bc924 R __host_cmd_0x00000x0010
100bc930 R __host_cmd_0x00000x0011
100bc93c R __host_cmd_0x00000x0012
100bc948 R __host_cmd_0x00000x0013
100bc954 R __host_cmd_0x00000x0015
100bc960 R __host_cmd_0x00000x0016
100bc96c R __host_cmd_0x00000x0017
100bc978 R __host_cmd_0x00000x0025
100bc984 R __host_cmd_0x00000x0026
100bc990 R __host_cmd_0x00000x0029
100bc99c R __host_cmd_0x00000x002a
100bc9a8 R __host_cmd_0x00000x002b
100bc9b4 R __host_cmd_0x00000x002c
100bc9c0 R __host_cmd_0x00000x0044
100bc9cc R __host_cmd_0x00000x0045
100bc9d8 R __host_cmd_0x00000x0046
100bc9e4 R __host_cmd_0x00000x0047
100bc9f0 R __host_cmd_0x00000x0061
100bc9fc R __host_cmd_0x00000x0062
100bca08 R __host_cmd_0x00000x0064
100bca14 R __host_cmd_0x00000x0065
100bca20 R __host_cmd_0x00000x0067
100bca2c R __host_cmd_0x00000x0087
100bca38 R __host_cmd_0x00000x008c
100bca44 R __host_cmd_0x00000x008d
100bca50 R __host_cmd_0x00000x008f
100bca5c R __host_cmd_0x00000x0092
100bca68 R __host_cmd_0x00000x0093
100bca74 R __host_cmd_0x00000x0096
100bca80 R __host_cmd_0x00000x0097
100bca8c R __host_cmd_0x00000x0098
100bca98 R __host_cmd_0x00000x0099
100bcaa4 R __host_cmd_0x00000x009e
100bcab0 R __host_cmd_0x00000x00a0
100bcabc R __host_cmd_0x00000x00a1
100bcac8 R __host_cmd_0x00000x00a8
100bcad4 R __host_cmd_0x00000x00a9
100bcae0 R __host_cmd_0x00000x00b6
100bcaec R __host_cmd_0x00000x00b7
100bcaf8 R __host_cmd_0x00000x00d2
100bcb04 R __host_cmd_0x00000x00d3
100bcb10 R __host_cmd_0x00000x00db
100bcb1c R __host_cmd_0x00000x0101
100bcb28 R __host_cmd_0x00000x0102
100bcb34 R __host_cmd_0x00000x0103
100bcb40 R __host_cmd_0x00000x0104
100bcb4c R __host_cmd_0x00000x0110
100bcb58 R __host_cmd_0x00000x0111
100bcb64 R __host_cmd_0x00000x0112
100bcb70 R __host_cmd_0x00000x0113
100bcb7c R __host_cmd_0x00000x0114
100bcb88 R __host_cmd_0x00000x0115
100bcb94 R __host_cmd_0x00000x0116
100bcba0 R __host_cmd_0x00000x0117
100bcbac R __host_cmd_0x00000x0118
100bcbb8 R __host_cmd_0x00000x011a
100bcbc4 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX
100bcbc4 R __hcmds_end
BRANCH=none
Change-Id: I5d13d2a7fe7fa9a0fbeed43177cc612f572a58bb
Reviewed-on: https://chromium-review.googlesource.com/419702
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
- Before the change was made, the "__ro_end" was at 00013520h.
We change to 00012760h.
- Rename "CONFIG_IT83XX_ILM_BLOCK_SIZE" to "IT83XX_ILM_BLOCK_SIZE"
this is because we don't support reconfiguration at board-level.
- Put some task functions into "__ram_code" section to
fill the gap and improving performance of code-fetch.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: flasherase, flashwrite, and flashread.
Change-Id: I2f2906a2a0b6971aadd00120c282801161447808
Reviewed-on: https://chromium-review.googlesource.com/424248
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add HOST_LDFLAGS to cmd_c_to_host to allow for cross-compilation of
utils such as 'ectool'.
BRANCH=master
BUG=none
TEST=Cross compile using arm-oe-linux-gnueabi with corresponding
linkerflags and run resulting binary on armv7 device
Change-Id: Iebdfa92239eb5f245d4ad3623cbdceafd82d1675
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/424855
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
TPM NVMEM commits are reenabled as soon as the system boots into
Chrome OS. However, sometimes the device does not boot into Chrome OS,
in which case it is necessary to be able to reinstate NVMEM commits
explicitly.
The new vendor command will provide this functionality.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=added code to depthcharge to issue the new vendor command if the
system falls into recovery mode, verify that commits are
re-instated once the command is issued.
Change-Id: I3c06b27175751dc2c095911441935eee62ed9c50
Reviewed-on: https://chromium-review.googlesource.com/424064
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch eliminates NVMEM commits at system startup, namely between
the moment the TPM is reset and the moment the AP is trying to read a
PCR (which is an indication of the AP having booted into OS).
To avoid losing NVMEM changes in case TPM is reset before PCR Read
command is issued, pending changes (if any) are saved before TPM reset
is processed.
For the same reason TPM reset invocation is being added to the hard
reboot path; this will kick in when there is a restart after cr50
firmware update.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=with instrumented coreboot/depthcharge observed the following
execution times for various TPM command issued at startup
command 0x144, 15203 us
command 0x14e, 11814 us
command 0x182, 12461 us
command 0x182, 12456 us
command 0x138, 11503 us
command 0x138, 11512 us
command 0x14e, 14648 us
command 0x14e, 12597 us
command 0x121, 11353 us
which totals 113 ms and shaves more than 200 ms off the boot time.
Change-Id: Ic52309291fdb9c3ede96e0ad015ad9fc076bddc5
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424063
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
In preparation to adding new features, switch cr50 to using shared
memory allocator allowing concurrently allocated buffers.
BRANCH=none
BUG=chrome-os-partner:59873
TEST=verified that cr50 works fine and could be updated on a reef.
Change-Id: I87656cbd1f6d4928f25396dbcc59cc3f43984d85
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424850
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new code allows to replace the existing one buffer at a time
shared memory facility with a malloc/free implementation. A new
configuration option is being provided (CONFIG_MALLOC).
The names of functions allocating and freeing memory are not being
changed to allow to switch between the two implementations seamlessly.
A double linked list of buffers is used to keep track of free and
allocated memory. During initialization the entire free memory block
is considered a single free buffer. No allocations/frees are allowed
from within interrupts. The control structures are protected by a
semaphore, so allocate and free invocation could be blocking.
A test is added which randomly allocates and frees memory, continuing
until all branches in the allocate and free functions are taken.
BUG=chrome-os-partner:
TEST=make buildall -j succeeds, which includes testing the new
malloc/free implementation.
Change-Id: I5e71c0190c6c247ec73bb459f66a6d7a06e3d248
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/420466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to reduce build times during development, this change allows an
engineer to build a subset of all boards, writing the results for each
board into the ".failedboards" directory.
The expectation is that, while working on code that affects multiple
boards, the engineer will invoke "make build_boards BOARDS=<board-list>"
periodically to confirm that all affected boards still build.
Before pushing any code for review, however, the engineer is still expected
to run "make buildall" to ensure all boards still build and tests pass.
* Define a new make variable, BOARDS, whose default value is $(boards).
This variable can be overridden on the make command line or via the
environment. Its value must be non-empty.
* Use the BOARDS make variable to control which boards will be built by the
new "build_boards" and "try_build_boards" targets.
* Refactor the "buildall" target so that it depends on "build_boards". This
indirectly allows the boards built to be controlled via the BOARDS make
variable.
* Here are some make command lines that were used to test the behavior of
the change:
make -j buildall # Builds all boards, runs tests.
make -j build_boards # Builds all boards, doesn't run tests.
make -j build_boards BOARDS="cr50 reef" # Builds cr50 and reef boards
make -j build_boards BOARDS= # Fails due to empty BOARDS.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I833277842e5e20d86eaa90df6457264a2f86a3fa
Reviewed-on: https://chromium-review.googlesource.com/420110
Commit-Ready: Carl Hamilton <carlh@chromium.org>
Tested-by: Carl Hamilton <carlh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
ISL9237 and ISL9238 are almost identical, with few register changes,
let's make the driver generic, to support both chargers.
BRANCH=none
BUG=chrome-os-partner:61166
TEST=make buildall -j
Change-Id: I029894dd62ab7e45897d877289707ee8c1ff1d09
Reviewed-on: https://chromium-review.googlesource.com/422197
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This error code is used to indicates the data has not changed.
Motion sense task will therefore not add any entry in the sensor FIFO.
BUG=chrome-os-partner:59423
TEST=make -j buildall
BRANCH=reef
Change-Id: I58b9be5675d8949bd682d8c89dadea1dfff9bf2e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424856
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If there's a task switching occurred between loading waiter and
unlocking the lock, the task with higher priority won't wake up since
the local variable, waiter, doesn't contain its ID bit before task
switching. In this situation, the higher priority task only can be
awakened when the other tasks execute mutex_unlock() again.
But consider the following conditions: (For example, the driver of
charger bd9995x.)
1. There are more than one mutex for the usage path of i2c port.
2. There are more than one task access this usage path of i2c port and
one of these tasks, task A, met the situation above.
3. The other tasks have no chance to execute mutex_unlock() of i2c since
the task A still occupied the mutex of charger.
All the tasks used the same i2c port or the other hardware will sleep
forever. This CL makes loading waiter and unlocking the lock as atomic
to solve this issue.
BRANCH=none
BUG=chrome-os-partner:60617
TEST=make BOARD=snappy; make BOARD=oak; Executed charger factory test on
4 units of snappy for 3 days and no symptom occurred.
Change-Id: Id976fc47955b33ca83bb2182b197d9f2781c341b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/423285
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We need 2 accelerometer for tablet mode. If one of them is not working,
disable tablet mode. We will stay in clamshell mode, lid angle will be
always unreliable.
BUG=chrome-os-partner:61141
TEST=On kevin with a single sensor. Check we are in clamshell mode
when rebooting the EC.
BRANCH=kevin
Change-Id: I7bf6cdc9d85370fce20e5183622b4bc18f4f5f99
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424184
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix issue where the block is calculated wrong since the offset that gets
added is wrongly EEPROM_BLOCK_COUNT_PSTORE which is the number of
total blocks rather than the starting block given by
EEPROM_BLOCK_START_PSTORE.
TEST=Build test, ran on board with stubbed out functions.
BUG=none
BRANCH=none
Change-Id: Ide4839845353c2b9f95a37eb689c8d800169bb22
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/424182
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Setting HICTRL.FW_OBF clears the HIKMST.OBF and STATUS.OBF flags but it
does not deassert IRQ1 when already asserted. To make sure IRQ1 will
also be deasserted need to emulate a host read.
Modified drivers:
1. lpc.c: emulate a host read to clear OBF and deasserted IRQ1.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall; Run FAFT items related to Power on/off, reboot,
and keyboard on Wheatley.
Change-Id: Ibf0ff3b8a4eeece853916e4e19d67fcc7ae2e989
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/419909
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Follow reef setting.
discharges on AC till the charger is detected and settled but
when booting from the cut-off mode this will kill the power hence
do not discharge on AC when battery is still waking up and settled.
BUG=none
BRANCH=reef
TEST=make buildall
Change-Id: I09d8f5a363d20bb3d0df80694de52ae3a37a0ed9
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/422621
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added common code for charger profile override for fast charging.
Fast charging configs can be defined in the respective board battery
file and use the common code for imposing the custom data.
BUG=chrome-os-partner:59393
BRANCH=none
TEST=Enabled the config on Reef. Manually overrode the temperature
and voltage. Observed correct charge profile config is selected
for each tests.
Change-Id: I075d271258470b98d38e4d5395d749469d3fd469
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/407928
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code that referenced these structure definitions was removed
months ago. GCC 6.2 warns about the structures being definte but
not used.
BRANCH=none
BUG=none
TEST=Build tested only
Change-Id: I68de7cc351667b3fb51aa9004dfc86d936f4a9cc
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424432
Reviewed-by: Shawn N <shawnn@chromium.org>
- Enable keyboard backlight configuration option so the keyboard backlight
interface is present.
- Enable interrupt on both directions for volume buttons, otherwise we
see the press but not the release.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=manual testing on P1 board
Change-Id: If0b6a913bb63f31051ab5a30ffe9f0682550e058
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/424493
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add support for the Texas Instruments TMP112 I2C temperature
sensor. The sensor provides a single temperature value.
BUG=none
BRANCH=none
TEST=Ran 'temp' console command over and over. Verified values with
digital thermometer.
Change-Id: Ida4c082309d245c3f7c6282ecea74ce5af746e43
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/418488
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The EC attempts to limit USB ports to 1.5A if a device is plugged
into both ports, but this ends up with no power to the ports instead.
Until this can be debugged with the right equipment just pretend we
can do 3A to both ports so factory tests can pass.
BUG=chrome-os-partner:61431
BRANCH=none
TEST=plug device into both ports on P1 board and see that they work
Change-Id: Icd4430d0026dc323e56b7ce88b9d8e79e6e825c5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/424453
