Board-specific features like lightbar should be config'd at the board
level, not at the chip level.
BUG=none
TEST=build link, bds, daisy
Change-Id: If1df2ca0422f7b8bdc172d0df7bd9f6a1af6a9d2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Allow to build without the power button task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make qemu-tests
Change-Id: Ibc757a6641f195f0d10e6a673792b996694f8cec
This works similar to SCI/SMI events, but triggers a separate
level-sensitive signal to the PCH instead.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8514
TEST=manual
From EC console:
gpioget PCH_WAKEn --> should be 1
hostevent wake 0x1
close lid switch (with magnet)
hostevent -> should show wake mask 0x1, raw events 0x1
gpioget PCH_WAKEn --> should be 0
hostevent clear 0x1
hostevent -> should show raw events 0
gpioget PCH_WAKEn --> should be 1
Change-Id: I29832c1dc30239a98987578f07dfeb25791dde11
Remove dummy boot-time output to UART1; no longer needed now that
there's a debug command to do the same thing.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual
comxtest - prints default message to x86 UART
comxtext ccc123 - prints 'ccc123' to x86 UART
Change-Id: I37d37aeca06bf71b106f5ad3473a79780fd089a9
Not compiled into any target; new version of temp_sensor.c is in common/
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=build link and bds
Change-Id: I00232a7cd8a8a9ee6353c5f04c86fcacc83cbd3e
For debugging PCH reset.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8397
TEST=power system on, then use x86reset to reset it. Should see line state changes printed.
Change-Id: Ief2f09bd0986339812183d0b32dc0208437d1103
Note that this moves the charger to a different I2C port. If you're
working on battery charging, you'll need to hack board.h in your local
repo to move it back.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8458
TEST=manual
Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
And faninfo now checks if the fan is powered.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=manual
1) faninfo --> fan is initially disabled and powered off
3) gpioset enable_vs 1 --> fan is now powered on, but still disabled
2) fanset 8000 --> fan is now enabled, and you should hear it
Change-Id: I97f35a20022cabd4520522f2d18ecb7603faabd1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8325
TEST=manual
Boot system with lid open. 'ectool switches' should show lid open.
Use 'dut-control goog_rec_mode:on'. 'ectool switches should show
dedicated recovery signal on.'
Use 'dut-control goog_rec_mode:off'. 'ectool switches should show
dedicated recovery signal off.'
Disable write protect via screw. 'ectool switches' should show WP
signal disabled.
Boot system in recovery mode (power+esc+reload). Should show 0x09.
Change-Id: I0434427c4b5f8c07c02a8714618f7eb101b86fed
Also prints the current timer value when inits are done, and when the
watchdog task first gets to run (after all higher priority tasks sleep
at least once).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST=none
Change-Id: I342f86ad087fd18ab064a10a5bcdd0b69ee373d0
Implement a generalized I2C transmit-receive function that
write-then-read blocks of raw data. Original 8-bit and 16-bit
read/write functions are refactored.
SMBus read-block protocol for ASCII string is also implemented
based on this API.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8026,8316
TEST=manual:
Type 'lightsaber' to check 8-bit read/write.
Type 'charger' to check 16-bit read.
Type 'charger input 4032' to check 16-bit write.
Change-Id: I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
Note that this only handles lid and power button; see
crosbug.com/p/8325 for write protect.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8185
TEST=manual
1. Check state with lid open
localhost ~ # ectool switches
Current switches: 0x01
Lid switch: OPEN
Power button: UP
Write protect: ENABLED
2. Press power button
localhost ~ # ectool switches
Current switches: 0x03
Lid switch: OPEN
Power button: DOWN
Write protect: ENABLED
3. Release power button and close lid
localhost ~ # ectool switches
Current switches: 0x00
Lid switch: CLOSED
Power button: UP
Write protect: ENABLED
Change-Id: I25f2fa3dfeac004dde9b10a4243ee235875f1b6e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8324
TEST=manual
1. When system is off, open lid. Debug console should show PB PCH pwrbtn activity.
2. Wait for system to boot.
3. Quickly close and open lid. Debug console should not show pwrbtn activity.
Change-Id: Ia018ff06a31ac2a68f20021d17e47ddb06096eb8
(Also define other host events)
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8308
TEST=manual:
Use magnet to trigger lid-closed and lid-open.
'hostevent' should show raw events = 0x3.
Press power button.
'hostevent' should now show raw events = 0x7.
Change-Id: I9c8367d5152d526299a7a3149250de84cc2e0557
implement actual_key_masks[]. A ghost key exists if two columns share
more than one row (after ANDed actual_key_masks[]).
BUG=chrome-os-partner:7485
TEST=on bds. test cases:
single press of all keys.
~ 1 4 5: later 2 keys should be ignored (ghost).
h j k: all keys should work.
u R-shift 0 P: p should be ignored (ghost).
i R-shift ' p: P should show up.
Change-Id: I1ac105874a5327e839a5240ccbdd6304637ad404
We used to have flaky PECI temperature read so we ignored failure. Now
the PECI temperature read seems to work fine so we should have it report
error on failure.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7493
TEST=When powered off, 'temps' shows error on PECI temperature reading.
Change-Id: I161a8f84f66ba06959c21838ee364b2f8d8b4945
This is necessary to support SCI/SMI events.
Note that this breaks compatibility with previous ectool builds - and
probably also breaks flashrom support.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8253
TEST='ectool hello' and 'ectool flashinfo' still work
and 'ectool usbchargemode 3 1' fails with error 2
Change-Id: If39e5b6e7cdcec1b5ec765594e8492925b430b10
Add console command 'autofan' to turn on automatic fan speed control.
Also modify 'fanset' to disable automatic control before setting fan
speed.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8250
TEST=Manual test
Change-Id: I2db85ce2e754bba21567b2c92e4476049d517627
On the STM32L UART without a FIFO, the Transmit Register might need
some time before pushing its content to the shift register.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on ADV board, verify we are no longer missing most of the carriage
return on console.
Change-Id: Ic638dc452d6e30a5f127710fc964143d477fa1d6
Actual RPM is now read from LPC mapped space. Modify this command to
return target RPM so we can verify EC receives target RPM.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8238
TEST=Get the same value after setting target RPM.
Change-Id: I9bcc9edd327cec1311b51fd0fcbc4a43b353daff
Add a task to update fan speed in LPC mapped memory once per second.
Also added read_mapped_mem16 and read_mapped_mem32.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8183
TEST="ectool pwmgetfanrpm" shows same result as "faninfo" from ec
console.
Change-Id: Ibc536acd39f836ffcad0bfa7c9c14e730220bd49
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8097
TEST=manual
faninfo
should report fan is disabled
powerbtn
system turns on, fan turns on
faninfo
should report fan is enabled
powerbtn
system turns off, fan turns off
faninfo
should report fan is disabled again
Change-Id: I1be67004edb23ccd18ad434c9340bfbecc22e7c4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8097
TEST=manual
faninfo
should report fan is disabled
powerbtn
system turns on, fan turns on
faninfo
should report fan is enabled
powerbtn
system turns off, fan turns off
faninfo
should report fan is disabled again
Change-Id: I8e94c142bf18d07f83bac05287bcd503a098cee7
We now have a task contantly polling temperature sensors, so we need to
use mutex to arbitrate I2C buses.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7491
TEST=temps, i2cscan, and i2cread all work fine.
Change-Id: I1360afb22d98b47da3da0820c95df45c15056f82
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:8125
TEST='hibernate 1000' should hibernate and wake back up
Change-Id: I3bf36171ea86a90415593bdc884c004bfff62c4c
The FT4232 chip used on Servo v2 has adaptative clocking feature.
Let's try to use it to avoid signal integrity issue we observe on
Proto-0.5 JTAG.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=connect to Link proto-0 and read/write all the SRAM without errors.
Change-Id: Ic2b91acc29c6d510fb6f3364dd253d3deb650949
A temperature polling task is added to achieve temporal correction and
also reduce the latency of reading temperature.
Factor out sensor specific part to keep code clean.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7801
TEST=On link, 'temps' shows all temperature readings.
Cover each sensor with hand and see object temperature rise.
Compilation succeeded on bds/adv/daisy/discovery.
Change-Id: I3c44c8b2e3ab2aa9ce640d3fc25e7fba56534b86
This loosely ports the LM4 keyboard_scan code to STM32
Notable differences:
- Keyboard GPIO layout is spread across multiple ports and is not
contiguous in many places. Because of this, bitmasks are mostly
generated on-the-fly instead of hard coded (IO is kept to a minimum)
- Longer timeout when scanning columns (100us versus 20us)
Also, some functions are stubbed out currently since they rely on
other bits being implemented:
- keyboard_state_changed()
- keyboard_has_char()
- keyboard_put_char()
BUG=none
TEST=Tested on STM32L-Discovery (monitoring keystrokes via UART)
Change-Id: I84985879589e70688b2b29b288ab17037f7668b2
To accomodate our growing code, image RW.B is removed so that RO and
RW.A can both have 60K space. This is just a temporary solution. Add
RW.B back when we have enough space for all three images.
Also add license header to firmware_image.lds.S so that repo does not
complain about it.
BUG=chrome-os-partner:8079
TEST=build image and run on proto-0.
Change-Id: I85b723f3e645c12fd89b189263ca44d58c4621eb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Compared to Daisy, it has the EC console on USART2 (pins PA2 and PA3)
and regulator enable GPIOS EN_PP1350 and EN_PP5000 are on PA9/PA10.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv && make BOARD=daisy && make BOARD=discovery
Change-Id: I545f7c9b05480e58db913ea562c77a1a1cd2b11c
Avoid duplicating in each board file, the stub functions replacing not
implemented drivers on the STM32L platform.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=discovery
Change-Id: I25cd949c31e53a90c39f623617c7d52517a3d205
Allow to set easily the SoC pins to one of their native functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, check the muxing of the USART pins is still
working and we get traces.
Change-Id: I6e83d2eea8986d814720ad4b2fef588908b99079
This CL attempts to abstract underlying bus from i8042 code. Nearly
all i8042 logic is isolated already. This patch is intended to allow
us to use i8042 logic for processing keys and commands on boards which
do not necessarily use LPC as the host <--> KBC bus interface.
This CL does the following:
- Define KBC bus <--> host (kbc_host_bus) on a per-board basis in
board.c.
- Add generic wrappers in place of lpc_keyboard_* in i8042 code.
- Define the behavior of generic wrappers in EC-specific keyboard
sources. If board.c specifies LPC, then send via LPC.
TODO: This needs to be tested on real hardware...
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=Locally compiled for Link, BDS and Discovery.
Change-Id: I9cabd514bd44fd6b508c26994eccc3011eedbc0f
Allow to setup edge triggered interrupts on the GPIOs.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=add a adhoc handler for the USER button and check its trace.
Change-Id: I11a280c412c1d333bab4a74f869221edf59fcf8e
This will allow more efficient access to EC-provided data (temperature,
fan, battery) by the main processor.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7857
TEST='ectool hello' from link main processor should still work
Change-Id: I2dc683f3441b34de9fb4debf772e386b9fdcfa82
Implement enable_fpu() and disable_fpu().
enable_fpu() disables interrupt and then enables FPU.
disable_fpu() disables FPU and enables interrupt.
Also added a CONFIG_FPU flag.
BUG=chrome-os-partner:7920
TEST=none
Change-Id: I2d71f396d9c7d7ac4a6a2d525f3d86f8aae87521
Signed-off-by: Vic Yang <victoryang@chromium.org>
