Mapped reads are relative to CONFIG_EC_*_STORAGE_OFF, not
CONFIG_R*_MEM_OFF. The previous implementation happened to work for
internal mapped storage (eg. stm32) but failed for external mapped
storage which is copied to SRAM before execution (eg. npcx).
BUG=b:62841029
TEST=Verify sysjump works again on eve/poppy/soraka. Verify sysjump
and sig verification continues to work on fizz and stm32.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id51ce5697555eea38b246b58dbf47f22d4befaa7
Reviewed-on: https://chromium-review.googlesource.com/541861
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This CL includes:
1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish
which npcx's ec is used on the board.
2. Add config_chip-npcx5/7.h files and move features depend on chip
family into them.
3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and
NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on
npcx7 ec. We'll use them later in gpio/system/flash drivers.
4. Add ram size checking for all npcx ec series.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481560
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Kevin is code space constrained, so use RAM normally used for data
instead for code.
BUG=chrome-os-partner:52876
BRANCH=None
TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data
RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes
to add sensor task). Also, verify kevin continues to boot + power sequence.
Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343191
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Since npcx5m6g has larger than 128 KB code ram for FW, the original
alignment between RO & RW regions isn't suitable for new chip.
Therefore, we add 256KB alignment of them for npcx5m6g.
In order to program the flash used by npcx5m6g, we add new board array,
BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout
ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g
and flash_npcx5m6g to program flash with different layout.
Modified sources:
1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for
npcx5m6g.
2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to
distinguish which flash layout ec used.
3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with
different layout.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/331903
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT
variant to distinguish which verson ec is.
In config_chip.h, we use CHIP_VARIANT to specify the size and start address
of program memory. Ecst tool also needs a chip parameter to make sure
the address range checking of entry pointer won't fail.
Modified sources:
1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec
of npcx ec.
2. config_flash_layout.h: Replace constant value with
CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE.
3. build.mk: Add -chip parameter for ecst tool to check entry address.
4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g).
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/330072
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
SERIRQ bug:
PMC1/2 share the same IRQ number 1 with default setting. Enable it will
influence 8042 protocols since KBC has no data but IRQ 1 is issued by
PMC.
AC detection bug:
GPIO definitions between AC_PRESENT and ACOK mismatched. AC_PRESENT will
always
be high even we don't plug the adaptor.
Modified drivers:
1. lpc.c: Remove enabling SERIRQ for PMC1/2 and disable IRQ12 for Mouse.
2. config_flash_layout.h: Modified for adjusting RAM size.
3. gpio.inc: Modified GPIO definitions for AC issue
4. board.h: Modified for adjusting RAM size and add support for ACC
5. board.c: Add support for ACC and adjust ADC max value
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ib330ef4078e4b06f1c01a2a6316e468b43d7a8d9
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/311933
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Remove NPCX_EC_FLASH_SIZE definition and replace it with CONFIG_FLASH_SIZE.
Due to inconsistence between NPCX_EC_FLASH_SIZE and CONFIG_FLASH_SIZE,
some flash commands such as flasherase will cause unexpected results.
Modified drivers:
1. config_flash_layout.h: Remove NPCX_EC_FLASH_SIZE definition.
2. flash.c: Replace NPCX_EC_FLASH_SIZE with CONFIG_FLASH_SIZE.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Idca286eef5bb014d5c4cd689c39635e09f40ee03
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/307004
Reviewed-by: Shawn N <shawnn@chromium.org>
Since CONFIG_RO_SIZE and CONFIG_RW_SIZE now exist (which may
theoretically be different sizes), it is no longer useful to globally
define the size of an image.
BUG=chromium:535027
BRANCH=None
TEST=`make buildall -j`. Also, verify glados / glados_pd continue to
function as expected.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie29959923bc5d02b4d7d6d507ff2191bcb7d24c8
Reviewed-on: https://chromium-review.googlesource.com/301743
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Since there is no more concept of a flash region belonging only to the
EC, we only need one FLASH_SIZE config, which represents the actual
physical size of flash.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6
Reviewed-on: https://chromium-review.googlesource.com/297824
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to support architectures with non-contiguous writable and
protected regions, change storage offsets to be relative to writable and
protected regions, rather than relative to "the start of the region of
storage belonging to the EC".
Spec doc available at https://goo.gl/fnzTvr.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4
Reviewed-on: https://chromium-review.googlesource.com/297823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
CDRAM / CODERAM configs were previously used for chips which copied code
from external SPI to program memory prior to execution, and were used
inconsistently between npcx and mec1322.
These CONFIGs are now completely redundant given new configs like
CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4
Reviewed-on: https://chromium-review.googlesource.com/297804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Based on feedback from programmers, it's not clear when
config_std_internal_flash should be used, and when non-standard
chip-specific layouts need to be defined. Add clarity here with the
following changes:
- Explain in-depth the one config that config_std_internal_flash should
be used for.
- Move non-standard chip-level flash layout CONFIGs to their own new
chip-level file, config_flash_layout. All chips should either include
config_std_internal_flash.h OR define their own layout in their own
config_flash_layout.
Functionally, this change is a NOP.
BUG=chrome-os-partner:23796
TEST=`make buildall -j`
BRANCH=None
Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/296527
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
