Add this to the GPIO API. It seems that the implementation is copied
in LM4 and STM32 so I have reluctantly done the same with this new
function.
BUG=chrome-os-partner:9424
TEST=build and boot on Daisy
Change-Id: Ifddc52e69b2b33af2645384c0171dd264e588fcd
Signed-off-by: Simon Glass <sjg@chromium.org>
The changes in the message protocol break SPI support, so re-introduce
these, this time in the driver itself.
We add the concept of an option preamble in the message, a length and a
trailing byte.
BUG=chrome-os-partner:9426
TEST=run U-Boot, see that keyboard works correctly now.
Change-Id: I83b4af7e3745b935ffafcd9e2f521fce77e3bc6e
Signed-off-by: Simon Glass <sjg@chromium.org>
The position of jump_tags was shifted every time a new field was added
to struct jump_data. This broke the sysjump hook badly.
To make this more scalable, add a header_size field in struct jump_data.
Then the new code can always prepend (or reduce if jump_data becomes smaller)
some spaces between jump_data and jump_tags.
BUG=chrome-os-partner:9447
TEST=EC upgrade from EC 517 (2231) to this version, and keyboard keeps working.
Note that EC 526 (2235) to this version is not working because we have no way
to identify that header version change.
Change-Id: If1b506c6f7d22e5affaaf8ada15990f60d2f957a
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8982
TEST=manual
run console command 'charger'
charger option will be displayed in bin and hex output
Change-Id: I461bce347f13eeb4f2c8595b83a7ba4c7d40ea58
The address of charger temperature sensor and memory temperature sensor
are interchanged. Fix this in this CL.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:9450
TEST=Manual
Change-Id: I20ae4d39ef13992ca7cac32bb2e6be12e195731e
Rather than open code this each time, create a function for this. The
wrap-around condition may not be needed, if the timer starts at zero,
since we have 64 bits to play with.
BUG=chrome-os-partner:9424
TEST=build and boot on daisy
Change-Id: I84ae651212769b5927c452bc03f31f60a25a829e
Signed-off-by: Simon Glass <sjg@chromium.org>
We no longer support ADV EVT0 board and Discovery reference design.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=link
Change-Id: I7eb81e5271c070b17f018ac9c14491f1804c0e08
This modifies the existing daisy's board.c to use the new pin mapping.
BUG=None
TEST=Tested on Daisy-EVT1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I717ce78df1ed29843d1498e979956c6ffdb05e80
this fixes the build breakage on stm32-based platforms.
In the linker script, remove the ASSERT since this macro is not designed
to work in that context and this size condition is already verified by
the linker by setting the "length" of the "FLASH" memory region.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=daisy
boot on Link and Daisy
Change-Id: I08964749d44f47caa0a359bc93c303a9611e5d73
Add STM32F support.
Based on David's changelist.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9057
TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery
Change-Id: Ide817d11480f0b56f67deaae3c08bc631f605075
Add a parameter to define the chip variant and pass it to build/make
processes.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9057
TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery
Change-Id: I87b65b582ed5fc2cf5966446e15224ac15e328e9
just rename STM32L to STM32.
Most of the STM32L15x code is common with STM32F1xx.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9057
TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery
Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
power related GPIO has been renamed, update the board definitions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv
Change-Id: I2f0e1e9e93af22c1a6f64f354336bf0c30e9c5cd
This is very basic, so you can only rely on RO_SECTION, RW_SECTION_A, and
RW_SECTION_B for now. We'll fill in more regions as we add vboot stuff.
Still, you should be able to do things like this:
flashrom -p internal:bus=lpc -r ec.bin
flashrom -p internal:bus=lpc -w ec.bin -i RW_SECTION:ec.B.flat
BUG=chrome-os-partner:8198
TEST=manual
Build the image, look for the FMAP in it.
cd src/platform/ec
make BOARD=link
dump_fmap ./build/link/ec.bin
Change-Id: I0adbbfb8e975faae805bda271873fcef46590cf4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
When the host reboots the EC it should be able to request the EC to
force recovery mode after reset. This is achieved by extending the
REBOOT EC command with a bitmask byte, with bit 0 dedicated to
recovery request.
So, when BIOS on the way up determines that recovery is requested, but
the EC is not running from the RO space, the BIOS would reset the EC
forcing it to run from RO and to request recovery mode through the LPC
bitmask. Then BIOS will restart itself ensuring that the system comes
up in consistent state.
Some refactoring was also done to make the code a bit more compact.
BUG=chrome-os-partner:9040
TEST=manual
. tested along with coreboot changes (test described in the coerboot CL).
Change-Id: I29801b6aec80da0901ba0e8db8e92e615cc778bd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
LM4 reports fan stalled when fan speed is set to 0. Need to check this
before issuing warning.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7497
TEST=Did not see fan stall warning when fan speed is 0.
Change-Id: I8eecca8516b5442d4943d9195d04acc5b4041085
Note: This will not work on older (0.94 boards).
- Use power button (KB_PWR_ON) to drive power sequencing events and
disable EC_PWRON. This is because EC_PWRON and KB_PWR_ON shared an
external interrupt line. Daisy v2.x will fix this so that both can
be enabled. Note: KB_PWR_ON is active low, wihle EC_PWRON is active
high.
- Relay power button state to PMIC. Also, since we are driving
PMIC_PWRON instead of PMIC_ACOK now, so updated the naming.
- Add a keyboard power button debounce period to avoid accidentally powering
the system back on after keyboard power-off.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=tested on daisy (frh@ verified behavior using a scope)
Change-Id: I5338eebe42c9b43a07af371a450db23276b2a574
This is a hack to avoid issues caused by incompatible
messaging protocol updates.
During protocol development, the length of a packet changed which
could cause the system to hang (or other issues) if the host
requested the wrong number of bytes from the EC. This avoids the
issue with development versions of the protocol, by simply making
the EC unresponsive on the old port.
BUG=none
TEST=Tested on Daisy 1.02 and EVT1
Change-Id: I96495d4c2bd14b377bef862801934d5168cb6cc7
Signed-off-by: David Hendricks <dhendrix@chromium.org>
ensure we cannot miss any timer, no matter how slow is the CPU and how
many simultaneous timer we set.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9319
TEST=boot Link EC and do long key press, see the EC watchdog panic no
longer happening.
Change-Id: I1ecc88fc06698175444fd86cce4c0abb5e846996
The EVT boards will have an enable signal for the +5V always-on rail
connected to GPIO PK4.
Just turn it on at startup to ensure that EVT boards will run out of the
box with the current EC firmware.
(PK4 is a test point on proto-1 board, this should be harmless).
We can later implement fancier power saving scheme by enabling it only
when we enter S3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9284
TEST=boot Linux kernel on Link proto-1 and Link-1 proto-1 reworked with
+5V Always-on enable on PK4.
Change-Id: I26527480c7cd364f3fabcaabaadd079a332f9c1c
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:9152
TEST=manual
run latest ectool with old EC image
Change-Id: I09d4f6e8fcc131da227fc5a9c48291b08dfb6d19
BUG=chrome-os-partner:7839
TEST=manual
cd src/platform/ec
make BOARD=link
copy ./build/link/util/lbplay to the host and run it as root.
Change-Id: I6a4a842b7500751185c8f4c2744f4389226bae9b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Adjust fan step thresholds:
T=55C Fan=20%/2200RPM
T=65C Fan=40%/4400RPM
T=75C Fan=60%/6600RPM
T=85C Fan=80%/8800RPM
T=95C Fan=100%/11000RPM
Also set minimum fan speed to 0 rpm.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8466
TEST=Manual test
Change-Id: I609853f2eceb9a6a43fbeb500084e82b1461f092
When PWM module detects fan stall, issue SMI warning and print warning
message to console.
Signed-off-by: Vic Yang <victoryang@google.com>
BUG=chrome-os-partner:7497
TEST=Disconnect fan and power up. See warning message.
Change-Id: I4d96595f7f3cdfab5df333afc35206304bacab9d
BUG=chrome-os-partner:7839
TEST=manual
Try "lightbar help" on the EC console and "ectool lightbar help" on the
host. You should see the same commands and behavior.
Change-Id: I6e879e8bb892ef5ada7ef85a97fdf243149f4cb6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
fix small modularity issues to ensure we are able to compile all boards
in "tests" configuration.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:8546
TEST=make BOARD=link tests && make BOARD=bds tests
make BOARD=daisy tests && make BOARD=adv tests && make BOARD=discovery tests
Change-Id: I9eed0195af6bfd3b47ef74e3cb27966c4365c345
This sets the SYSCFGEN bit. Writes to external interrupt config
registers (SYSCFG_EXTICRn) will not stick unless this is set.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=tested on daisy
Change-Id: I9a92b424e9ac1f909206f89ed773248807619ab2
