In order to prevent keeping the CSAE bit at 1 forever impacts the eSPI
performance, the npcx driver enables host access wakeup functionality
before ec enters deep sleep or wfi. But this bypass also should be added
in __idle() of core/cortex-m/task.c if CONFIG_LOW_POWER_IDLE is
disabled.
This CL also narrows the bypass only when host interface is eSPI.
BRANCH=eve
BUG=b:64730183
TEST=No build errors for make buildall. Disable CONFIG_LOW_POWER_IDLE
functionality on poppy and use following script "count=0; while :;
do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep
1; count=$((${count}+1)); done" to test eSPI performances over 300
times. No errors occur and all tests' efficiency are the same as
removing CSAE bypass.
Change-Id: I8b6b69e37318208c185747151c06b3e6bdfd2f4e
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/644967
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
The state machine in common/case_closed_debug.c only handles a subset
of what we need to do for Cr50 external case closed debugging, and
also supports a 'partial' CCD state that doesn't exist for Cr50. Move
the few lines of code from that we actually need into our file.
BUG=none
BRANCH=cr50
TEST=manual
Assert CCD_MODE_L
See 'CCD EXT enable'
Confirm Cr50 console appears as a RW /dev/ttyUSBn endpoint
Confirm firmware update over USB works
Deassert CCD_MODE_L
See 'CCD EXT disable'
Confirm Cr50 console appears as a RW /dev/ttyUSBn endpoint
Confirm firmware update over USB does not work (can't find device)
Change-Id: Id96f2770632839a9690740ece54bc2eb71d39a38
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/647909
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, only usb_pd_protocol.c cares about the actual ccd mode
(disabled/partial/enabled). Everything else just cares whether it's
enabled or not. So promote the boolean ccd_is_connected() from
board/cr50 up to chip/g, and rename it to ccd_ext_is_enabled() to
match the new nomenclature (since 'CCD' itself is now too overloaded).
This will make it easier to handle CCD state directly in board/cr50
after we split it from common/case_closed_debug.c
BUG=none
BRANCH=cr50
TEST=make buildall; boot cr50; make sure USB endpoints still work
Change-Id: Ic3df7467bfe29f1c5d7060cac1309a1f0e090d9e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648212
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
CCD_CHANGE_HOOK should use CONFIG_CASE_CLOSED_DEBUG_V1.
All boards which use chip/g either use both CONFIG_USB_SERIALNO and
CONFIG_CASE_CLOSED_DEBUG or neither of them, so just depend on
CONFIG_USB_SERIALNO.
This is in preparation for making common/case_closed_debug refer only
to the usb_pd_protocol version (with mode=disabled/partial/enabled),
and cr50 will have its own version (with only enabled/disabled, and
tied more closely to CCD config).
No functionality changes.
BUG=none
BRANCH=cr50
TEST=make buildall -j; boot cr50 and see change hook called
Change-Id: I1985c8c48c1a85fed4549402a7b47b8a9cf135d7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/648067
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously, chip/g/rdd provided a method for an external console
command to override the Rdd cable detect state. But since we'll be
refactoring the 'ccd' command, it's tidier to move this to a console
command inside the rdd driver itself.
BUG=none
BRANCH=cr50
TEST=manual, with no debug cable present
rdd enable -> Rdd connect
rdd -> keepalive
rdd disable
rdd -> connected (hasn't had a chance to run state machine)
(wait <1 sec)
rdd -> debouncing
(wait 1 sec) -> Rdd disconnect
Change-Id: I141eedf8070b4ad2c96cc5a364f4e37dc29bed70
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/647991
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Currently, the console inhibited output when is_readonly=1, and only
inhibited input when is_enabled=0. That's harmless in the current
implementation, because common/case_closed_debug() only ever calls it
with enabled=0/readonly=1 or enabled=1/readonly=0. But if we ever do
decide to use enabled=1/readonly=1, that would have acted like
write-only, not read-only.
Fix that.
BUG=none
BRANCH=cr50
TEST=Attach to cr50 USB console, console is read/write.
Hack USB console to set is_readonly=1, console is read-only.
Change-Id: I04258fe2b040a00f98067d8be48a0632eb16e9c1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/647336
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This is the last state machine which used common/device_state.c. But
servo is more complex than that, because it needs to differentiate
state-isn't-known (debouncing) from state-isn't-knowable (Cr50 driving
EC TX), so it's cleaner to split it out the way we did AP and EC state
machines in previous CLs.
BUG=b:35587387
BRANCH=cr50
TEST=manual with CR50_DEV=1 build
// Test detect at boot, even with CCD connected
Pull CCD_MODE_L low
Pull DETECT_SERVO high
Pull DETECT_EC high
reboot -> 'Servo connect'
// CCD is not driving EC UART TX
ccd -> EC on, Servo connected, CCD enabled, EC UART RX
// When servo disconnects CCD can drive EC TX
Pull DETECT_SERVO low --> 'Servo disconnect'
ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX
// Can't detect servo reconnecting if we're driving EC TX
Pull DETECT_SERVO high --> (no change)
ccd -> EC on, Servo undetectable, CCD enabled, EC UART RX+TX
// When we stop driving EC TX, can redetect servo
Pull EC_DETECT low --> See 'EC off', 'Servo connected'
ccd -> EC off, Servo connected, CCD enabled, EC UART disabled
// Test debouncing at boot
Pull DETECT_EC high
Pull DETECT_SERVO low
Pull CCD_MODE_L high
reboot
Within 1 sec, pull DETECT_SERVO high --> 'Servo connected'
// Test debouncing after boot
Pull DETECT_SERVO low then high < 1 sec --> (no message)
Change-Id: I964bd36c35f52c8ef7b3ea3793b6e0764e93587c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/636047
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Implement keyboard backlight control through HID output report. One
could enable CONFIG_USB_HID_KEYBOARD_BACKLIGHT to enable keyboard
backlight support for a given board. Target board must implement the
`void board_set_backlight(int brightness)` function in order correctly
set backlight.
BRANCH=none
BUG=b:37971411,b:63364143
TEST=with follow up CLs
1. `make BOARD=hammer -j`
2. `echo 10 > /sys/class/leds/hammer\:\:kbd_backlight/brightness`
console shows 'Keyboard backlight set to 10%'
Change-Id: Ibeff510a0d996ddebf61b54ed6b500b02c35564a
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/586348
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Do not report click events when no finger is present on the touchpad.
BRANCH=none
BUG=b:65098167
TEST=Bend case, hear click, but no event reported in evtest.
Change-Id: I0385213102dab0775e1b6906cb3a45933deac757
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/637288
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Invalid paths (with arbitrary length) can be annotated and removed.
Report set of possible function cycles.
Sort the callsite outputs by filename and line number.
BUG=chromium:648840
BRANCH=none
TEST=extra/stack_analyzer/stack_analyzer_unittest.py
make BOARD=elm && extra/stack_analyzer/stack_analyzer.py \
--objdump=arm-none-eabi-objdump \
--addr2line=arm-none-eabi-addr2line \
--export_taskinfo=./build/elm/util/export_taskinfo.so \
--section=RW \
--annotation=./extra/stack_analyzer/example_annotation.yaml \
./build/elm/RW/ec.RW.elf
make BOARD=elm SECTION=RW \
ANNOTATION=./extra/stack_analyzer/example_annotation.yaml \
analyzestack
Change-Id: I9d443df6439b55d5b92a7624bdd93cb6e18494e2
Signed-off-by: Che-yu Wu <cheyuw@google.com>
Reviewed-on: https://chromium-review.googlesource.com/640393
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When my 15V/30W charger is plugged in scarlet,
I see rt946x (the battery charger on Scarlet) asserts OVP because
VBUS(15V) > VBUS_OVP(14V) defined in rt946x datasheet.
So we should limit the maximal VBUS to ~13V even if the source can
provide higher voltage.
Meanwhile, let's replace some numbers with macros for better
maintainability.
BUG=b:65118519
BRANCH=none
TEST=manually verify charging works with a 15V/30W PD charger
Change-Id: I19b7d8297bdbab0a722c488910fd872eb1395e16
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/639927
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Elan has shipped other AVL IC in Chromebook recently.
And it will support hammer project "charger"
Original code use constant definition for FW page count.
Unfortunatlly new IC's page count is different.
I add a code to judge IC first,
and then get the correct page count before FW updating
Signed-off-by: KT Liao <kt.liao@emc.com.tw>
BRANCH=none
BUG=None
TEST=Execute fw updating in hammer system
Change-Id: Ibdd9f7c0b61118950d8e751b7bbaaefeaaa3fb27
Reviewed-on: https://chromium-review.googlesource.com/620451
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: KT Liao <kt.liao@emc.com.tw>
Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
-Routing HPET1 timer requires HPET's General Config register's Legacy
routing bit should be set.
-For HPET0 interrupt, no need to set IRQ# to T0C register.
-change IRQ# back to default values.
BUG=None
BRANCH=master
TEST=`Build ISH and verify the timer interrupt via various
console cmds`
Change-Id: I9f83d62a1f7d999ebf6cedafd38691531ec91081
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/627628
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Before all of the charge suppliers are initialized,
charge_manager_refresh() wouldn't be called to update
charging voltage/current.
Since we don't define CONFIG_USB_CHARGER, we need
to do the initialization in board specific files.
BUG=b:65118519
BRANCH=none
TEST=manually verify charging voltage/current are updated
Change-Id: Ib0c226c236b8add0dcba7bf3610da47c26166732
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/639926
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The device state machines aren't quite similar enough to use common
code. Split the AP state machine out, the way we split out the EC
state machine in the previous CL.
BUG=b:35587387
BRANCH=cr50
TEST=manual, with Cr50 strapped (or hard-coded) not to use platform reset
and not to use TPM reset to detect the AP:
Pull CCD_MODE_L low, so Cr50 detects/enables CCD
Pull AP_DETECT high.
Pull INT_AP_L low (with resistor).
Pull AP_DETECT low --> See 'AP off' message
gpioget --> INT_AP_L=0
ccd --> AP UART disabled
Pull AP_DETECT high --> See 'AP on' message
gpioget --> INT_AP_L=1
ccd --> AP UART RX+TX
Pull AP_DETECT low for <1 sec then back high
(don't see AP off/on message)
gpioget --> INT_AP_L=1
ccd --> AP UART RX+TX
Reboot with AP_DETECT still low -> AP off at 1 second
Reboot with AP_DETECT still low and then assert AP_DETECT
within a second -> AP on immediately
Repeat with Cr50 strapped/hard coded to use platform reset, but
using TPM_RST_L instead of AP_DETECT. Note that this will also
show TPM reset debugging output when TPM_RST_L is asserted.
Change-Id: Ief9e4e5f2585ff925de1595cc8fbd5306c94a806
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/634248
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Previously, some code paths such as CCD permissions change could
result in enabling EC or AP UART RX when the EC or AP is off. This
could result in interrupt storms.
BUG=none
BRANCH=cr50
TEST=manual
// Initial conditions
Assert CCD_MODE_L
Deassert DETECT_SERVO
// Both RX and TX disabled when processor turns off
// and re-enabled when it turns back on
Deassert DETECT_EC
ccd -> EC UART disabled
Assert DETECT_EC
ccd --> EC UART RX+TX
Deassert DETECT_AP
ccd -> AP UART disabled
Assert DETECT_AP
ccd --> AP UART RX+TX
// TX disabled when CCD disabled
Deassert CCD_MODE_L
ccd --> EC UART RX, AP UART RX
Assert DETECT_SERVO
ccd --> EC UART RX, AP UART RX
// Don't enable TX when detecting EC, if servo is connected
Deassert DETECT_EC
ccd -> EC UART disabled
Assert DETECT_EC
ccd --> EC UART RX
// Don't enable TX when detecting CCD, if servo is connected
Assert CCD_MODE_L
ccd --> EC UART RX, AP UART RX
// When servo disconnects, enable TX if CCD is connected
Deassert DETECT_SERVO
ccd --> EC UART RX+TX, AP UART RX+TX
Change-Id: Icb144c23e949afb0384c242965aa729b078b03eb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/642349
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
LPC area for sensors support 3 sensors:
up to 2 accelerometers and 1 gyro.
If only 1 accelerometer is present, only the first accelerometer slot is
populated.
If there is no gyro, the gyro slot is not populated.
Add tests and remove assumption in the code to be sure the rules above
are enforced.
BRANCH=none
BUG=b:64232053
TEST=compile, check eve is still working.
On soraka:
ectool motionsense odr 2 10000
ectool motionsense
output matches:
grep . /sys/bus/iio/devices/*/in_*_raw
Change-Id: Ifd791a6fa89d94bf91ad1a65b8987f69bada801e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/639319
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Allow reporting that keyboard backlight doesn't exist even when the code
is compiled in. Useful if there are multiple device models that should
share firmware.
BUG=b:64705535
BRANCH=none
TEST=none
Change-Id: I9c1fc370aedf66ef856a571f73831095d27e3d39
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/633926
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
we need to properly restart the anx3429 after a firmware update.
simply initializing the chip doesn't seem to get it to reload its
firmware - at least not the portion of the chip that implements the
firmware version register. so, we explicitly power down and reset the
chip before reinitializing it to force it to run the new firmware.
the chip also needs a 10ms "off" time so the reset is properly seen by
the chip, so i did a light refactoring of the code paths that reset
the anx3429.
TEST=used 2 different firmware blobs and verified it switches between
them during software sync.
BRANCH=none
BUG=b:35586895
Change-Id: I967898dd906f21bdc5bc4ce9c1dff9f873d198c1
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/631976
In order to test certain devices in the test lab using cased closed
debugging (CCD), we need a mechanism to programmatically "press" the
recovery button. Even though this signal is being buffered through the
EC to the AP, and the EC could theoretically set it if needed, we cannot
trust the EC in its RO image since it may speak to the outside world
over USB PD.
Instead, this commit introduces a console command on cr50 that can be
used to force the recovery button state to be pressed. However, it is
gated behind the CCD capabilities defaulting to the IfOpened state.
Additionally, a new vendor command is added to query the trusted state
of the recovery button. The AP should use this command instead of
trusting the GPIO connected to it.
BUG=b:37751915, b:64146626
BRANCH=cr50
TEST=Flash cr50. Press KEY0, verify that reported rec btn follows the
state of the button.
TEST=`recbtnforce enable` causes the button to be reported as pressed.
Physical presses of the button do not alter the reported state.
TEST=`recbtnforce disable` causes the reported state to follow that of
the physical button.
TEST=The `recbtnforce` command is set to the IfOpened capability by
default.
TEST=CCD locking the DUT and attempting to force the recovery button
results in an error of access denied. The physical state is reported.
TEST=From the AP, issue the vendor command to retrieve the button state
and verify that it behaves as expected.
Change-Id: Ib8c2928e75e5f9a1a83c5361664efc3fa0ae2ddb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/635955
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Add a function to translate device_state enum into a string, then use
it for printing the ec and RDD state.
Refactor ec_state so that all state transitions go through a
set_state() function, which makes it easier to turn on debugging all
state transitions. That's normally not compiled in because it would
be spammy during debouncing.
BUG=none
BRANCH=cr50
TEST=ccd command prints EC and RDD states
Change-Id: Ie7bc56c7b66beee23d1d1989711c640e5e39ce43
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/642121
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Now that there are separate board config functions, use
!board_detect_ap_with_tpm_rst() to decide whether to configure
DETECT_AP on DIOA3, not board_use_plt_rst().
BUG=none
BRANCH=cr50
TEST=Boot cr50 strapped to use platform reset. See that 'gpioget'
shows DETECT_AP does not respond to changes on the DIOA3 pin.
Boot cr50 strapped not to use platform reset. See that 'gpioget'
shows DETECT_AP responds to changes on DIOA3.
Change-Id: Ieb05015c948b2bbafa744f00a11e6b3da143ca5b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/642120
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
By default the input current on Scarlet is limited to 500mA,
which is defined by ILIM pin.
We need to disable the control from ILIM pin to draw more
current from the source.
BUG=b:64821815
BRANCH=none
TEST=manually monitor the charging current
Change-Id: Ia356a2397b3671c178479a581b44a17215fee83d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/639918
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
convert_servo_ina.py can convert power log config
files from hdctools/servo/data into sweetberry configs
BRANCH=None
BUG=b:35578707
TEST=compare kevin_r0_loc.py output with kevin.board
Change-Id: Iadc57fe4eb1f5b220c6bffe3a3fe8a10b0d6b5a2
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/634486
fusb302 determines attach / no-attach (and Rd / Ra) by comparing CC
voltage against an MDAC output (42 mV steps). The previous 'floor'
calculation was particularly bad for 3.0A Rp (2600 / 42 = 61, 61 * 42 =
2562 mV - 21 = 2551 mV actual threshold, ignoring other error sources).
Reduce the chance of error by rounding our thresholds, which also
matches the suggested thresholds in the datasheet.
BUG=chromium:758608
BRANCH=gru
TEST=Attach problematic dingdong, verify we don't enter an attach /
detach loop.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9211782da0fdad8339246e272952ba1930b69851
Reviewed-on: https://chromium-review.googlesource.com/633276
Reviewed-by: Joe Bauman <joe.bauman@fairchildsemi.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 311b3e4e15fd37ea2ab151edb8b8a468e93355fd)
Reviewed-on: https://chromium-review.googlesource.com/638694
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
For some boards, the control lines to the charging port controller are
all tied to a power rail. In essence, this leaves the ILIM_SEL as the
only signal able to be controlled, which means that we only support
CDP/SDP.
This commit adds a new CONFIG_* option which describes this.
CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
Additionally, some cleanup is made to not always assume the number of
smart power ports.
BUG=None
BRANCH=None
TEST=make -j buildall
Change-Id: I080ccd67ffc20ccccf1e6b33a3cf9374a6b70ad6
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/634274
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The way Cortex processors handle exceptions allows writing exception
routines directly in C, as return from exception is handled by providing
a special value for the link register.
However, it is not safe to do this when doing context switching. In
particular, C handlers may push some general-purpose registers that
are used by the handler and pop them later, even when context switch
has happened in the meantime. While the processor will restore {r0-r3}
from the stack when returning from an exception, the C handler code
may push, use and pop another register, such as r4.
It turns out that GCC 4.8 would generally only use r3 in svc_handler and
pendsv_handler, but newer versions tend to use r4, thus clobbering r4
that was restored from the context switch and leading up to a fault
when r4 is used by the task code.
An occurrence of this behaviour takes place with GCC > 4.8 in __wait_evt,
where "me" is stored in r4, which gets clobbered after an exception
triggers pendsv_handler. The exception handler uses r4 internally, does
a context switch and then restores the previous value of r4, which is
not restored by the processor's internal, thus clobbering r4.
This ends up with the following assertion failure:
'tskid < TASK_ID_COUNT' in timer_cancel() at common/timer.c:137
For this reason, it is safer to have assembly routines for exception
handlers that do context switching.
BUG=chromium:631514
BRANCH=None
TEST=Build and run speedy EC with a recent GCC version
Change-Id: Ib068bc12ce2204aee3e0f563efcb94f15aa87013
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://chromium-review.googlesource.com/362830
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Zero ITERM_SET to keep the charger out of topoff mode, since it has
undesirable side-effects related to dead / low battery charging.
BUG=b:35575421
BRANCH=reef
TEST=Previous testing on kevin with same register setting.
Change-Id: Ic1dd280e1069d410895498c0f72989654a6b8c63
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/636152
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
--power provides a single sample from the INA
--powerlog [n] provides n samples
--check_version returns the tigertail's firmware version
--bus selects which bus to probe power on [vbus|cc1|cc2]
BRANCH=None
BUG=b:35849284
TEST=check power readings, version.
Change-Id: I728d954b6649fe0401093bf3beb7ec89f27822a6
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/634566
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The device state machines aren't quite similar enough to use common
code. Split the EC state machine out, the way we split out BattPrsnt
and CCD_MODE.
BUG=b:35587387
BRANCH=cr50
TEST=manual
Pull CCD_MODE_L high, so Cr50 detects/enables CCD
Pull EC_DETECT high.
reboot -> 'EC RX only', then 'EC on' at 1 second
Pull EC_DETECT low --> See 'EC off' message
ccd --> EC UART disabled
Pull EC_DETECT high --> See 'EC on' message
ccd --> EC UART RX+TX
Pull EC_DETECT low for <1 sec then back high
(don't see EC off/on messages)
ccd --> EC UART RX+TX
Reboot with EC_DETECT still low -> EC off at 1 second
Reboot with EC_DETECT still low and then assert EC_DETECT
within a second -> EC RX only, then EC connect at 1 second.
Change-Id: I71687e651d625cadd656934f4cb2bbadc0b58816
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/619750
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
fetching the chip firmware version toward the end of the chip
anx74xx_tcpm_init() sequence is a good place to do this. we need this
info in any case and this is a safe place to access device registers
and cache the values. subsequent chip firmware queries typically
return the cached value. also, tcpci_tcpm_init() is already
structured this way.
TEST=verified with follow-up CL that firmware update succeeds and new
version is reported
BRANCH=none
BUG=b:35586895
Change-Id: Ic3fd07bbf8a220bfd506d59d8a1f3ea25b14e94c
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/634513
Reviewed-by: Shawn N <shawnn@chromium.org>
For system using core/minute-ia, build will fail since __image_size is
not defined. If later this variable is used, should adjust its value
properly.
BUG=none
BRANCH=None
TEST=Build passed for Soarka ISH which uses core/minute-ia.
Change-Id: I8e179e0bac551a46d93ca10ba8b61b4ebade74fc
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/595151
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
TEST="make buildall" succeeds, "make runtests" passes for reef.
returning SUCCESS instead of UNIMPLEMENTED from .release() means the
pd_task() is allowed to reinitialize the TCPC when coming out of
PD_STATE_SUSPENDED or similar scenario.
TEST=verified anx3429 firmware update succeeds, USB port still usable
for charging after update.
BRANCH=none
BUG=b:35586895
Change-Id: I1a624ccf25dfa6468de72f8564f936bc0a35edb1
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/596797
Reviewed-by: Shawn N <shawnn@chromium.org>
Add some board property functions that describe what behavior we are
checking instead of just using board_use_plt_rst. More devices are
getting deep sleep support. This changes some function names to make the
transition easier.
This change adds board_use_deep_sleep and board_detect_ap_with_tpm_rst.
Right now both of these just call board_use_plt_rst. This will
eventually change with the expansion of deep sleep to new devices.
BUG=none
BRANCH=cr50
TEST=run firmware_Cr50DeepSleepStress with 10 suspend/resume cycles
Change-Id: I8d9ef23f686dea788d26ac4973054ad027fdd3a4
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/633891
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
