Add support to enable the architectural D-cache on ARMv7-M CPU
supporting it.
Update the MPU code in order to be able to declare an 'uncached' RAM
region (e.g. to store the DMA buffer).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:78535052, b:75068419
TEST=with the following CL, on ZerbleBarn, boot and capture a finger
image.
Change-Id: I275445e7c0b558cedc3e7d6fc6840ff9b4b76285
Reviewed-on: https://chromium-review.googlesource.com/1032776
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
With the Cortex-M7 core on STM32H7, the imprecise bus abort triggered by
the flash permission check might be propagated rather than ignored as we
might have gone through the ignore_bus_fault(0) before the exception
actually happens.
Add a barrier to avoid this case.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:75068419
TEST=On ZerbleBarn with MPU on and caches enabled, verify that the
flash_set_protect() in rwsig_jump_now() no longer triggers an imprecise
abort.
Change-Id: I8ed4f13cb7a379964919bf389542221517a34c17
Reviewed-on: https://chromium-review.googlesource.com/1080809
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
ID pins are considered additional KSOs while keycode scanning works
for the existing KSI0 ~ KSI7. While diriving ID pins, the state of
interconnection between ID pins and KSI pins could be used for
identifiers to tell keyboard itself. (e.g. US, Japan,and UK keyboard)
BRANCH=master
BUG=b:80168723
TEST="make -j buildall"
TEST=Verified 5 distinct keyboard samples w/ different Language ID values
on the same reworked Coral, which VOL_UP and VOL_DOWN were reworked
for ID pins. crrev.com/c/1053617 is my experimental patch on top of
this for further verification
Change-Id: I1d6e647df74c50d60bc1264c045b2587d0bf23d8
Signed-off-by: paris_yeh <pyeh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1068951
Commit-Ready: Paris Yeh <pyeh@chromium.org>
Tested-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Some tests cannot be built on some boards (not enough SRAM,
unusual configuration, etc.). Instead of the long list of
exceptions in test/build.mk that we currently use, allow
each board (or chip) build.mk to set test-list-y, and
only use the default list if it is unset.
BRANCH=poppy
BUG=b:80167548
TEST=make buildalltests -j
Change-Id: I803c691f419451aad4396529302a4805cbe3f9b5
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1074572
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
SERIIRQ# is by default deasserted level high. However, when using
eSPI, SERIRQ# is routed over virtual wire as interrupt event. As per
eSPI base spec (doc#327432), all virtual wire interrupt events are
deasserted level low. Thus, it is necessary to configure this
interrupt as inverted. ITE hardware takes care of routing the SERIRQ#
signal appropriately over eSPI/LPC depending upon the selected mode.
BUG=b:79897267
BRANCH=None
TEST=Verified using evtest that keypresses are properly identified on
the OS side.
Change-Id: Ie3b92f20fa915ba8f17dcbcb600ebfe5cbfb4d57
Signed-off-by: Dino Li <dino.li@ite.corp-partner.google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1069570
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
This makes it easier to add params or flags for vendor commands
without changing all of the command handlers. It also reduces code
size by 56 bytes.
For now, existing command handlers continue to use
DECLARE_VENDOR_COMMAND(). Added DECLARE_VENDOR_COMMAND_P() for
handlers which take the params struct directly. The CCD command will
be the first user of that, since it will have different rules for
'open' based on where the command comes from.
No change to existing command behavior.
BUG=b:79983505
BRANCH=cr50
TEST=gsctool -I still works
Change-Id: I7ed288a9c45e381162e246b50ae88cf76e67490d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1069538
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Change prefix from CONFIG_ESPI to CONFIG_HOSTCMD_ESPI for consistency.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: I8b6e7eea515d14a0ba9030647cec738d95aea587
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067513
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Observed task stack sizes growing, especially PD related.
Adjust chip configuration for 64KB data.
Use RAM size config items in flash layout config items.
Update SPI image generator python script to not add
a Boot-ROM header to EC_RW and add a test mode for debugging
SPI read and hash calculations.
BRANCH=none
BUG=
TEST=Build boards based on chip mchp. Check RO and RW
EC binaries are correct size and located properly in
ec.bin
CQ-DEPEND=CL:1036258,CL:1053576
Change-Id: I12709a434d5aaa84fabe459176a3423365343308
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053948
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added flags parameter to extension_route_command(). The caller now
specifies whether the command comes from the USB interface or the AP.
Moved USB-specific shuffling of response to embed result code into
usb_upgrade.c, so extension_route_command() can be more generic.
No change to permissions/behavior for existing commands.
ccd_command_wrapper() still sends vendor commands as if they come from
the AP. That's fixed in the next CL.
Reduces code size by 128 bytes
BUG=b:79983505
BRANCH=cr50
TEST=manual
Build with DEBUG_EXTENSION defined, to turn on printing each command
'ccd lock' comes from AP and works
From host, 'gscutil -I' comes from USB and fails
From AP, 'gscutil -t -I' comes from AP and works
Change-Id: I7136bb54073de9c5951a174c308151b1871c56f3
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1068101
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The new GCC build shows a warning/error in clock-f.c:
'alarm_us' may be used uninitialized in this function
[-Werror=maybe-uninitialized]
This is actually a fake warning. In the context of the logic,
there is no way 'alarm_us' would be used uninitialized.
But let's still initialize 'alarm_us' to clear the compiler warning.
BUG=none
BRANCH=scarlet
TEST='USE=coreboot-sdk emerge-scarlet chromeos-ec'
TEST=make buildall -j
Change-Id: I7a0642cbe03c5a0adb6997ddc80c9cb797715749
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1068256
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Martin Roth <martinroth@chromium.org>
Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
AP and EC consoles may generate a lot of bursty traffic, and cr50 UART
console to USB processing is very slow: when characters become
available, a hooks task callback is invoked, which retrieves received
characters one at a time and queues them up to the appropriate USB
transmit queue.
This patch speeds up things as follows:
- increases the seize of USB transmit queues for AP and EC console
channels to 512 bytes. Experiments supported by code
instrumentation has shown that even this is not enough to avoid
underruns, but this is a good compromise between memory use and
performance, these sizes could be revisited later,
- raises UART RX interrupt priority from level 1 to 0
- moving bytes from UART TX FIFO to USB queue happens on the
interrupt context when UART TX interrupt is asserted
- as many characters as possible are read from the UART first,
before queuing function is called, and the entire received batch
is passed to the queuing function.
It has to be mentioned here that presently batch processing is not
necessarily much more efficient, because queuing function becomes
more complicated when multiple objects are passed to it, this will
have to be dealt with in a separate patch.
There is still a lot of room for improvement:
- functions used to queue up data are very generic, dedicated code
could help a lot.
- UART drivers should have methods for collecting all bytes
available in receive FIFO in one invocation,
- USB side of things (dequeuing data and passing it to the
controller.
BRANCH=cr50, cr50mp
BUG=b:38448364
TEST=ran 'chargen' application on both AP and EC to flood the console
channels and observed the flow of characters on the host site, it
is pretty smooth with occasional hiccups, especially when TPM is
active, before this patch it was impossible to have both stream
up, both were garbled.
- Verified that new account can be created and user logged in on
restarts while chargen is running, i.e. TPM task gets enough
processing bandwidth.
- When EC is reset, there seem to be no lost characters on the
console (it used to cause some garbled console output before this
patch). The below output was collected on Coral:
> reboot
Rebooting!
--- UART initialized after reboot ---
[Reset cause: soft]
[Image: RO, coral_v1.1.8363+2cc945d5a 2018-05-15 17:41:57 ...
[0.003605 init buttons]
[0.003826 Inits done]
[0.004094 tablet mode disabled
]
[0.008272 found batt:SMP]
[0.022278 SW 0x01]
[0.042247 hash start 0x00040000 0x00021994]
[0.045823 Battery FET: reg 0x0018 mask 0x0018 disc 0x0000]
[0.071136 kblight registered]
[0.071544 PB init-on]
[0.071818 USB charge p0 m0]
[0.073670 ID/SKU ADC 4 = 1309 mV]
[0.075630 ID/SKU ADC 3 = 852 mV]
[0.076077 SKU ID: 71]
[0.076335 Motion Sensor Count = 3]
[0.083594 PD comm enabled]
...
- did not test bitbang programming mode, it is in line for
reworking for speeding up as well.
Change-Id: Ic9f3972f585dd1976169965c2a2422253aeac87a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1016037
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The factory tests relies on being able to read CEC_IN through the
GPIO API. When it is configured as TA1, it can't be read as a
GPIO. With this change, the pin will be a reconfigured as a GPIO
at boot or when CEC is runtime disabled using "ectool cec set
enable 0"
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:79842676
BRANCH=none
TEST=Test that "ectool cec read" still works with CEC on, and
that "ectool gpioget CEC_IN" reflects the incoming voltage when
CEC is off.
Change-Id: I3b17d6551612a156897d95ea2473e4fbcbd70e39
Reviewed-on: https://chromium-review.googlesource.com/1064110
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
When pushing to the circular buffer, the read-offset mutex is no
longer taken, so don't unlock the mutex.
Don't allow writing to the last byte of the buffer. In that case,
the read and write pointers will become equal and the buffer will
be treated as empty.
Add handling for pushing messages of invalid size.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Turn on/off TV:
ectool cec write 0x40 0x36
ectool cec write 0x04 0x40
Verify that incoming messages still works when turning off TV:
ectool cec read -- -1
Change-Id: Id207c442fac573430aac0c744ec07fa203074228
Reviewed-on: https://chromium-review.googlesource.com/1068945
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Some boards (like nocturne) use PSL mode, but the deassertion of PSL_OUT
does not directly cut the EC's VCC1 rail. Therefore, the board needs to
implement a board specific implementation of hibernate while also being
able to configure PSL mode. This commit exports a function of entering
PSL mode which could be used in a board specific hibernate
implementation.
BUG=b:79713379
BRANCH=poppy
TEST=`make -j buildall`
Change-Id: I8debcae5e713b85c6d23ee3419416b6ae5d5dbf0
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1067891
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Expose the i2c interface through usb so that we can read power rails
through servod leveraging the work being done there.
BRANCH=none
BUG=chromium:806148
TEST=manual testing
- powerlog still works
- i2c over usb using servod code works (other CLs needed)
Change-Id: I48876bc4839509a397ce77376b337c37c556ae40
Signed-off-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1051136
Reviewed-by: Nick Sanders <nsanders@chromium.org>
gcc 8.1 complains about duplicate const, and while some of these really
are duplicate, others look like they were supposed to tighten the API
contract so that variables are "const pointer to const data", but didn't
have that effect.
BUG=b:65441143
BRANCH=none
TEST=building Chrome EC as part of upstream coreboot's build with a
gcc 8.1 compiler now works (better. there are other issues left)
Change-Id: I6016c5f282516471746f08d5714ea07ebdd10331
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1039812
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Before:
*** 4560 bytes still available in flash ****
After:
*** 4696 bytes still available in flash ****
BRANCH=none
BUG=b:65253310
TEST=Update Cr50 with this image and verify the keys are the same.
Change-Id: I1c722ced185c41f732ce0ed5236db01401f21dfc
Signed-off-by: Allen Webb <allenwebb@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1031058
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Gemini Lake-based chipsets support a subset of virtual wires that other
Intel processors do. The current settings prevent the GLK APs from
bootign in some situations; PLTRST# doesn't get reasserted when there is
an error.
See "eSPI Compatibility Specification (562633)" for details.
BRANCH=None
BUG=b:79778835
TEST=Successfully booted bip after a cold reset from servo
Change-Id: I02b403ab6b06cbcae61ac46132018e95988a3d43
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1064704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>
When running signed with dev keys and the fallback certificate is not
available, proceed installing unverified root certificate. This at
least allows to keep basic TPM functions like storing objects in NVMEM
to keep going. Added a new return value to indicate this condition.
BRANCH=cr50, cr50-mp
BUG=none
TEST=verified that it is possible to switch chromebook between prod
and dev modes when running with a dev signed Cr50.
Change-Id: I5b16d0bcbcfb25368f65075e1d2d485a69cb729f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1054990
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Usually, we enable CONFIG_FPU on NPCX, which requires larger
stack size. Also, NPCX has very deep call patch in I2C transactions
(in particular, I2C recovery path), so it generally requires larger
stack.
To make the code fit, however, we need to reduce the accelerometer
fifo depth from 1024 to 512, on a few boards.
BRANCH=none
BUG=b:75234824
TEST=make buildall -j, stackanalyzer result on poppy looks a little
better.
Change-Id: I37b5a2a97a760dc4fd225253c23962d74e25605a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/967963
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
AES-CMAC implementation based on extant 128-bit AES, following closely
to the description in RFC 4493. Timing depends only on the length of the
message, not the content or the keys.
Signed-off-by: Jade Philipoom <jadep@google.com>
BRANCH=cr50
BUG=b:72788497
TEST=Passed the four test vectors provided in the RFC; these tests are defined as commands in aes_cmac.c and can be run with
"test_cmac 1 2 3 4" when CRYPTO_TEST_SETUP is defined.
Change-Id: I96fb4f29927c11970a6a17c0fd583694aa945c91
Reviewed-on: https://chromium-review.googlesource.com/975181
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Instead of fetching incoming CEC messages using a specific read
command, extend the standard mkbp event so the CEC message can
be delivered directly inside the event.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST="ectool cec read" still working with a kernel that has support
for the increased mkbp size.
CQ-DEPEND=CL:1046186,CL:1051085
Change-Id: Id9d944be86ba85084b979d1df9057f7f3e7a1fd0
Reviewed-on: https://chromium-review.googlesource.com/1051105
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Logical address selection is best done from the AP since
it depends on what kind of CEC device type we want to be.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Set address to different values and verify that it
only receives messages on that address (or broadcast)
CQ-DEPEND=CL:1030229
Change-Id: Ia5ef182b22f2345831caaa7f29cc9f009f932c99
Reviewed-on: https://chromium-review.googlesource.com/1030370
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If pulses shorter than the CEC specification allows are detected,
ignore the bus for a while. This avoids CPU stress if there is a
misbehaving device sending short pulses on the CEC bus.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=none
CQ-DEPEND=CL:1030228
Change-Id: I55819f9437a00799718e235c30f256508465bf4c
Reviewed-on: https://chromium-review.googlesource.com/1030229
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When an incoming message is complete, store it in a
internal circular buffer and notify the AP so the
message can be read out.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Write different type of messages from one EC to another EC
using ectool. Also use ectool on the second EC to verify that
they are received correctly.
CQ-DEPEND=CL:1030226
Change-Id: Ie4370b0c954befe81a055cd5dff7d7f13dbefbd0
Reviewed-on: https://chromium-review.googlesource.com/1030227
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Adds handling of incoming messages:
* Start-bit detection
* ACK incoming messages
* Broadcast handling
* Pulse-width validation
* EOM detection
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Tested in later CL when messages are plumbed all the
way back to the AP.
CQ-DEPEND=CL:1030225
Change-Id: I541072b8afa3d911b310628f09f0b665f11a0a15
Reviewed-on: https://chromium-review.googlesource.com/1030226
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
