Only report alert status if the PD chip is not being held in reset.
(idea borrowed from Amenia's implementation)
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: Ic637b1ab4e20527c806311a45c149b9ea5f64362
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360020
Reviewed-by: Martin Roth <martinroth@chromium.org>
Proto brought up 5V, 3.3V, and PMIC very early in the EC boot process
due to dependencies in the power topology. This had some other side-
effects, for example, a lot of the power rails would already be up by
the time the EC got around to processing the power state machine thus
leaving it waiting for signal changes that were supposed to come
later but had already occurred instead.
This patch updates the nominal codepath for rail and PMIC init on EVT
while using IS_PROTO to retain the Proto sequence if desired.
BUG=chrome-os-partner:54962
BRANCH=none
TEST=built and booted on proto and evt boards with subsequent patches
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: If9ddd41044f132e719b0b7f0ab80ed908ddb1d9b
Reviewed-on: https://chromium-review.googlesource.com/358913
Reviewed-by: Martin Roth <martinroth@chromium.org>
This removes write-protect ranges that are unnecessary so
that we save a bit of space.
BUG=chromium:633431
BRANCH=none
TEST=compiled only.
Change-Id: Ib34c6a125b001fc92a21f795ac3d922e77143342
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Print the reply bytes, be more consistent between %d and %x.
BUG=none
BRANCH=none
TEST=manual
Build debug version, verify that it prints more stuff.
Change-Id: I8c8a983360f4895ccc72b73ed67ce2d45a461bad
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365120
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
The kernel DP driver do not support hpd gpio detect, it use
EXTCON_DISP_DP cable state to decide power on/off DP PHY. Hence, do not
change GPIO_USB_DP_HPD level, but set or clear the TYPEC_MUX_DP when hpd
level changing in attention.
BUG=chrome-os-partner:52872
BRANCH=none
TEST=keep Type-C Dock inserted
1. plug HDMI cable, check with "ectool usbpdmuxinfo"
Port 0: USB DP
2. unplug HDMI cable, check with "ectool usbpdmuxinfo"
Port 0: USB
Change-Id: I369a92135bf0ca177e81eab6385980d51d863172
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/364401
Commit-Ready: Guenter Roeck <groeck@chromium.org>
Tested-by: Guenter Roeck <groeck@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The chip revision and board version show up on the second line of
the returned string, immediately before the build info.
BRANCH=none
BUG=chrome-os-partner:55558
TEST=Queried version string using tpm_test
make -C test/tpm_test && sudo ./test/tpm_test/tpmtest.py
Starting MPSSE at 800 kHz
Connected to device vid:did:rid of 1ae0:0028:00
RO_A:* 0.0.2/d0c9abe3 RO_B: 0.0.2/13eda43f RW_A: cr50_ [...]
B2:0 cr50_v1.1.5013-ab0e228+ [...]
^^^^
Change-Id: Iaa1efe5dca441aca24f281f76c1f218e24c844be
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365421
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Enable the SHI interrupt only after we have received and begun
processing our host command. Disable the SHI interrupt once our
transaction is complete (with either success or error status). This will
prevent the SHI interrupt from being asserted at the same time as the CS
interrupt, which can lead to the SHI interrupt being serviced first.
Also, it avoids needless, non-useful SHI interrupts during error
transactions.
BUG=chrome-os-partner:55710,chrome-os-partner:55795
BRANCH=None
TEST=Manual on gru. Stress test flashrom w/ unpowered Donette attached
(for host command spam), verify no errors encountered after 100 minutes.
Change-Id: I0ab20b0202ebcfe15c04b272ec67001a6a358dad
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364698
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Add functions to initialize and disable the radio.
Add packet definitions.
Update the spelling of the FICR_OVERRIDEEN register.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: I3a9e500d0f177b6ce77a3b6ed6a42acd4f49eb7e
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362175
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Levi Oliver <levio@google.com>
Image sizes must be aligned to block erase size to ensure that the host
can erase the entire image and nothing but the image.
BUG=chrome-os-partner:55828
BRANCH=None
TEST=Manual on kevin, rebuild FW with new EC, rebuild + flash EC once
again, verify that SW sync completes and unit boots to OS.
Change-Id: If6110f39869d6421038a3fe7afdc7d918323249e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365142
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Both build string (which includes status of all firmware components of
the running image) and the firmware version string (which show
versions of various objects in the flash) are important to the user.
Let's include both of these strings into the TPM_FW_VER register
output. Buffer storing the string needs to be increased accordingly.
BRANCH=none
BUG=chrome-os-partner:55558
TEST=verified the contents of the AP firmware console log:
localhost ~ # grep cr50 /sys/firmware/log
Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A: ...
cr50_v1.1.5003-af11829+ private-cr51:v0.0.66-bd9a0fe tpm2:v0.0.259-8f3d735...
Change-Id: I67df3e810bd07053d0b7d8b6fac350253ca06bb0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364830
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Cr50 cant retain the TPM state in deep sleep so it wont be enabled until
it knows that the AP is off. If the AP is off it wont be asserting
SPS_CS_L, but it may be low because the AP isn't pulling it up.
This change disables it as a wake source in deep sleep.
BUG=chrome-os-partner:54796
BRANCH=none
TEST=run 'idle d'. Make sure cr50 goes into deep sleep and only resumes
due to a rdd event or when sys_rst_l is asserted.
Change-Id: Idf3ded6b439b71a27ac7eb4682a65dcdd6342cb9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364864
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The existing algorithm makes several assumptions for a particular
thermistor circuit. This patch introduces a more generic version
that can be used for multiple thermistors on a single board.
The idea is to approximate a curve produced by solving for voltage
measued by an ADC using the Steinhart-Hart equation. For a straight
line one only needs two data points. For a steady curve data
points can be distributed evenly. For the most part, though, data
points should be provided after a significant change in slope.
More data points give more accuracy at the expense of memory, and
we mostly only care about accuracy in the range between "warm"
and "too hot" so only a few data points should be used.
BUG=chrome-os-partner:54818
BRANCH=none
TEST=added unit test, needs real testing
Change-Id: I046e61dbfd1e8c26c2a533777f222f5413938556
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/344781
Reviewed-by: Shawn N <shawnn@chromium.org>
Increasing the USB console TX buffer size allows to see pretty much
all early startup messages generated before USB console is
initialized.
There is still plenty of room left in SRAM, 23K on cr50, much more on
all other g based boards.
BRANCH=none
BUG=none
TEST=observed better USB console output on cr50 restarts.
Change-Id: I82f37ee7f3aecd8b7e95f3d421789c11375b2fd4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364811
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Nadim Taha <ntaha@chromium.org>
As the version string grows longer, reading it in 4 byte chunks
becomes more and more expensive, the overhead of setting up a separate
SPI transaction per very chunk is just too much.
There is no reason not to allow the host to read as many bytes at a
time as it requires (limiting it by the maximum version string buffer
size of course).
BRANCH=none
BUG=chrome-os-partner:55558
TEST=verified that the version string is still read properly by the
TPM driver on Kevin
Change-Id: Ib76cd151e8dc32374f87135af36266b4ec725a56
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364831
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The only place where two separate buffers for the RO version strings
is required is the tpm_registers.c:set_version_string() function.
In preparation of reporting the build string along with the version
string, let's rearrange the function not to require separate buffers
for the RO versions.
BRANCH=none
BUG=chrome-os-partner:55558
TEST=verified that version reported by the TPM driver on Kevin is
still correct:
localhost ~ # grep cr50 /sys/firmware/log
Firmware version: RO_A: 0.0.1/84e2dde7 RO_B:* 0.0.2/13eda43f RW_A:*...
Change-Id: I8924ac48bd838851670f0d659e95aa92a8524665
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364587
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Some boards now provide very long build version strings including
version strings of multiple subcomponents.
Let the version command split those long lines printing each
subcomponent's version string in a separate line.
BRANCH=none
BUG=chrome-os-partner:55373
TEST=verified on cr50:
> vers
Chip: g cr50 B2
Board: 0
RO_A: 0.0.1/84e2dde7
RO_B: * 0.0.2/13eda43f
RW_A: * cr50_v1.1.4980-2b9f3e1
RW_B: cr50_v1.1.4979-8cec36d+
Build: cr50_v1.1.4980-2b9f3e1
private-cr51:v0.0.66-bd9a0fe
tpm2:v0.0.259-2b12863
cryptoc:v0.0.4-5319e83
2016-07-28 20:40:55 vbendeb@kvasha
Change-Id: Ie14af3aa9febd5a3b02b273a7ab6302e74777e43
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364491
The recent addition of the multicomponent version string for cr50,
requires further tweaking of the version generating script. In
particular, the CROS_EC_VERSION32 variable used by the "verson" cli
command is not supposed to include any information about subcomponents
of the image, it should reflect the EC version only.
Separating everything after the first space accomplishes that.
BRANCH=none
BUG=chrome-os-partner:55373
TEST=verified that RO_x and RW_x versions are printed properly:
> vers
Chip: g cr50 B2
Board: 0
RO_A: 0.0.1/84e2dde7
RO_B: * 0.0.3/8fe06b9e
RW_A: cr50_v1.1.4992-7c9f891+ private
RW_B: * cr50_v1.1.4989-52b3cc6+
...
Change-Id: I192eb29816dfa963b08aa97f749b978b1367d6b7
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364490
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
As a temp measure until a proper solution is implemented, reset the
restart counter when the PCR_Read command is issued by the host.
This is a good indication that Chrome OS is through the boot process,
as PCR value is used to determine the boot mode.
BRANCH=none
BUG=chrome-os-partner:55667
TEST=installed the new image on a Kevin cr50 and rebooted it in normal
and recovery modes, observed on the cr50 console the message like
> system_process_retry_counter:retry counter 1
Change-Id: Ib55e161d5edbf8f6e2d387fd756b94aa53c20ed8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364311
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Aux switch settings set the polarity and this happens once on every
cable connect. But when the cable is kept connected if the mux is
set to 0 this is also reset and remains 0 for any next valid mux state.
BRANCH=ToT
BUG=chrome-os-partner:55757
TEST=manual:on reef, plug HDMI type-C dongle and check if DUT screen
is displayed on HDMI display for both the orientation.
Change-Id: Ie1320d11d1927acb292dbaf4c932b48cdfd7768e
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/364693
Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The timer test checks the accuracy of the internal timer. After sync,
DUT and TH start counting down one second. After one second, DUT raises
GPIO level. TH determines whether the test passes or not based on how
much more or less time elapsed than one second, assuming its clock is
calibrated.
This test takes advantage of TH running on a bare chip. If the host
were measuring (instead of TH), the timing would be affected by many
software and hardware layers (e.g. UART drivers on DUT and host,
python interpreter, etc.).
BUG=chromium:624520
BRANCH=none
TEST=cts.py --module timer && cts.py --module gpio && make buildall
Change-Id: I535e7772b4d93f1f5d248506f7ea167429a50174
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361384
- Pass-thru to IBF handler code in case both IBHF and IBF interrupts are
pending, in order to properly keep track our Tx byte count.
- Don't disable the SHI IRQ in our host command handler callback since
system-wide interrupts are already disabled.
BUG=chrome-os-partner:55711,chrome-os-partner:55721
BRANCH=None
TEST=Manual on gru with subsequent commit. Verify `flashrom -p ec -r
file.bin` passes 100x with no errors or warnings.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6225ffde1fe0127c7484933fe4a151d22f42415c
Reviewed-on: https://chromium-review.googlesource.com/364234
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Whether the bootrom locks the bootloader or not is deteremined by
fuses and/or flags in the bootloader's signed header. This CL
locks the active bootloader, just case those aren't configured to
do so.
BUG=chrome-os-partner:55261
BRANCH=none
TEST=manual
On an unlocked bootloader, I see this after booting:
> rw 0x40090100
read 0x40090100 = 0x00000001
With this CL applied, I see this instead:
> rw 0x40090100
read 0x40090100 = 0x00000000
Change-Id: I2e1396b7d7e71c8633d97d3cb573e9468eeb51e7
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364280
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Updates for EVT:
- TCPC0 interrupt polarity is now low, define GPIO_INT and set ANX74xx
internal polarity control based on IS_PROTO.
- Swapped pin assignments for USB_C1_PD_INT_ODL and EN_USB_C1_5V_OUT.
- Rename USB_PD_RST_ODL to USB_C0_PD_RST_L and make it push-pull.
- Add USB_C1_PD_RST_ODL
BUG=chrome-os-partner:54958,chrome-os-partner:54952,chrome-os-partner:55165
BRANCH=none
TEST=needs testing
Change-Id: I075934cced532d656f942841c30e3640a6f42568
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/358944
Reviewed-by: Duncan Laurie <dlaurie@google.com>
This ensures that we're only checking the reset signal for the
corresponding interrupt. Otherwise we can hit a race condition
when both TCPC chips are taken out of reset.
(This is also how it's done on Amenia)
BUG=none
BRANCH=none
TEST=needs testing
Change-Id: I47513b3b47e947c8b4644f4d837ddc3fb1ee7a30
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361061
Reviewed-by: Shawn N <shawnn@chromium.org>
This makes board_set_tcpc_power_mode() a noop since that's controlled
by anx74xx code and we have another TCPC chip onboard. Instead, we'll
reset the TCPC chips in a hook that will run after board and I2C init.
This is more like what Amenia code does.
BUG=chrome-os-partner:54952
BRANCH=none
TEST=needs testing.
Change-Id: Id3af4af1014432235b699a9568ee19df63601b2c
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361060
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
It has rare chance for FW to get a unexpected value when reading
IBUFSTAT. This is because the clock source of SHI and CPU are
asynchronous. The reading value is invalid if IBUFSTAT is during
transition state. Use two consecutive equal reading can make sure
the value is valid.
BUG=chrome-os-partner:34346
TEST=run "while true; do ectool version; done" on gru, verify each
failure happens about 50000 host commands
BRANCH=none
Change-Id: Ie246561d201dd87d89cb2424c23d016dcdcd47c9
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/362734
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
'+' flag can be used with signed integer type (%d) and causes positive
integers to be prefixed with '+' (e.g. +1745). This emphasizes output
values as a signed value. It can be mixed with left-justification flag
'-': %-+8d. It's ignored when used with unsigned integer or non-integer
types: %u, %x, %p, %s, %c, etc.
BUG=none
BRANCH=none
TEST=make buildall &&
int32_t d = 1745;
CPRINTS("'%-+8d'", -d); /* '-1745 ' */
CPRINTS("'%-+8d'", d); /* '+1745 ' */
CPRINTS("'%d'", d); /* '1745' */
CPRINTS("'%+08d'", -d); /* '000-1745' */
CPRINTS("'%+08d'", d); /* '000+1745' */
CPRINTS("'%+d'", -d); /* '-1745' */
CPRINTS("'%+d'", d); /* '+1745' */
CPRINTS("'%+s'", "foo"); /* 'foo' */
CPRINTS("'%-+8s'", "foo"); /* 'foo ' */
CPRINTS("'%+08x'", d); /* '000006d1' */
CPRINTS("'%+u'", d); /* '1745' */
Change-Id: I8dcd34b0cf03dbefc500b9c98fea235d85bde8d3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363924
Previously, tcpci_tcpm_set_vconn() would set bit0 and clear all others
of POWER_CTRL. With this patch, only bit0 is updated.
BRANCH=oak
BUG=chrome-os-partner:55221
TEST=plug/unplug apple dongle, check TCPCI 0x1c bit4 should be always 1
Change-Id: I83f113c13bdaad8ce6ece56241296a8f097e1f0a
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360771
Reviewed-by: Todd Broch <tbroch@chromium.org>
The cr50 code comes from four different repositories. This patch
introduces an array of the repositories where version information is
supposed to come from.
For all boards but cr50 this array includes just the local repository,
for cr50 the array is extended with the three other components.
This patch also allows to change the 'tree dirty' marker appended to
the sha1s of the 'dirty' trees, having a shorter marker helps to keep
multicomponent version strings shorter.
All external component's version information in the generated combined
version string is prepended by the component's root directory name.
BRANCH=ToT
BUG=chrome-os-partner:55373
TEST=ran the script for two EC boards, kevin and cr50, verified the
output:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ BOARD=kevin ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is clean, use the commit date of the last commit */
$
$ BOARD=cr50 ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is clean, use the commit date of the last commit */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
then introduced some local changes in the ec and tpm2 directories and
ran the script again. Note the '+' used as the 'dirty' marker in the
cr50 string:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
$ BOARD=kevin ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is dirty, using time of last compilation */
$
$ BOARD=cr50 ./util/getversion.sh
/* This file is generated by util/getversion.sh */
/* Version string for use by common/version.c */
/* Version string, truncated to 31 chars (+ terminating null = 32) */
/* Sub-fields for use in Makefile.rules and to form build info string
* in common/version.c. */
/* Repo is dirty, using time of last compilation */
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Change-Id: I4b4ec23ce003970c09442e8d8aeed2306d4e5dd8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363917
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
We need to ignore sys_rst_l right now when we use the usb spi endpoint
to update the AP or EC. We hold the EC and AP in reset and this causes
sys_rst_l to be asserted at the start of updating the AP and when the EC
comes out of reset.
Using the USB SPI endpoint may require doing a bunch of transactions
back to back. Cr50 should not reset itself between each one.
This change postpones the reset until we're done using the usb spi
endpoint. Once sys_rst_l just resets the TPM we can remove all of this.
BUG=chrome-os-partner:52366
BUG=chrome-os-partner:54982
BRANCH=none
TEST=manual
verify 'util/flash_ec --board=kevin --raiden' updates the EC
'sudo flashrom -p raiden_debug_spi:target=AP -w $IMG' updates
the AP
The AP and cr50 reset after usb_spi is disabled.
Change-Id: I68a76012bc7bf6d3abd073a70f0b90e440d72c49
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364051
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
It is necessary to collect information about more then one git
repositories status for the cr50 board. To facilitate this, separate
the code retrieving build version information into a function,
get_tree_version().
The function returns a two element string, the version information and
the 'dirty' marker in case the tree has any uncommitted changes. The
0x01 character is used to join the elements of the string, which makes
it easier to split the string when processing it.
BRANCH=ToT
BUG=chrome-os-partner:55373
TEST=ran the script before and after changes, observed that generated
output is identical.
Change-Id: I2c211cbda8c3cab3c8c21b4430e4b3102691e74a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362849
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
It is useful to be able to see which pins are set as wake pins and what
type they are. This change adds prints to show_pinmux to describe the
wake pins.
BUG=none
BRANCH=none
TEST='pinmux' should show DIOA12 as a wake_low source.
Change-Id: I2a0ccdbf9b07abb627c3d52c7dd28433a2beff3c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363494
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
We have the lid and base sensors correct in relation to each other.
e.g., when at 90 degree lid angle, this reports correctly:
# ectool motionsense lid_angle
Lid angle: 90
But it appears that our axes are opposite from (e.g.) what Chrome
expects. With the lid angle at 180 degrees flat on a desk, I see:
# ectool motionsense
Motion sensing inactive
Sensor 0: -571 1018 -16302
Sensor 1: 0 0 0
Sensor 2: 896 -3424 -16208
but the Z-axis should be positive. After this patch, I see:
# ectool motionsense
Motion sensing inactive
Sensor 0: 580 -1000 16289
Sensor 1: 0 0 0
Sensor 2: -832 16368 1008
Which looks more accurate, and actually gets Chrome to rotate properly.
All tested on kevin rev3.
BRANCH=none
BUG=chrome-os-partner:55717
TEST=`ectool motionsense`, `ectool motionsense lid_angle`; also test
rotation in Chrome
Change-Id: Ie1bffe27989c893d6037e251499f235ef10d4578
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364161
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The ancient native tests can't deal with board-specific
configurations, don't build them. We run generic changes with
host tests and board-specific cases by running on real hardware.
BUG=chrome-os-partner:55705
BRANCH=none
TEST=make BOARD=cr50 tests; make buildall; test on Cr50 hardware
Change-Id: I5eb7229ca9df16293d6f0f84b474d4c992277baf
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363942
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Cr50 was not waking up long enough after SPS_CS_L was asserted for the
spi slave transactions to start and disable sleep. It also was not
handling SYS_RST_L properly when it was asleep.
This change sets SPS_CS_L to be an edge triggered wake up source instead
of level triggered, because cr50 should just wake up on the edge and
disable sleep until the spi transaction is done.
It also adds sys_rst_l as a wakeup source. The sys_rst_asserted
interrupt cannot be triggered while cr50 is asleep, so the
pmu_wakeup_interrupt will call sys_rst_asserted if SYS_RST_L is low at
resume. This change relies on the EC extending the delay in
chipset_reset to be long enough for SYS_RST_L to still be asserted when
cr50 resumes.
BUG=chrome-os-partner:54331
BRANCH=none
TEST=manual
make sure suzyq is disconnected.
verify ap boots up to the kernel after running
'gpioset SYS_RST_L 0' then 'gpioset SYS_RST_L 1' on the ec
console.
Check that cr50 goes to sleep when the AP is not trying to use
the TPM.
When cr50 is asleep pwrbtn + refresh still resets the system.
Disable SYS_RST_L_IN as a wake source and verify the system
verification fails and requests a recovery image.
Change-Id: I807b1918842d96c9d2922aa33404d87ab28b9906
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363606
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Cr50 has sys_rst_l as a wake source, but it can't tell which pin woke it
on resume. To know the source it has to check the value of the pin on
resume. This change makes the delay long enough for Cr50 to resume and
check that sys_rst_is asserted.
BUG=chrome-os-partner:55674
BUG=b:30308276
BRANCH=none
TEST=enable sleep on cr50 and verify apreset still reset it
Change-Id: I8e088c5f13a4222142161d8b79550dfc6eb529d6
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364170
Reviewed-by: Shawn N <shawnn@chromium.org>
The case close debug (CCD) feature is provided by the external security
chip. We add CONFIG_CASE_CLOSED_DEBUG_EXTERNAL to be able to detect debug
accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without
seeing Rp).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:55410
TEST=manual:on Kevin, plug a SuzyQ (with Rd/Rd) either in S5 or
transition the device to S5 afterwards and see the debug USB endpoint
works.
Change-Id: Icef4209470463be77d43f4a46e32769ebf58f558
Reviewed-on: https://chromium-review.googlesource.com/363401
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the case close debug (CCD) feature is provided by an external chip
(e.g security chip or TCPC), we still need to be able to detect debug
accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without
seeing Rp).
Add a CONFIG_CASE_CLOSED_DEBUG_EXTERNAL configuration parameter for this
case.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:55410
TEST=manual:on Kevin, enable CONFIG_CASE_CLOSED_DEBUG_EXTERNAL,
plug a SuzyQ (with Rd/Rd) and verify that the device in debug mode
when transitioning to S5.
Change-Id: Ie04a000a7b0eb670e3808f7bca1180298dfcd9db
Reviewed-on: https://chromium-review.googlesource.com/363400
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
