As a temp measure until a proper solution is implemented, reset the
restart counter when the PCR_Read command is issued by the host.
This is a good indication that Chrome OS is through the boot process,
as PCR value is used to determine the boot mode.
BRANCH=none
BUG=chrome-os-partner:55667
TEST=installed the new image on a Kevin cr50 and rebooted it in normal
and recovery modes, observed on the cr50 console the message like
> system_process_retry_counter:retry counter 1
Change-Id: Ib55e161d5edbf8f6e2d387fd756b94aa53c20ed8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/364311
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
'+' flag can be used with signed integer type (%d) and causes positive
integers to be prefixed with '+' (e.g. +1745). This emphasizes output
values as a signed value. It can be mixed with left-justification flag
'-': %-+8d. It's ignored when used with unsigned integer or non-integer
types: %u, %x, %p, %s, %c, etc.
BUG=none
BRANCH=none
TEST=make buildall &&
int32_t d = 1745;
CPRINTS("'%-+8d'", -d); /* '-1745 ' */
CPRINTS("'%-+8d'", d); /* '+1745 ' */
CPRINTS("'%d'", d); /* '1745' */
CPRINTS("'%+08d'", -d); /* '000-1745' */
CPRINTS("'%+08d'", d); /* '000+1745' */
CPRINTS("'%+d'", -d); /* '-1745' */
CPRINTS("'%+d'", d); /* '+1745' */
CPRINTS("'%+s'", "foo"); /* 'foo' */
CPRINTS("'%-+8s'", "foo"); /* 'foo ' */
CPRINTS("'%+08x'", d); /* '000006d1' */
CPRINTS("'%+u'", d); /* '1745' */
Change-Id: I8dcd34b0cf03dbefc500b9c98fea235d85bde8d3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363924
When the case close debug (CCD) feature is provided by an external chip
(e.g security chip or TCPC), we still need to be able to detect debug
accessory with Rd/Rd (by setting Rp/Rp when VBUS is detected without
seeing Rp).
Add a CONFIG_CASE_CLOSED_DEBUG_EXTERNAL configuration parameter for this
case.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:55410
TEST=manual:on Kevin, enable CONFIG_CASE_CLOSED_DEBUG_EXTERNAL,
plug a SuzyQ (with Rd/Rd) and verify that the device in debug mode
when transitioning to S5.
Change-Id: Ie04a000a7b0eb670e3808f7bca1180298dfcd9db
Reviewed-on: https://chromium-review.googlesource.com/363400
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The SoC looks for two RO images at reset, and is typically
configured for two RW images as well. This CL reports version
strings for all those images, as well as identifying the active
RO and RW copies.
Since the RO image doesn't contain a version string, we create
one using the epoch_, major_, minor_, and img_chk_ members of its
signed header.
BUG=chrome-os-partner:55558
BRANCH=none
TEST=make buildall; run on Cr50 hardware
The "version" command now includes information like this:
RO_A: * 0.0.2/a3c3d5ea
RO_B: 0.0.2/8895c9eb
RW_A: cr50_v1.1.4965-a6c1c73-dirty
RW_B: * cr50_v1.1.4959-2f49d5c
The '*' indicates the active image.
The test/tpm_test/tpmtest.py program has been updated to request
the version information at startup, and it also now reports
similar information, just all on one line:
RO_A:* 0.0.2/a3c3d5ea RO_B: 0.0.2/8895c9eb RW_A: cr50_v1.1 ...
The active images are marked with a '*' following the ':', so
that the same regexp can match either format:
($ro, $rw) = m/RO_[AB]:\s*\*\s+(\S+).*RW_[AB]:\s*\*\s+(\S+)/s;
Change-Id: Ic27e295d9122045b2ec5a638933924b65ecc8e43
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362861
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This change implements logic for installing
endorsement certificates in the RW section.
The endorsement certificates are initially
provisioned in a fixed RO flash region and
are copied in the RW TPM data region (once
this region has been initialized).
Also add code for reading from the info bank,
which is where the endorsement seed is
initially stored.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=TCG tests running
Change-Id: Id8c16d399202eee4ac0c4e397bdd29641ff9d2f3
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/362402
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
The clock() function was introduced to provide free running clock for
the TPM2 library, which expects this clock to run with a millisecond
resolution.
This patch fixes the bug where the function in fact was returning the
clock running at a microsecond resolution.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
BUG=chrome-os-partner:50115
TEST=with the appropriate modification of the user of this function
all lockout related TCG tests pass.
Signed-off-by: nagendra modadugu <ngm@google.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/361180
(cherry picked from commit b4e78b309900402499b8742199fb4536570d3000)
(cherry picked from commit fefaa02a4f2c807a3ad50137bd7dba7f5f081c31)
Change-Id: Ic02fffca610426d22e58609eb8c3693aec96ad5c
Reviewed-on: https://chromium-review.googlesource.com/362118
For now the presence of both RSA and EC certificates at fixed NVRAM
indices is considered evidence of TPM being through manufacturing.
BRANCH=none
BUG=chrome-os-partner:50645
TEST=with the rest of the patches applied TPM manufacturing status is
properly detected at startup.
Change-Id: Iff3861603272cdfb58ebc523458c114685b2429f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362351
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This copies the generic USB update code into common
so it can be used on other platforms. There should be
no functional change. cr50 folks want no change to their
code so vbendeb@chomium.org will refactor this back
together at a later date.
BUG=chromium:571476
TEST=none
BRANCH=none
Change-Id: I710afb22940013e7db5d8694898b90c0ae245777
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/362131
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This allows us to specify the polarity of the alert signal for
each TCPC chip onboard, even if we have multiple instances of
the same chip.
BUG=none
BRANCH=none
TEST=built and booted on reef
Change-Id: I06a58c4e26892843243e8e98f2c86c6d3a696eb1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360948
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently, the matrix keyboard protocol does not have support for
handling non-matrixed keys. This commit adds support for buttons which
do not appear in the keyboard matrix as well as switches.
Additionally, the keyboard FIFO is now just a general MKBP events FIFO
which MKBP events are free to use. Now, buttons and switches wil join
the key matrix event.
BUG=chrome-os-partner:54988
BUG=chrome-os-partner:54976
BUG=chromium:626863
BRANCH=None
TEST=Flash kevin, and verify that keyboard is still functional.
TEST=make -j buildall
CQ-DEPEND=CL:358926
Change-Id: If4ada904cbd5d77823a0710d4671484b198c9d91
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/358633
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When the debug cable is disconnected the a USB suspend interrupt is
triggered and puts the chip to sleep before rdd can detect a change on
the cc lines and disconnect from CCD. This prevents the DEBUG_STATE_MAP
from being reset to detect the debug connect and is left detecting the
disconnect. Since the debug accessory is already disconnected the RDD
interrupt will wake up the chip right after it goes to sleep.
The UTMI and PIN wake source still cause the chip to wake up before the
RDD interrupt, so disable those to test this change.
BUG=chrome-os-partner:54796
BRANCH=none
TEST=Disable wake pin and utmi wake sources. Put cr50 to sleep. Attach a
reworked suzy q and make sure cr50 wakes up. Detach it and check that it
goes back to sleep. Do that a couple of times. Check CCD is still
enabled when the debug accessory is detected and disabled on
disconnect.
Change-Id: I58a012895bc874dcdd512aa84de9a917469f3139
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/360234
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added code to get the VBUS level by reading the charger registers.
BUG=chrome-os-partner:55117
BRANCH=none
TEST=Manually tested on Amenia, VBUS_VAL (5Ch) & VCC_VAL (5Eh)
registers are updated with the correct VBUS value on the
respective ports.
Change-Id: I3b019b2d87e4c347f12596df387a2a659092ae25
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/359416
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When cr50 is not trying to do ccd, we dont need to monitor the devices.
Disable device state detection interrupts and the AP and EC UARTs.
BUG=none
BRANCH=none
TEST=gru and kevin monitor devices correctly when ccd is enabled, and
dont monitor anything when it is disabled.
Change-Id: Ic3f5974320486ff6dd0147c490a1c294cc2f6a76
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356770
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
cts.tasklist contains tasks run only for CTS. These tasks are added to the
tasks registered in ec.tasklist with higher priority. This design allows
board directories to be free from CTS stuff.
cts.tasklist can be placed in each suite directory (cts/suite/cts.tasklist).
If a suite does not define its own cts.tasklist, the common list is used
(i.e. cts/cts.tasklist).
BUG=chromium:624520
BRANCH=none
TEST=Ran the followings:
make buildall
make CTS_MODULE=gpio BOARD=nucleo-f072rb
make CTS_MODULE=gpio BOARD=stm32l476g-eval
Change-Id: Ibb242297ee10a397a8fcb6ff73d8cbc560daa885
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359445
Reviewed-by: Chris Chen <twothreecc@google.com>
The first time you use this with a particular th,
connect only th and run ./cts.py --th
Then connect both boards and you can run
./cts.py to build/flash both boards.
BRANCH=None
BUG=None
TEST=manual
- Enter chroot
- Navigate to ec/cts
- Connect only th
- 'sudo ./cts.py --th'
- './cts.py -b'
- Exit chroot
- Connect both boards
- './cts.py -f'
Each board should flash successfully
Change-Id: Ib14fccabcd9fdad04f9b92817da597bc0dcb3d89
Reviewed-on: https://chromium-review.googlesource.com/358100
Commit-Ready: Chris Chen <twothreecc@google.com>
Tested-by: Chris Chen <twothreecc@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
If the EC has CONFIG_HOSTCMD_RTC set to 'y', then export this via the
features host command. The kernel can then use this feature to expose
an RTC device under /dev/rtc*.
Signed-off-by: Stephen Barber <smbarber@chromium.org>
BRANCH=none
BUG=chrome-os-partner:54639
TEST=`ectool inventory` shows RTC on kevin
Change-Id: I644c8e61c4d9f691cc6ca94ef60bee4384c21660
Reviewed-on: https://chromium-review.googlesource.com/359414
Commit-Ready: Stephen Barber <smbarber@chromium.org>
Tested-by: Stephen Barber <smbarber@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
elm EC console output is very spammy, as EC_CMD_MOTION_SENSE_CMD
is called every 100ms, so we want to set "hcdebug" to "off" as
the default (which still includes errors, but no "normal"
commands).
BRANCH=none
BUG=chrome-os-partner:55001
TEST=make buildall -j
TEST=Flash elm EC, see that output is fairly quiet.
Change-Id: I70d91c291d934b4f032e5c57f3c333e2c10b93bc
Reviewed-on: https://chromium-review.googlesource.com/359112
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Currently, it is assumed the host will sooner or later retrieve the
events from the sensor ring: It is only used by Android and the sensor
HAL is enabling the ring buffer at boot.
But if nobody processes the ring, and the ring is almost full, the EC will
generate interrupt for every new events.
This can happen with ARC, where events generated for ChromeOS
will be in the ring but nobody will process them until Android is
started.
Add a command to allow sending ring MKBP events. It will be used when
the IIO ring buffer is enabled / disabled.
It also can be used for preventing raising interrupt when the device is
about to go to sleep.
BRANCH=ryu,cyan
BUG=b:25425420,b:27849483
TEST=Check with fiforead that no events are queued when IIO ring
buffer is disabled.
Check with ectool and androsensor that interrupt generation stops.
Change-Id: Ibc85eed2e0eae3a9ec07d191e692118bc2fd0dab
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356689
For certain board configurations, KSI2 will be stuck asserted for all
scan columns if the power button is held. We must be aware of this case
in order to correctly handle recovery mode key combinations.
BUG=chrome-os-partner:54602
BRANCH=None
TEST=Manual on gru. Do three-key salute, verify EC detects recovery mode.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I03d76e1121107484f79520745858388f6cae096c
Reviewed-on: https://chromium-review.googlesource.com/357590
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Changes were submitted for ec_commands.h but only in the braswell tree.
Merge in ToT for future reference.
BRANCH=none
BUG=chrome-os-partner:50627
TEST=compile.
Change-Id: I74f6ce3c5fd2a628879593a65506d10c44ee574d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356551
Not everything with a temperature sensor uses thermal throttling. This
change modifies the conditional build to enable building temp sensor
source without thermal throttling.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356484
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added console commands for the debugging purpose
psys - Can be used to measure the system power
amonbmon - Can be used to measure AMON/BMON voltage diff, current
BUG=chrome-os-partner:54273
BRANCH=none
TEST=Manually tested on Amenia
psys - Ran fish task and observed psys value changes.
amonbmon - AMON & BMON voltage & current are same as measured
across sense resistors.
Change-Id: I6653e814d9b00efe7dae9ce1fbd7ddbc2356f8e0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/353043
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
For designs where the host SOC is responsible for setting the USB-C SS
mux, the EC must track the desired mux state and inform the host when
the desired state changes. Then, the host must ask the EC for the new
desired state and set the mux accordingly.
BUG=chrome-os-partner:52639
BRANCH=None
TEST=Manual on gru with subsequent commit.
Attach USB dongle in port 1 and DP dongle in port 0, then verify `ectool
usbpdmuxinfo` output:
Port 0: DP
Port 1: USB
Flip DP dongle and verify output changes:
Port 0: DP INV
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6a99ce93a76c3197f9195cfaa25c5217d09aeb75
Reviewed-on: https://chromium-review.googlesource.com/355281
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a host event to support MKPB:
When sent, the ACPI code will send a notification to the kernel
cros-ec-lpcs driver that will issue EC_CMD_GET_NEXT_EVENT.
We can allow code (sensor stack for instance) that uses MKBP to work
on ACPI based architecture.
Obviously, host event over MKPB is not supported.
BRANCH=none
BUG=b:27849483
TEST=Check we get sensor events on Cyan through the sensor ring.
(cyan branch)
Change-Id: Iadc9c852b410cf69ef15bcbbb1b086c36687c687
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353634
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Previously our charger ISR called a deferred task which woke our charger
task. We can skip the deferred task and just wake our charger task
directly.
The other meaningful change here is to assume that we're using the
charger for VBUS detection / BC1.2 if we have a usb_chg task, which
holds true for all of our current boards with this charger.
BUG=None
TEST=Manual on kevin with subsequent commit. Verify charger connect /
disconnect detection works properly on both ports, with zinger, donette
and generic DCP charger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iad4f3ea90947b50859c549b591675e325717209f
Reviewed-on: https://chromium-review.googlesource.com/352822
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ANX7688 is a TCPCI compatible port controller with HDMI to DP converter.
The HDMI converter needs a reset every time after enabling its function.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=manual
boot elm proto
plug and unplug dingdong and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: I774421d7b0b8d2cfd31e860fcd4eaed08ee48ac7
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Reviewed-on: https://chromium-review.googlesource.com/340371
Commit-Ready: Koro Chen <koro.chen@mediatek.com>
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
There is only one charger IC and one interrupt PIN for both the ports
and also from the ISR it's not possible to decode from which port the
interrupt is triggered hence a deferred function is used to trigger
the wake event for the ports. As there is no additional benefit of
having an extra task, added code to use only one USB charger task for
both the ports.
BUG=chrome-os-partner:54272
BRANCH=none
TEST=Manually tested on Amenia. BC1.2 detection is success
and the battery can charge on both the ports (VBUS/VCC).
Change-Id: I2745a5a179662aaeef8d48c8c1763919e8853fd0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351752
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit includes changes required for
supporting a hardware based montgomery
modexp (r = a ^ e mod N).
The function bn_is_bit_set() was previously
static, and now added to internal.h, as this
function is used by the hardware implementation.
Add function declarations for new functions
related to the hardware implementation to
chip/g/dcrypto/internal.h
BRANCH=none
CQ-DEPEND=CL:*260618,CL:*260895
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I5fe4a6692678b64f27659f42a08d200b6fe6f0cc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/347462
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Added support to enable the BD99955 charger interrupt to detect
the VBUS activity. With this approach GPIO USB_Cx_VBUS_DET_N pin
can be removed.
BUG=chrome-os-partner:53688
BRANCH=none
TEST=Manually tested on Amenia. Type-C, DCP & SDP chargers can
negotiate to desired current & voltage. Battery can charge.
USB3.0 & USB2.0 sync devices are detected by the Kernel.
Change-Id: I5470092c5cd43026aafc1a638ba446d0037c71e7
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/343650
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commands makes it possible to control the PD chip (or
the interaction between EC and PD), from the AP.
- PD_SUSPEND: Suspends the PD chip: EC needs to stop talking
to PD chip. Useful at beginning of PD FW update.
- PD_RESUME: Resumes the PD chip: EC can start talking to PD
chip again. Useful at end of PD FW update.
- PD_RESET: Resets the PD chip (called at the end of the update).
- PD_CONTROL_DISABLE: Prevents further calls to this command
(for security reason, we do not want the AP to be able to
call the other subcommands after the update has been performed).
BRANCH=none
BUG=chrome-os-partner:52433
TEST=ectool pdcontrol {suspend,resume,reset,disable}
Change-Id: I7a955dd27b65086c21d195a6504aa7392eb0406d
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342584
Reviewed-by: Randall Spangler <rspangler@google.com>
add a new config flag to support active low power control signal
BUG=chrome-os-partner:53665
BRANCH=none
TEST=Use multimeter to check for voltage present on the WiFi slot.
Use gpioget to check GPIO state in S0 (on) and S5 (off).
Change-Id: Ibeca88d16f39eadd7f29589cd3cd15aeef0dd524
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347085
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Kevin uses inverted polarity (low = enable 5V output), so add a new CONFIG
to support this.
BUG=chrome-os-partner:53777
BRANCH=None
TEST=Manual on Kevin. Enable USB charger tasks, verify that VBUS is
properly detected on no-battery case.
Change-Id: Ifb3e5fa9db1973d9826435712711f0cb0fd1d3a5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349260
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
move PRECHARGE_TIMEOUT to config.h so that we can customize precharge time to
meet client's spec.
BUG=none
BRANCH=master
TEST=`make -j buildall`, precharge time is set to 300s in elm.
Change-Id: I5c3bf0d5c5240b9c087e6cdb7c6e97301efa9f84
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/348151
Reviewed-by: Shawn N <shawnn@chromium.org>
Port SHA and P256 code to depend on third_party/cryptoc.
Remove config options CONFIG_SHA1, and CONFIG_SHA256 as
these are provided by third_party/cryptoc.
Also remove unused config options CONFIG_SHA384, CONFIG_SHA512.
Crypto functions prefixed by dcrypto_ (declared in internal.h ),
DCRYPTO_ (declared in dcrypto.h) are implemented under
chip/g/dcrypto, and otherwise are implemented under third_party/cryptoc.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53782
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: If7da02849aba9703573559370af5fae721d594fc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340853
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
