This implements a basic battery LED policy:
- Charged: green
- Charging: yellow
- Error: red
- No charger: off
BUG=chrome-os-partner:17561
TEST=Manual
BRANCH=none
Change-Id: I7fa8242efa4d0382d8ef0cafe80f01d44c390397
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/42607
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This change introduces the following modifications:
When used outside chroot on Goobuntu the serial interface fails to initialize
if parity enable bit is set (for a reason not clearly understood). On top of
that the tcsetattr() return value of zero is not a guarantee of success. To be
sure that the settings came through one is supposed to read back the driver
config and compare it with the desired config.
To add insult to injury, gPrecise driver rejects attempts to enable parity.
Parity setting is not essential in many cases, this is why we check the actual
config and if the only missing setting is parity we print a warning message
and continue.
In case an operation fails, the exit value should reflect that (so
that the autotest suite using the utility could report failure).
Often when the programming attempt is undertaken soon after reset,
this utility gets overwhelmed with the console output generated by the
EC on resets. Consume the output before proceeding.
Instead of printing a long set of dots (one per written/read block),
print a spinning wheel instead.
BRANCH=None
BUG=chrome-os-partner:15610
TEST=manual
. used the utility to program Snow EC both inside and outside
chroot, it succeeded.
Observed the failing attempt to set parity when running outside
chroot.
Observed spinning characters instead of stream of dots.
Change-Id: Id25595d35a2a3ca578639cebd508f599e618787c
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/42310
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This makes it possible to define color constants so as to reduce code
size when called.
BUG=chrome-os-partner:17561
TEST=Build success.
BRANCH=none
Change-Id: I800b8d4b84749907b071febfea58d27fef7cc2b7
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/42617
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Allow to send commands to the smart battery using EC commands when the
battery is connected to an I2C bus behind the EC.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:14314
TEST=on Spring, with a kernel including patch to use the pass-through
for the sbs-battery driver, run "power-supply-info" and see the correct
information.
Change-Id: Ie10f1c95afe4a33cf0b55d5a0de7640d5971ebb3
Reviewed-on: https://gerrit.chromium.org/gerrit/41289
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Activate the pass-through for TPSchrome LDOs settings
and remove hard-coded values used for bring-up.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:14314
TEST=on Spring, with an updated bootloader, see the screen is still
coming up.
Change-Id: I7fe67640e66939b1a19074b54d81d64459a34f4a
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/41296
Reviewed-by: Vic Yang <victoryang@chromium.org>
Removed the check for modem device and now unconditionally
setting the GPU min frequency to 450.
BUG=chrome-os-partner:16439
TEST="cat /sys/kernel/debug/dri/0/i915_min_freq" and verify that it
returns 450 for systems with and without modem device.
BRANCH=none
Change-Id: I34d176e65420834a85a02755bad11124432ac33f
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/41564
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
BRANCH=link
BUG=chromium-os:37967
TEST=Remove write protect, reflash without 'unprotect', flag
and verify the write protect flag is stil enabled with
flashrom -p internal:bus=lpc --wp-status. Power down,
then reflash with the --unprotect flag. Now verify the
write protect status flag is disabled.
Change-Id: Ie05b5dc85dd31d29ab43a392fe948a52d547fff3
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/41477
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Allow to send commands to switch on/off the TPSchrome LDOs by using EC commands
when the TPSchrome chip is connected to an I2C bus behind the EC.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:14314
TEST=on Spring, with an updated bootloader, switch on screen FETs from
U-Boot instead of hardcoding them in the EC board code.
Change-Id: Ic6cebf04ba73a7c0ca2c54f532f8cf4c953ac0c1
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/41288
Reviewed-by: Vic Yang <victoryang@chromium.org>
To make test and bring-up easier, adds a host command for USB mux
switching.
BUG=chrome-os-partner:17111
TEST=manual
BRANCH=none
Change-Id: I9da43fe934881ce24f326275ef312c4e6a474f11
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/40586
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ADC pins should be configured as analog input pins. Also sets conversion
factor to obtain voltage values in mV.
BUG=chrome-os-partner:14319
TEST=Manual
BRANCH=none
Change-Id: I7e084052062c2b669f10da4309e99bf9e2954ded
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/40199
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds USB port control to charger task. For now, it only senses
attached device type and log it to console.
BUG=chrome-os-partner:14319
TEST=Attach/detach charger and see console output.
BRANCH=none
Change-Id: I1218d520c292d9d398c868122ae3876d3fc889bc
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/40078
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is a prepartory work for integrating USB port control into PMU
task.
Currently TPS65090 charger task is throttled to only waken by event once
per 500 ms. This in a way makes it hard to integrate other functionality
into this task. This CL moves the throttling mechanism to interrupt
handler so as to provide better control of when to throttle the
interrupt event.
BUG=chrome-os-partner:14319
TEST=Build success and boot on spring.
BRANCH=none
Change-Id: I72e63180442b379a379e1a87c10ef62395434872
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/40189
Reviewed-by: Rong Chang <rongchang@chromium.org>
This adds functions to control interrupt and get device type from
TSU6721.
Also expose initialization function so that we can initialize TSU6721
before we solve the initialization problem.
BUG=chrome-os-partner:14318
TEST=Build success.
BRANCH=none
Change-Id: Ia50f1c93309360d35902a707090694e94a3f7a74
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/40077
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We have yet another tweak for the lightbar, but we don't want to update the
EC. This CL adds an init script that runs on the AP at every boot and pokes
the EC to modify the lightbar settings. We have to run it at every boot
because the EC will hibernate after the AP has been off (not suspended) for
an hour on battery power and will lose its settings.
There's a corresponding CL for the ec-utils ebuild that installs the
userspace scripts into the rootfs.
BUG=chrome-os-partner:16827
BRANCH=link
TEST=manual
Build the image for Link, install, reboot.
Run "ectool lightbar params". The output should match what's in
/usr/share/ec/lightbar_params.txt
Change-Id: If50ac2ef2432f7d60cdaf4c222b68dbdee80b2ec
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39979
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Richard Barnette <jrbarnette@chromium.org>
The code to re-program the IR3570A core regulator on the fly is no
longer needed as the parts should be pre-programmed correctly and it is
slow.
This will break the EVT and older boards which have bad pre-programmed
settings.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=link
BUG=chrome-os-partner:15596
TEST=on Link, run the power_Resume test and observe the firmware resume
time has decreased.
Original-Change-Id: Id4f56a68d874879bf2f50047c21fbfabea16c850
Reviewed-on: https://gerrit.chromium.org/gerrit/36417
Reviewed-by: Puneet Kumar <puneetster@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 5c59877ee1878b8de380b662601592c817a8b0a8)
Change-Id: I40937c0379a1b94c24679ee5e3110c242849986a
Reviewed-on: https://gerrit.chromium.org/gerrit/39912
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Randall Spangler <rspangler@chromium.org>
To save power, we need the ability to switch ILIM pin back to GPIO when
we are not using PWM.
BUG=chrome-os-partner:14319
TEST=In console, test 'ilim on', 'ilim off', and 'ilim 50'.
BRANCH=none
Change-Id: Ib3e0400266ef94df25fca1c6e5f118eba37b3848
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39835
This adds init code to configure PWM and a console command to adjust
duty cycle.
Also rename ILIM_1500 to BOOST_EN.
BUG=chrome-os-partner:14319
TEST=Adjust PWM duty cycle and measure voltage.
BRANCH=none
Change-Id: I23856416da19ed523d46af39e6cbc3129ac25525
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39587
The host does a lot of ACPI keyboard backlight writes, which were
scrolling the debug console output. Change to using CR instead of LF,
so it's not so distracting.
(No code changes other than debug output)
BUG=none
BRANCH=none
TEST=Move laptop through different ambient light settings and look at
console output as keyboard backlight ramps up and down. The 'ACPI
kblight' messages shouldn't cause piles of scrolling.
Change-Id: Iafde57ffe6090830fa54d4920c48b198c36d8d85
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39914
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reads of HIBRTCC and HIBRTCCSS are not properly synchronized and may
return incorrect data. We were re-checking HIBRTC, but not HIBRTCSS.
BUG=chrome-os-partner:16864
BRANCH=link
TEST=from ec console, do 'rtc' command repeatedly;
printed values should be strictly increasing.
Change-Id: I3e59dc840316ad36bb4851f03b66a3ae3df5cccd
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39795
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
And tidy a few comments. No code changes, only comments and whitespace.
BUG=none
BRANCH=none
TEST=compile code (nothing to test)
Change-Id: I10faadc4f11147984cb911c4e630d05ac594cc56
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39796
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
for now, just control the USB pins muxing.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:14318
TEST=on Spring, put the EC UART on the micro-B connector and read it
using a modified FTDI cable.
Change-Id: Ib0c87e483fb0bbe1835bd6ea008176b88d6f12f8
Reviewed-on: https://gerrit.chromium.org/gerrit/38361
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Hardware clock uses two timers, currently TIM3 and TIM4. This CL adds an
option to select between TIM2, TIM3, and TIM4, so that we can use any
one the three timer as a PWM source.
BUG=chrome-os-partner:14319, chrome-os-partner:7463
TEST=Build and run on snow/spring. Build success on daisy.
BRANCH=none
Change-Id: I1a00b3d491ee3e131708b573f6ea70e6b56c96dd
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39584
This adds a '-debug' postfix to chip name when debug mode is enabled,
allowing us to probe debug mode from host.
BUG=chrome-os-partner:16700
TEST='mosys -k ec info' and see chip name postfixed with '-tm'
Test same thing on DVT and chip name is not postfixed.
BRANCH=link
Change-Id: Iade26f2009dd3bdb8ddbe92da0da8da5404c6e99
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39455
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If the entire flash is protected (as it normally is after software
sync), fail all flash write/erase operations.
Add a shadow copy of the all_now flag.
BUG=chrome-os-partner:16727
BRANCH=link
TEST=manual
Verify that flash operations work properly before all_now. Then enable HW WP
and
flashwp enable
flashwp now
and try
flasherase 0x38000 0x1000
flashwrite 0x38000 0x100
Those commands should fail with error 7
From the host side
ectool flasherase 0x38000 0x1000
echo 'Khaaaaaaaaaaan' > /tmp/b16727
ectool flashwrite 0x38000 /tmp/b16727
should also fail.
Change-Id: I99a4d2bb86080bd12c900582a8fbdfc79c99916c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39517
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This gives VDDC more time to bleed out before the system reboots.
This will require FAFT changes to compensate for the longer cold reset time.
BUG=chrome-os-partner:16600
BRANCH=link
TEST=from ec console, 'reboot cold' should take a second.
Change-Id: I7e0e901958593262868151642560296f0c5496a7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39515
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The hardware fix for issue 16600 adds RC delays to ENABLE_5VALW, so
that +5VALW stays on during a warm reset of the EC. In the worst
case, +5VALW will drop around 150ms, which could then move the +3VALW
glitch right into the time frame where the EC is booting following
hibernate.
Increase the cold reset hibernate time from 150ms to 200ms. This
ensures that +5VALW has dropped before the EC comes out of hibernate.
BUG=chrome-os-partner:16600
BRANCH=link
TEST=manual
From the EC console, 'reboot cold' a bunch of times. The system
shouldn't hang. (Alternately, you can 'ectool reboot_ec cold' a bunch
of times)
Change-Id: I4bebdb552b8e917c6345badd6efb68b10d7d1f86
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39340
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This works around a problem where disabling +5VALW glitches +3VALW_EC,
which may cause the EC to brown out or hang.
BUG=chrome-os-partner:16600
BRANCH=link
TEST=manual
1. When the system boots, look for this line as the first x86 power state:
[0.004977 x86 power state 0 = G3, in 0x0001]
2. Boot the system. Should boot normally.
3. Shut down the system using the power button.
4. After ~10 seconds, you should see that line of output again.
5. At the EC console: 'gpioget enable_5valw' should output:
1* ENABLE_5VALW
This should ideally be combined with a hardware fix to add 30+ ms of
delay to EC_EN_5V, since when the EC is reset via power+refresh that
tri-states EC_EN_5V, and it takes ~22ms for the EC to boot and start
driving EC_EN_5V again.
Change-Id: Iba4d961d064105faf988a35c2277e9d7406e39e2
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/39334
Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
When reading, the line must be sampled in a narrow timing window after
the output pulse. Interrupts or context switches during this time
corrupt the data.
Similarly, when writing, the difference between a 0-bit and a 1-bit is
the length of the output pulse. So a context switch or interrupt
there can turn a 1-bit into a 0-bit.
BUG=chrome-os-partner:15507
BRANCH=link
TEST=manual
0. plug in AC power
1. hold down shift key for the duration of this test
2. powerled yellow
3. powerled red
4. repeat steps 2-3 several times
5. release shift key
Power adapter LED should toggle color each time. (It may also toggle
to the normally expected color during this experiment, if the charging
task updates it.) Power adapter LED should NOT turn off during this test.
Change-Id: Ief11e6e9a5b07aa3a25c60c50e4e7744a4705713
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/38925
Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If interrupts are disabled and the deadline is across a 32-bit timer
boundary from the current time, udelay() can lock up. The fix is to
do 32-bit math directly in udelay().
BUG=chrome-os-partner:16472
BRANCH=link
TEST=manual
waitms 1 -> prompt returns almost instantly
waitms 500 -> prompt returns after 0.5 sec
waitms 1000 -> watchdog error printed, then prompt returns
waitms 2000 -> watchdog reboot
Change-Id: Ib8ca06cee414d48900c0142e629daa68aa0993c9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/38924
Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On systems with modems, a harmonic of the lowest GPU frequency
of 350Mhz interferes with the cellular signal. Set the minimum
GPU frequency for such systems to 450Mhz.
BUG=chrome-os-partner:16439
TEST="cat /sys/kernel/debug/dri/0/i915_min_freq". On systems without
this modem, it should read back 350. On systems with the modem, it
should read back 450.
BRANCH=none
Change-Id: I103a55af11955aed2f3e8c945904444475c63865
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/38826
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
This seems to happen when the I2C signals come up so that the EC sees
a start condition from the remote end. In this case, the EC refuses
to talk on the I2C port until the EC's I2C state machine is reset.
Also, don't fail on bus-busy, since that's true during a multi-part
transaction such as an I2C string read.
BUG=chrome-os-partner:16262
BRANCH=link
TEST=boot system; 'battery' and 'temps' should give good info
Then run snanda's suspend_stress_test for a while and repeat.
Or a better test is to open 2 crosh shells, sudo bash in each, and
1) while true; do ectool temps all; sleep 0.5; done
2) suspend_stress_test
Then watch the EC console for "I2C5 bad status" errors. These happen
rarely, only on some systems. With this fix, they'll be reported when
they occur, but should not cause errors to be reported by 'ectool
temps all', since the I2C module will clear the arbitration-lost
status before retrying.
Change-Id: Idfaf9cd7e8ef2abcc0130332890329dd5d2ca052
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/38686
Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
The behavior of GCC seems to have changed between 4.6 and 4.7,
now it might generate unaligned memory accesses, so we need to
explicitly set "-mno-unaligned-access".
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:16391
TEST=make BOARD=link dis, then check the generated assembly for
keyboard_scan_init
Change-Id: I326479a77d6319f1d74e17efe483f5cde56ff325
Reviewed-on: https://gerrit.chromium.org/gerrit/38758
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
1) Properly report I2C errors on TMP006 as error, not device-not-powered.
2) Treat clock timeout and bus-busy I2C status as error (previously ignored).
3) If clock timeout or bus-busy, reset I2C master for that bus to clear the
error.
These should help with systems where the thermal I2C bus gets into a
weird state on suspend/resume.
BUG=chrome-os-partner:16262
BRANCH=link
TEST=boot system; 'battery' and 'temps' should give good info
Then run snanda's suspend_stress_test for a while and repeat.
Change-Id: I534be8236a4d6de82575fe6d33a68502ce0a3a95
Original-Change-Id: Iec5d6bbd357d2e5eb3dc3d361c829f353e996ab6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/38444
Reviewed-on: https://gerrit.chromium.org/gerrit/38659
Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
Add an interface to allow the CPU to cap the maximum battery charging
current.
The maximum is removed every time the machine goes to S3 or S5.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=link
BUG=chrome-os-partner:16041
TEST=on Link, plug AC to charge the battery,
then run "ectool chargecurrentlimit 1200" and see
the charging current in "power-supply-info" decreasing to 1.2 A.
Change-Id: I10900e1c264d2db67809638ec0dcb836d721fa75
Reviewed-on: https://gerrit.chromium.org/gerrit/37532
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
When the system is in S5, it will go to hibernate mode after 1 hour
instead of 24 hours.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=link
BUG=none
TEST=on Link DVT3 with servo connected, turn off the machine and
see the EC going to hibernate after 1 hour (according to EC UART traces)
start the machine and see it boot properly.
Change-Id: I1da87b3e09b90817ce5609f3f74b5969235fb90a
Reviewed-on: https://gerrit.chromium.org/gerrit/37526
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
When a nonexisting file is specified as the EC image, the ec flash
programming script reports the error, but continues running and
returns zero status (success) after completion.
With this change the exit status on some errors gets communicated to
the caller.
The openocd script is edited to drop the unused parameter of the
flash_lm4() function and the flash_ec script is edited not to require
EC images to be executable.
BRANCH=none
BUG=chrome-os-partner:15610
TEST=manual
. run flash_ec with nonexisting or nonreadable file as a parameter,
observe it to report proper return status. Run it with a proper
image file name and observe it succeed.
. run the command again, while the device is being programmed enter
'ctl-c', observe programming stepped but the 'Restoring servo
settings..." message still showing up.
Change-Id: Iac0b233fe579b0d5a84cf5a9acf85ed8bf10422e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/37363
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add i8042 output port commands (0xf0-0xff), I8042_ENABLE_A20 and
I8042_DISABLE_A20.
BUG=chrome-os-partner:13119,
BRANCH=None
TEST=Tested on W7 installer. No KB error shown on EC console.
Change-Id: I9ad1fd7baa10683ef18ccf13faf09dc0cefcca0a
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/34994
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Add a few very basic tests and the required key matrix information.
The key matrix is for snow, and the tests are just enough to exercise
the feature.
BUG=chrome-os-partner:12179
BRANCH=none
TEST=manual for now:
On snow:
./ectool keyscan 10000 key_sequence.txt
See that the test passes.
Change-Id: Ibe5a6fe5333102ba7f37be4b526185a48b3c1ae8
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/35120
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a way of easily setting up keyscan tests using a simple text file
format. The steps to run a test are as follows:
- read the test file
- read the key matrix information
- translate the ascii characters from tests into keyscan codes
- send the keyscan codes to the EC
- tell the EC to start the test
- wait for the required time, then collect what input we have received
- check that the input matches the expected input
BUG=chrome-os-partner:12179
BRANCH=none
TEST=manual for now:
On snow:
./ectool keyscan 10000 key_sequence.txt
See that the test passes.
Change-Id: I7de646205803a99443503a1b4bbf32f5fe89c534
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/35119
Reviewed-by: Randall Spangler <rspangler@chromium.org>
They're not x86-specific, so move to the chipset interface.
BUG=chrome-os-partner:15579
BRANCH=none
TEST=x86reset warm, then x86reset cold. Should reboot OS in each case.
Change-Id: Ib571ab916bab16179198a0d054320e59afbae124
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/36785
This reduces memory / code size, and gets rid of ifdefs in temp_sensor.c.
BUG=chrome-os-partner:15714
BRANCH=none
TEST=boot system and run 'ectool temps all' every few seconds
- ectool temps all
The numbers should update over time.
Change-Id: Idaac7e6e4cbc1d6689f5d3b607c623a5cc536a4f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/36940
The time out value passed to task_wait_event() is signed 32-bit and
thus waiting for 24 hours will cause overflow. Limit max wait time.
BUG=chrome-os-partner:15797
BRANCH=link
TEST=Disconnect AC, shut down system, and close lid. From ec console,
do 'hibdelay 8000' and then wait 2.5 hours. EC should have
hibernated. (8000 is more than twice the max time for
task_wait_event())
Change-Id: I5fa505554182e8bad6399c12a382ff71bb123d8f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/37095
Reviewed-by: Vic Yang <victoryang@chromium.org>
This fixes the EC not being able to do a cold reset while the power
button is held down, because the power button asserts WAKE#.
BUG=chrome-os-partner:15705
BRANCH=link
TEST=manual
- scope HIB#
- hold down power button
- from console, 'reboot cold'
HIB# should stay asserted for 150ms. Before this fix, it asserted only briefly.
Change-Id: I07c6bb5ee3f846544c75e7e0d4584f8434a9cd56
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/37090
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Puneet Kumar <puneetster@chromium.org>
