We currently rely on *head == 0 as error condition, which is
fragile and inconsistent across TCPCs implementations.
Instead, let's return a proper return value on all implementations.
BRANCH=none
BUG=chrome-os-partner:60575
TEST=elm FW as of 65fb80d (later version include a fix that would
hide this issue), cherry-pick this patch, connect j5create
adapter, then HDMI, then power => no crash
Change-Id: If7235e0491e9f80fdd50ce2605477ee518f8e1aa
Reviewed-on: https://chromium-review.googlesource.com/417443
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
From TCPC spec:
"""
RECEIVE_BYTE_COUNT: Indicates number of bytes in this register
that are not stale. The TCPM should read the first RECEIVE_BYTE_COUNT
bytes in this register. This is the number of bytes in the
RX_BUFFER_DATA_OBJECTS plus three (for the RX_BUF_FRAME_TYPE and
RX_BUF_HEADER).
"""
We were always reading 3 bytes too many. This is an issue if we
receive a packet followed by a hard reset, as the register value
will be set back to 0, but TCPC_REG_RX_HDR may contain a valid
header, leading to corrupted packets being passed down the stack.
Also update usb_pd_tcpc to match the specification.
BRANCH=none
BUG=chrome-os-partner:60575
TEST=elm FW as of 65fb80d (later version include a fix that would
hide this issue), cherry-pick this patch, connect j5create
adapter, then HDMI, then power => no crash
Change-Id: I9ed8f3b500d5733ec7563e31246505e0b8bd48bb
Reviewed-on: https://chromium-review.googlesource.com/417442
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Charger Operation Control Setting 1 (CHGOP_SET1) has separate bits to
disable input current limitation for DCP, SDP, others. If it is not
disabled, input current is automatically selected, which results in
hard resets on weak chargers hence disable the input current
limitation for all types of chargers.
BUG=chrome-os-partner:60722
BRANCH=none
TEST=Tested on Reef. Input current is not automatically set to all
types of chargers.
Change-Id: Ideb16ac2a40b403c94c28e85f254043ead7415e0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/417234
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
After sending a hard reset through Control3 SEND_HARD_RESET, packet Tx
will fail until PD_RESET is triggered. Therefore, always do such a reset
when we see an M_HARDSENT interrupt. Previously, it may have been possible
to skip our reset depending on prior Tx packet status, leaving the TCPC
in a wedged state.
BUG=chrome-os-partner:58232
TEST=Manual on kevin, spam 'pd 0 hard' for 10 hours with zinger attached,
verify TCPC is still responsive and negotiating to 20V.
BRANCH=gru.
Change-Id: I42db792a5f51218c58235dc38c2d49795b54986e
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/393769
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 811534541c263244d2fe9bdf9465de196e1575da)
Reviewed-on: https://chromium-review.googlesource.com/415486
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the battery is fully charged or not charging, upon removal of
the AC, discharge takes long time. To overcome this issue suspend
the DC-DC converter when discharging on AC.
BUG=chrome-os-partner:58969
BRANCH=none
TEST=Manually tested on reef. Discharge is in the permissible range.
'chgstate' console command prints correct values.
Change-Id: I64afa992e50b6e18daf43edf237fde8cf658a8a2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/413153
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Rereading the specification, remove delays when not needed:
- When we move the sensor out of suspend, we need to wait before
using it (BMI160 spec: 2.11.38 Register (0x7E) CMD)
When we do a softreset, we need just need to wait 300us for the
sensor to go in suspend, we will wait only when we change the rate
and enable the sensor.
- The timeout at fifo flush is not needed, it was added for debugging.
- Remove unnecessary printf when initializing the magnetometer.
BUG=chrome-os-partner:59188
BRANCH=glados, reef, strago
TEST=On reef, check the EC boot faster: time spend initializing the
sensors
decreased from 240ms to 133ms
Change-Id: Ia80232da42aa705df819a4988da483a344ffcbb4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/411964
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Charger BGATE is off on POR hence the voltage to the battery pack is
not applied immediately from the VBUS. To overcome this issue, BGATE
is turned on (CHG_EN) at charger initialization. If the voltage across
VBATT is high but I2C is still failing, battery is booting from ship
mode hence overwrite the battery as not present till I2C on battery
is success and INIT bit is set.
BUG=chrome-os-partner:59308
BRANCH=none
TEST=Reef can boot to OS from shipmode battery.
Change-Id: If1b212612e27fd65a822675a9609f0a8c03d8add
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/411360
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This add basics for acc and gyro sensor ST lsm6dsm
Still need to add interrupt management for embedded
functions and FIFO
BUG=none
BRANCH=master
TEST=Tested on discovery BOARD with sensor connected on
EC i2c master bus. Added motion sense task on discovery
board task list, added gpio info in board configuration
file and tested with motion sense console commands. Data
for acc/gyro seems ok, can successfully change ODR and
full scale range for acc and gyro.
Change-Id: Ie50c8c0ee366994ed97f7ff3252633893b813ac2
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/406947
Commit-Ready: mario tesi <mario.tesi@st.com>
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Added battery charging profile settings as given in the datasheet.
BUG=chrome-os-partner:58553
BRANCH=none
TEST=Manually verified on reef. VBAT is equal to battery voltage.
Previous/current Charge status is equal to the conditions given
in the datasheet.
Change-Id: Ie04619a122fe52d6768c03ff5156b368e3f2d340
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/398080
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890
BRANCH=none
TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption
Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/399882
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When attaching a dump (not PD protocol) TypeC charger, the incorrect
charger type was being selected and therefore it was not enabling 3A
charging. I tracked this issue down to the anx74xx_tcpm_get_cc()
function returning a incorrect value. The expected value was
TYPEC_CC_VOLT_SNK_3_0, but instead it was returning
TYPEC_CC_VOLT_SNK_DEF.
The reason the incorrect cc type was being returned is because the if,
else if, construct didn't work properly for the 3A case where the
upper 2 bits are set. Modified this routine to use a case statement
and consolidated the checks for both cc1 and cc2 into one helper
function.
BRANCH=none
BUG=chrome-os-partner:58738
TEST=manual
Connected zinger and guppy chargers and verified correct cc type was
being returned. In addition tested hoho/dingdong adapters as well as
suzyq. Tested both cable orientations to verify that cc1 and cc2
returned the correct values.
With guppy connected, now see this output on ec console:
C0 HARD RST TX
C0 st5
C0 st36
C0 st37
C0 HARD RST TX
C0 st5
[1921.980074 AC on]
[1922.008140 charge_request(8688mV, 9280mA)]
C0 st6
[1922.910539 Ramp p0 st5 3000mA 3000mA]
Change-Id: I8b31c7ce366f383dfcc2f6e850b76a83340a02a1
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/406642
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54668
BRANCH=none
TEST=Verified SNK is detected in S0 (toggle on), S3 (toggle off),
and S5 (force sink). SRC is detect in S0 only, stays detected when
entered S3, but unplug/plug while in S3 will not re-detect until
system back in S0. When go to S5, SRC will get disconnected until
back in S0, and hotplug SRC in S5 will not get detected. Checked
power role swap with another chromebook in the above scenario also.
Change-Id: I2a487fca5cb04c45524aa3efde84fcd10ff0579e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/396918
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Take into account the rotation matrix to do calibration.
In particular the Z axis: if board is upside down, we need to use
MINUS_1G instead of PLUS_1G when setting online calibration.
BRANCH=kevin
BUG=none
TEST=Before, calibration would not work on the Z axis.
Change-Id: Ifaec331aac40a4be0e34fcab5dd3752d2d59b91f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/405854
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The 'else' was missing in the for the check of
port == BD9995X_CHARGE_PORT_BOTH. So if it wasn't this port type then
it would always hit the panic.
BUG=chrome-os-partner:59189
BRANCH=none
TEST=Manual
Verfied the failure case using a type C to type A adapter. After
applying the fix verified that it no longer panics.
Change-Id: Ia5a16c39e226d5e648c20d0c8675d6433d083f22
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/405747
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The check for hard reset complete was missing. Because of this, the
USB PD protocol state machine would get stuck in state 36
PD_STATE_HARD_RESET_SEND waiting for the pd_task to be woken following
the tx_complete. Instead it would always trip the 100 msec timeout.
BRANCH=none
BUG=chrome-os-partner:58738
TEST=manual
Without this CL, connect to a Guppy TypeC charger and observe:
> C0 st3
[101.946607 event set 0x00200000]
C0 st15
C0 st3
C0 st6
C0 st36
[102.466846 New chg p0]
[102.470376 Ramp reset: st1]
[102.470905 CL: p0 s2 i2000 v5000]
[103.543623 AC on]
After adding the fix for checking hard reset done:
> C0 st3
[32.880946 event set 0x00200000]
C0 st15
C0 st3
C0 st6
C0 st36
[33.410038 New chg p0]
C0 st37
[33.415641 Ramp reset: st1]
[33.416160 CL: p0 s2 i2000 v5000]
C0 HARD RST TX
C0 st5
C0 st36
C0 st37
C0 HARD RST TX
C0 st5
[34.489611 AC on]
[34.489965 event set 0x00000008]
[34.520457 event set 0x00400000]
[34.520876 charge_request(8688mV, 4608mA)]
C0 st6
[35.419391 Ramp p0 st2 500mA 0mA]
Change-Id: I6822983002fa387c85f7e55af5fe1e142c7b88e2
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404878
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Turn off the charger BGATE when the system is hibernated to
save maximum power.
BUG=chrome-os-partner:59001
BRANCH=none
TEST=Manually verified on the Reef.
System can boot from hibernate wake sources.
Following are the power measurement values at Battery
voltage = 8.3V & temperature = 23 deg C.
a. Normal operation 540uA, 3.500mW
b. BGATE OFF 80uA, 0.592mW
Change-Id: Ia30655ccefbf0dded623246150d53b2a815df2de
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/404685
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
POR has both VCC & VBUS enabled. If the port is sourcing VBUS it will
also act as sync and AC_OK pin gets enabled. Hence disable the input
to the port when sourcing.
BUG=chrome-os-partner:59020
BRANCH=none
TEST=Manually verified on Reef. Connected HoHo and AC_OK is not
enabled.
Change-Id: Ic51b81f45759d7dddb2c9744d1c24dbafd1e1293
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/404168
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Existing get_cc function depends on set_cc function which marks a
"pull" variable to indicate if anx74xx is setting Rp or Rd. However,
if DRP auto toggle is used, this "pull" variable is unknown, but
CC_STATUS register can differentiate between SRC and SNK, so this
"pull" variable is actually not needed.
BUG=none
BRANCH=none
TEST=verify Type-C functionality did not change on Reef.
Change-Id: I6cab8d7fcee20ec6e8414b6b2591c5d975d85293
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/396428
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
From the specs, "KX022-1020 Specifications Rev4.0", the power up time
can be as long as 10ms.
Add a loop to be sure the device is responsive before initalizing it.
BRANCH=reef,glados,oak,veyron,cyan
BUG=none
TEST=After putting a KX022 accel as first in the list, it would not
initialize properly. After adding the loop, it initializes properly.
Change-Id: I3194a5d1deb0c2eb2a04a459aab3b4269e479af3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394750
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
BMI160 driver assumes accel, gyro, compass are next to each other.
It was also assuming accel was sensor 0, which is wrong.
BUG=none
BRANCH=glados
TEST=On Cave, check sensors 1 (accel) and 2 (gyro) are working properly.
Change-Id: I37402e1d48070caaecbd7e32bbf53754616ee8cb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394067
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BMI INT2 can be input or output.
It is not used currently, but configure it properly nevertheless.
BUG=none
BRANCH=none
TEST=On cave, (int2 is output), ensure FIFO headers are free of
interrupt information.
Change-Id: I9c058689a8676593aad542e33601cc11da105838
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394066
We're using fusb302 rev. >= B now, so let's remove rev. A support.
BUG=chrome-os-partner:57492
BRANCH=none
TEST=Manuel
- plug USBC->DP cable into TV then into kevin
localhost ~ # ectool usbpdmuxinfo
Port 0: DP INV
- plug USBC->DP cable into kevin then into TV
localhost ~ # ectool usbpdmuxinfo
Port 0: DP INV
- unplug USBC->DP cable from TV
Port 0: OPEN INV
- plug USBC->ETHERNET into kevin and verified that network
displayed ethernet
Change-Id: Ia84dc2480c1a8b003ab8dfdcdaa9f82f6d429e4b
Reviewed-on: https://chromium-review.googlesource.com/388925
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If BD9995X_CMD_MAP_SET fails, the charger's internal map command set
may be the old set (if the charger failed to process the command) or the
new set (if the EC failed to receive the response). Therefore, reset the
EC's known map command state on failure, so that it will always be
re-set on the next transaction.
BUG=None
TEST=Build + boot kevin.
BRANCH=Kevin
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id16273ccf2e39b5aae7776d626aae8863e713df5
Reviewed-on: https://chromium-review.googlesource.com/390318
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
1.ANX3429 have CC Rx buffer, when the partner sent one message,ANX3429
received this message into Rx buffer and triggered an interrupt to
inform (TCPM), at this moment Reef sends a CC message before reading
CC Rx buffer. After Reef sends this CC message successfully, it receives
the message the partner sent. So (TCPM) sees an unexpected message was
received, that`s why sends out hard reset.
Root cause:
ANX3429 use a normal R/W register as a interrupt status register.
Between EC read interrupt status and clear interrupt status, if
ANX3429 change interrupt status, it causes interrupt status is
incorrect on EC side.
Solution:
ANX3429 FW use two normal R/W registers for interrupt status reg,
one is for FW interrupt status,other is for EC control register.
Note:
Since cc messages conflict between TCPM and the Partner,ANX3429
shall discard the TCPM message, (TCPM) sometimes send soft reset
depend on the discarded message type.
2. Sometimes TCPM (Reef) does not response GoodCRC for a received mesg.
Root Cause: Reef send message conflict with ANX3429 send auto GoodCRC.
Solution: This is fixed in the 1.5 ANX 3429 firmware.
BUG=chrome-os-partner:53936
BRANCH=none
TEST=On Reef tested with ANX3429 FW v1.5, did not see HARD RST on
ec log with Zinger.
Change-Id: I81da95433e7a0cc71e7ed121b925afccbcd84b06
Signed-off-by: Swang <swang@analogixsemi.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/381014
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added i2ctest console command to test the reliability of the I2C.
By reading/writing to the known registers this tests provides the
number of successful read and writes.
BUG=chrome-os-partner:57487
TEST=Enabled the i2ctest config on Reef and tested the
i2c read/writes.
BRANCH=none
Change-Id: I9e27ff96f2b85422933bc590d112a083990e2dfb
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/290427
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added unlocked versions of register access,
modified RMW functions to use unlocked versions
and made them locked themselves.
BRANCH=master
BUG=chrome-os-partner:49182
TEST=DUT boots successfully
Change-Id: Ifd16abc349cc731aeed78b12989595214e65cea2
Signed-off-by: Victor Prupis <vprupis@google.com>
Reviewed-on: https://chromium-review.googlesource.com/377151
Commit-Ready: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54332
BRANCH=none
TEST=verify only zinger is detected in sink mode (G3/S5), and both
zinger and hoho is detected in dual role mode (S0).
Change-Id: Ifce0009908acc4b1849723ce807ca1b4c8e26020
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/387260
Reviewed-by: Shawn N <shawnn@chromium.org>
Except the CHIP_ID and charger name code is common between BD99955
and BD99956. Hence renamed the code to BD9995X so that valid
output is printed from console commands.
BUG=chrome-os-partner:57519
BRANCH=none
TEST=Manually tested on Reef. 'charger' console command prints
charger name as 'bd99956'
Change-Id: I3c995757941bcc5a6a8026dd807d76a7a47c9911
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/387119
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
- Use 1200KHz DCDC clock.
- Set reverse current threshold to -50mV.
- Set internal gain to 2x.
BUG=chrome-os-partner:57118,chrome-os-partner:56255
TEST=Manual on kevin and reef, verify charging w/ zinger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ib7188764206743543fb873f303acb7b62977dc3d
Reviewed-on: https://chromium-review.googlesource.com/382451
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some chargers with valid VBUS advertise as Pull-up ports. Hence,
added code to support these kind of chargers as non-standard
BC1.2 chargers.
BUG=chrome-os-partner:57163
BRANCH=none
TEST=Manually tested on reef. Used a Pull-up port non-standard
BC1.2 charger and observed it can ramp to its maximum
current ratings.
Change-Id: I33c4c3a64e9c7176c909a48f6fbc49e04d529541
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/385239
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Rachel Nancollas <rachelsn@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The argument is mHz not ms.
BUG=chrome-os-partner:57117,b:27849483
BRANCH=reef
TEST=Using frequency sysfs parameter check the returned value is close
to the requested value. It will be greater than the requested frequency.
It maxes out at 76Hz when frequency is greater than 13.5Hz.
Check Androsensor reports pressure.
Change-Id: Ie40ac0f0a83d1578b5b66097d85a9124ec8e4c54
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385083
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When we source VBUS, the BD99955 does not disable its power saving mode
and messes up our USB2.0 data connection (DP/DN).
Let's disable the BD99955 power-save mode whenever a USB data connection
is present on one of the ports.
For configurations without power saving enabled, let's still write the
power-save mode register to ensure it is in the proper (disabled) state
whatever happened before (bad RW ...)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=gru
BUG=chrome-os-partner:57310
TEST=On Kevin, connect a USB-Ethernet dongle and see it enumerating
properly (while BD99955 power-save mode is enabled).
Change-Id: I379f94ecd294f045f353bd50eafd2035636837b1
Reviewed-on: https://chromium-review.googlesource.com/384851
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
