On EC reset where PMIC_EN will be pulled low,
PMIC could get into an unknown state and will
not sequence properly on sub-sequent boot.
This is a temporary workaround for Reef Proto,
a hardware change will be implemented on EVT.
BUG=chrome-os-partner:53974,chrome-os-partner:54507
BRANCH=none
TEST=Reef powers to S0 and starts coreboot after EC reset
Tested with servo cold reset button
and console reboot command
Change-Id: I32aa004b000895da2c97d1014a8ef48c0a98779d
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354762
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54503
BRANCH=none
TEST=Manually tested using console commands on both the ports.
a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is
1 when AC connected & 0 when AC disconnected.
b. Issued 'hibernate' & on plugging in the AC, device
boots to S0.
Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354721
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
following Change#227416 to meet client's spec.
BUG=chrome-os-partner:54263
BRANCH=master
TEST=`make -j BOARD=elm`, check factory force IDLE, works good
Change-Id: I1f0abdcbd56eeab379a6258869ccc133ff80736d
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/353521
Reviewed-by: Shawn N <shawnn@chromium.org>
BD99955 DCDC wiil turn off Vsys voltage under VSYSVAL_THL_SET
or VREF_BAT<VBAT if Charging Voltage set under actual battery
voltage or VSYSVAL_THL_SET.
BUG=chrome-os-partner:53777
BRANCH=none
TEST=boot-up without battery. using zinger or oem supplier
used kevin rev2, rev3
Change-Id: I03c5c52790b2d481be3fa942054516fbefa3ce98
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/348563
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54551
BRANCH=None
TEST=Manual on kevin. Verify negotiation to 20V when zinger is plugged.
Also verify "pd 0 dev 12" and "pd 0 dev 5" cause 12V/5V to be requested
from zinger.
Change-Id: I0298d535b791fa0c6f8ca077a6fd09a27e8ce77b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Implement the standard LED control scheme for gru, using a single PWM to
set the battery status LED color rather than the traditional GPIOs.
BUG=chrome-os-partner:54379
BRANCH=None
TEST=Manual on gru. Verify LED is green when charging w/ nearly full
battery, off when discharging w/ nearly full battery, amber when
charging otherwise.
Also verify LED control host commands work as expected:
ectool led battery green=1 // green
ectool led battery amber=1 // amber
ectool led battery red=1 // red
ectool led battery red=0 // off
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I184e72c552e6d2196aef2724af9292806e0ea8c0
Reviewed-on: https://chromium-review.googlesource.com/352520
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This makes the boot time less painful since it requires a long delay
for FW loading after power on this chip. This also makes it easier to
upgrade FW as we don't need to power on the chip before doing upgrade.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=plug and unplug dongle and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: Ia344c748697a3b1d06c9b442e1bf1d7227861f9b
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/347181
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ANX7688 is a TCPCI compatible port controller with HDMI to DP converter.
The HDMI converter needs a reset every time after enabling its function.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=manual
boot elm proto
plug and unplug dingdong and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: I774421d7b0b8d2cfd31e860fcd4eaed08ee48ac7
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Reviewed-on: https://chromium-review.googlesource.com/340371
Commit-Ready: Koro Chen <koro.chen@mediatek.com>
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Enable charger interrupt for VBUS / BC1.2 detection on kevin / gru.
Also, keep our USB data switches connected while we figure out how to
implement USB mux control.
BUG=None
TEST=Manual on kevin with subsequent commit. Verify charger connect /
disconnect detection works properly on both ports, with zinger, donette
and generic DCP charger.
BRANCH=None
Change-Id: I602e7bd3180110d351ec4c2916a6b8612c7e5f82
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352821
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shelley Chen <shchen@chromium.org>
This change implements distinct key derivation trees for
ECC and RSA key generation. The seed used for derivation
is HMAC(primary_seed, ALG), where ALG is either
"ECC", or "RSA".
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: Iee85731bdac02b7b1061e9220786bee52dbf6289
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351750
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
There is only one charger IC and one interrupt PIN for both the ports
and also from the ISR it's not possible to decode from which port the
interrupt is triggered hence a deferred function is used to trigger
the wake event for the ports. As there is no additional benefit of
having an extra task, added code to use only one USB charger task for
both the ports.
BUG=chrome-os-partner:54272
BRANCH=none
TEST=Manually tested on Amenia. BC1.2 detection is success
and the battery can charge on both the ports (VBUS/VCC).
Change-Id: I2745a5a179662aaeef8d48c8c1763919e8853fd0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351752
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Leave USB-A charging enabled in S3, and move gru-specific code into
board hooks, out of the power state driver.
BUG=chrome-os-partner:54159
BRANCH=None
TEST=Manual on gru. Verify USB-A enable GPIOs are asserted in S0 and
deasserted in G3.
Change-Id: Icadeb771226dd0fda4ae96fdde9b3984d87fdd15
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351670
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The motion sensors array as well as the config variables were copied
from another board and mostly wrong for Reef.
BUG=none
BRANCH=none
TEST=sensors which are connected successfully initialize, still need
to test lid sensors.
Change-Id: If8e1ec79803c7f378b21f4e9423a56bd6763eb4e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349733
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a certificate verifier, so that endorsement
certificates may be verified upon installation.
Doing so allows for catching certificate errors early.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I9339a6bc36e4d82ae875ce774e31848ae983fa1f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351031
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
LID_OPEN gpio is present on the daughter card and provided by the
EC. Add an internal pull-up on it for the cases when the daughter card
isn't plugged in.
This fix won't be required starting EVT.
BUG=chrome-os-partner:54143, chrome-os-partner:53566
BRANCH=None
TEST=Compiles successfully. "gpioget LID_OPEN" returns 1 without
daughter card.
Change-Id: Ieff281b489e4f3f8be184a55b7975fb2efcc1099
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/350460
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If our battery isn't able to provide enough power to the EC on boot, we
should not cut off our input power, regardless of dual role
determination or other charging policy.
BUG=chrome-os-partner:54058
BRANCH=None
TEST=Manual on gru. Drain battery completely, attach USB-C charger,
verify that "Battery critical, don't disable charging" is seen on the
console and the EC doesn't brown out.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I981f9dbf3d84390550bb696e561f5fa51ffc573a
Reviewed-on: https://chromium-review.googlesource.com/351224
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit includes changes required for
supporting a hardware based montgomery
modexp (r = a ^ e mod N).
The function bn_is_bit_set() was previously
static, and now added to internal.h, as this
function is used by the hardware implementation.
Add function declarations for new functions
related to the hardware implementation to
chip/g/dcrypto/internal.h
BRANCH=none
CQ-DEPEND=CL:*260618,CL:*260895
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I5fe4a6692678b64f27659f42a08d200b6fe6f0cc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/347462
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In no battery condition set the battery minimum voltage to the
battery maximum voltage so that the charger voltage is set to the
battery maximum voltage. This adds more reliability for the system
and also avoids system reboot due to voltage drop on VBATA.
BUG=chrome-os-partner:53968
BRANCH=none
TEST=If battery is not present, EC console command 'charger'
gives battery maximum value.
Change-Id: I1f7740977cbe7087c27de95036a0eb5c385c0a54
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348942
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Added support to enable the BD99955 charger interrupt to detect
the VBUS activity. With this approach GPIO USB_Cx_VBUS_DET_N pin
can be removed.
BUG=chrome-os-partner:53688
BRANCH=none
TEST=Manually tested on Amenia. Type-C, DCP & SDP chargers can
negotiate to desired current & voltage. Battery can charge.
USB3.0 & USB2.0 sync devices are detected by the Kernel.
Change-Id: I5470092c5cd43026aafc1a638ba446d0037c71e7
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/343650
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If a non-BC1.2 compliant charger is attached and if the USB charge
port detection is success then setting the charger supplier type as
CHARGE_SUPPLIER_OTHER.
BUG=none
BRANCH=none
TEST=Manually tested on Amenia. Used Apple USB charger (5.1V & 2.1A)
and few non-BC1.2 chargers (5V & 1A, 5V & 2.1A). Charger is
detected as CHARGE_SUPPLIER_OTHER and the battery can charge.
Change-Id: I35458dc173505cea970afc37d8f9ffb3c4376fe2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/348060
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This updates SMI/SCI-related config options on Reef so that
SMIs and SCIs are generated correctly.
BUG=chrome-os-partner:53726
BRANCH=none
TEST=built and booted on Reef EC, firmware seemed more stable
(stayed up longer), but still see watchdog timesouts in task 13.
Change-Id: I6717f48a7655e49207fe34e6a166957eb34a05fd
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349711
Reviewed-by: Shawn N <shawnn@chromium.org>
The default mode for the LPC pins is actually LPC. Setting the
altnerate function mode makes them GPIOs.
BUG=none
BRANCH=none
TEST=build and booted on Reef EC. Didn't seem to make much of a
difference on its own but with the follow-up things seemed more
stable.
Change-Id: Ibbc62d23d8d909be48a9bec90da8acebb9905b50
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/347443
Reviewed-by: Shawn N <shawnn@chromium.org>
This change adds a ccd console command to control the usb endpoints.
The uart console command is moved into this command so 'ccd uart
[enable|disable]' controls the AP and EC TX signals instead of the
'uart' console command. CCD can be enabled using 'ccd enable'. This
switches the PHY used by the USB controller to be the external PHY.
Changing the PHY exposes the cr50, AP, and EC consoles as well as the
upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles
will be read only until 'ccd uart enable' is called. Cr50 can be updated
using the usb upgrade endpoint. The EC and AP can be updated using the
USB SPI endpoint.
When CCD is disabled the usb controller will switch to using the AP PHY.
None of the endpoints will be visible to the host.
The USB SPI endpoint can be used to flash the EC or AP using
'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled
running flashrom using the raiden_debug_spi programmer will fail. Cr50
will not forward the commands to the external AP or EC ROM, so flashrom
will not be able to find the chip.
The UART TX signals are now controlled by the 'ccd uart' console
command instead of the 'uart' console command. The UART TX is enabled
separately from CCD, because we want to be able to enable CCD while
servo is connected, and having the cr50 UART TX pins wired directly to
the Servo TX lines could damage both devices. The AP and EC consoles
are be read only until 'ccd uart enable' is called. 'ccd uart disable'
disconnects the AP and EC TX pins from the UART peripheral.
When RDD becomes reliable on cr50, ccd_set_mode will select the PHY
being used by the g chip USB controller.
BUG=chrome-os-partner:49960,chrome-os-partner:52281
BRANCH=none
TEST=manual
TEST SERVO
power cycle the DUT
connect servo and check that the AP and EC consoles still work
check that both the AP and EC can be flashed using servo.
TEST SUZY Q
Attach Suzy Q
Connect to the all three consoles. Check that the cr50 console
is in read-write mode and the EC and AP consoles are read only.
Attach Servo.
Verify all of the servo functionality described above still
works with suzy q attached and ccd enabled.
Disconnect Servo.
run 'ccd uart enable' on the cr50 console and check both the AP
and EC consoles can be written to.
Check that the AP and EC can be programmed using the
raiden_debug_spi programmer.
Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342563
While in CCD, cr50 can be used to flash the AP and EC through USB. This
change adds an endpoint that can be used to read, erase, and write to
the AP and EC spi rom.
Currently CCD is not enabled on cr50, so usb_spi access has to be
enabled manually through the cr50 console.
BUG=chrome-os-partner:50701
BRANCH=none
TEST=manual
On EC console run 'flash_tristate true'
On cr50 console run 'usb_spi enable'
Use 'flashrom -p raiden_debug_spi:target=EC' and
'flashrom -p raiden_debug_spi:target=AP' to interact with
the AP and EC flash
CQ-DEPEND=CL:342144
Change-Id: I9c31dab252a8bfbc498eaf64ac5c2f53ec9dde30
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342511
Update power sequencing as per Rachel's recommendation. We currently
wait for PP5000_PG and PP3300_PG before enabling the PMIC. This changes
the order so that we don't wait for PP3300_PG before setting the PMIC
enable.
BUG=chrome-os-partner:51323
BRANCH=none
TEST=see scope shots mentioned in the BUG
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I022a9ab21c1bcb70dc72f358dbf89acb656851b8
Reviewed-on: https://chromium-review.googlesource.com/349291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
add a new config flag to support active low power control signal
BUG=chrome-os-partner:53665
BRANCH=none
TEST=Use multimeter to check for voltage present on the WiFi slot.
Use gpioget to check GPIO state in S0 (on) and S5 (off).
Change-Id: Ibeca88d16f39eadd7f29589cd3cd15aeef0dd524
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347085
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
move PRECHARGE_TIMEOUT to config.h so that we can customize precharge time to
meet client's spec.
BUG=none
BRANCH=master
TEST=`make -j buildall`, precharge time is set to 300s in elm.
Change-Id: I5c3bf0d5c5240b9c087e6cdb7c6e97301efa9f84
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/348151
Reviewed-by: Shawn N <shawnn@chromium.org>
Add tests for RSA-1024, and created partner CRBUG/53893
to track issue discovered with 1024-bit modinv.
1024-bit RSA support being added in preparation
for a forthcoming hardware based implementation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53893
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I6b5aaeffc9df1cbbe403535fd21cdd377b42c38e
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/348490
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Port SHA and P256 code to depend on third_party/cryptoc.
Remove config options CONFIG_SHA1, and CONFIG_SHA256 as
these are provided by third_party/cryptoc.
Also remove unused config options CONFIG_SHA384, CONFIG_SHA512.
Crypto functions prefixed by dcrypto_ (declared in internal.h ),
DCRYPTO_ (declared in dcrypto.h) are implemented under
chip/g/dcrypto, and otherwise are implemented under third_party/cryptoc.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524,chrome-os-partner:53782
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: If7da02849aba9703573559370af5fae721d594fc
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340853
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
GPIO_USB_C0_VBUS_WAKE_L is used to show VBUS status on elm.
If VBUS is present, pd sends soft reset on boot.
So it can boot without battery.
BUG=chrome-os-partner:53496
BRANCH=none
TEST=test on elm.
Remove battery and boot up successfully only with AC.
Use "sysjump rw" command and ec won't reboot by pd hard reset.
Change-Id: I1cdb12894c7b6bc41d7a16802b8c0ef14e2aa426
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/346261
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
It is important to be able to wipe out the non-volatile memory for
various reasons. This patch adds this ability for both when NV memory
is kept in SRAM and in flash.
Also a minor clean up to eliminate some code duplication and to have
normal flow messages printed out with time stamps.
BRANCH=none
BUG=chrome-os-partner:44745
TEST=just makeall at this time.
Change-Id: I59c1909669aeaa9e8ffb3d8ef81b02fa0facb6ab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348291
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change enables configs for:
CONFIG_USB_SERIALNO: a programmable serial number for servo_v4
CONFIG_CMD_GPIO_EXTENDED: ability to change GPIO functions on the command line.
BUG=chromium:571476
BRANCH=None
TEST=serialno set abcdef; serialno load; reboot; gpioget/gpioset
Change-Id: I0e871d256e41022d3bb9985e590864a6c4cdf6a4
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348391
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Initialize the charge suppliers after change manager is initialized,
otherwise charge supplier current & voltage values will be overwritten
to -1 by the charge manager ini function.
BUG=chrome-os-partner:53788
BRANCH=None
TEST=Observed there are no "CL: p(port) s(supplier) i-1 v-1" prints
on the EC console.
Change-Id: Id0212c502d5833c016ac79ee15d21304d6d7ceb2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/347896
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
