This updates the lockfile path for FHS 3.0 since powerd as well
as other pieces of software are migrating over.
BUG=chromium:616620
CQ-DEPEND=CL:351271
BRANCH=none
TEST=compiled
Change-Id: I6aa5fa30225e45039316e4a3af0e50cdef0fdf4e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351345
Reviewed-by: Dan Erat <derat@chromium.org>
Created a new TPM register define at the beginning of the
vendor defined configuration register space 0xF90 - 0xFFF.
Note that this same space is defined for each locality.
In order to retrieve the FW version string, the TPM register
at offset 0xF90 needs to be written. This will initialize
a the pointer index to 0. The same register is then
read by the AP and each read will return up to 4 bytes of the
FW version string. Once Cr50 detects the string termination
character, it stops incrementing the index so that 0s continue
to be returned for each subsequent read.
In addition there is a max value of reads for the case when the
version string is corrupt and doesn't have a '\0' character.
BRANCH=none
BUG=chrome-os-partner:54723
TEST=Manual
Added a routine in /coreboot/src/drivers/spi/tpm.c tpm_init()
that does the write/read sequence described above. This test
routine produced the folloiwng AP console output:
Reading TPM EC Version!!
scollyer@ code goes here
Read 1: cr50 0x30
Read 2: _v1. 0x2e
Read 3: 1.47 0x37
Read 4: 81-1 0x31
Read 5: 3619 0x39
Read 6: 95-d 0x64
Read 7: irty 0x79
Read 7: 0x0
Cr50 FW Version: cr50_v1.1.4781-1361995-dirty
Read Count = 29
Initialized TPM device CR50 revision 0
Change-Id: I5d68a037f7a508e3109c35e841dbcb3a893ce22f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355701
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The "PC Client Protection Profile for TPM 2.0" document defines SPI
bus addresses for different localities. That definition is not honored
in the cr50 implementation, this patch fixes it: locality zero
register file is based off 0xd40000.
BRANCH=none
BUG=chrome-os-partner:54720
TEST=verified that upstream Linux driver is happy now
Change-Id: Ibc01035a5dcc823a0ec82374d758de08a70083b6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/355610
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
On EC reset where PMIC_EN will be pulled low,
PMIC could get into an unknown state and will
not sequence properly on sub-sequent boot.
This is a temporary workaround for Reef Proto,
a hardware change will be implemented on EVT.
BUG=chrome-os-partner:53974,chrome-os-partner:54507
BRANCH=none
TEST=Reef powers to S0 and starts coreboot after EC reset
Tested with servo cold reset button
and console reboot command
Change-Id: I32aa004b000895da2c97d1014a8ef48c0a98779d
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354762
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54503
BRANCH=none
TEST=Manually tested using console commands on both the ports.
a. Issued 'gpioget AC_PRESENT', observed AC_PRESENT is
1 when AC connected & 0 when AC disconnected.
b. Issued 'hibernate' & on plugging in the AC, device
boots to S0.
Change-Id: Iad09914d79cdbd798fb650146321eafed06eb91c
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/354721
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Added mutex lock for nvmem write/move operations. In the
current implementation, there is no single entry point
for the platform specific NvMem calls. The mutex lock is
coupled with a task number so that the same task can attempt
to grab the lock without stalling itself.
In addition to the mutex lock, changed where the cache.base_ptr
variable is updated. Previously, this was done prior to the
partition being copied from flash to the shared memory area.
Now, the variable is only updated after the copy so that read
operations will always read from the correctly from either
flash or from cache memory if a write operation has been
started.
BRANCH=none
BUG=chrome-os-partner:52520
TEST=Manual
make runtests TEST_LIST_HOST=nvmem and verify that all tests pass.
Tested with tcg_test utility to test reads/writes using the
command "build/test-tpm2/install/bin/compliance --ntpm
localhost:9883 --select CPCTPM_TC2_3_33_07_01".
Change-Id: Ib6f278ad889424f4df85e4a328da1f45c8d00730
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353026
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add a host event to support MKPB:
When sent, the ACPI code will send a notification to the kernel
cros-ec-lpcs driver that will issue EC_CMD_GET_NEXT_EVENT.
We can allow code (sensor stack for instance) that uses MKBP to work
on ACPI based architecture.
Obviously, host event over MKPB is not supported.
BRANCH=none
BUG=b:27849483
TEST=Check we get sensor events on Cyan through the sensor ring.
(cyan branch)
Change-Id: Iadc9c852b410cf69ef15bcbbb1b086c36687c687
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353634
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Adding ability to get # seconds before rtc alarm
goes off.
BUG=chrome-os-partner:52218
BRANCH=None
TEST=ectool rtcgetalarm w/o setting returns
Alarm not set.
ectool rtcsetalarm 30; ectool rtcgetalarm
to make sure counting down to 0. After alarm
goes off, rtcgetalarm should return alarm not
set again.
rtcsetalarm 30; rtcgetalarm to check alarm is set.
rtcsetalarm 0; should disable alarm. Use
rtcgetalarm to ensure that alarm is disabled.
Change-Id: I176b12fe2dda08eedd23ea33dc64785f09f1d9ae
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353331
Reviewed-by: Shawn N <shawnn@chromium.org>
following Change#227416 to meet client's spec.
BUG=chrome-os-partner:54263
BRANCH=master
TEST=`make -j BOARD=elm`, check factory force IDLE, works good
Change-Id: I1f0abdcbd56eeab379a6258869ccc133ff80736d
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/353521
Reviewed-by: Shawn N <shawnn@chromium.org>
We have no guarantee about the alignment of our input buffer so don't
use 32-bit access.
BUG=chrome-os-partner:54561
BRANCH=None
TEST=Manual on gru. Enable CHROMEOS_VBNV_EC, verify exception isn't
encountered on host command 0x17. Also verify call to
system_set_vbnvcontext followed by system_get_vbnvcontext results in
same data being read back.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I4df636b70c71a43a2dd6f584ee965135e90b4351
Reviewed-on: https://chromium-review.googlesource.com/354132
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
BD99955 DCDC wiil turn off Vsys voltage under VSYSVAL_THL_SET
or VREF_BAT<VBAT if Charging Voltage set under actual battery
voltage or VSYSVAL_THL_SET.
BUG=chrome-os-partner:53777
BRANCH=none
TEST=boot-up without battery. using zinger or oem supplier
used kevin rev2, rev3
Change-Id: I03c5c52790b2d481be3fa942054516fbefa3ce98
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/348563
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:54551
BRANCH=None
TEST=Manual on kevin. Verify negotiation to 20V when zinger is plugged.
Also verify "pd 0 dev 12" and "pd 0 dev 5" cause 12V/5V to be requested
from zinger.
Change-Id: I0298d535b791fa0c6f8ca077a6fd09a27e8ce77b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353804
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Overflow happens when raw value from ADC is greater than 0x7FFF.
When it happens, skip the result.
BRANCH=ryu,jerry
TEST=Without this code, the proximity sensor would show 22000in
instead of staying close to 0 when thumb is near sensor.
BUG=chrome-os-partner:53851
Change-Id: Id2182acbbf7b00157d9fee5d28bb61df4f166246
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/348300
When we jump from RO to RW, tcpc_vbus declared in tcpci.c
is initialized to 0. So even if we had VBUS present before,
PD_FLAGS_VBUS_NEVER_LOW is not set and soft reset cannot be used
later when source cap is timeout. This causes power loss and reboot
when we boot up system without battery.
Set PD_FLAGS_VBUS_NEVER_LOW after tcpm_init() so we can refresh
tcpc_vbus from TCPC first.
BUG=chrome-os-partner:53496
BRANCH=none
TEST=test on elm.
Remove battery and boot up successfully only with AC.
Use "sysjump rw" command and ec won't reboot by pd hard reset.
Change-Id: Id4737f076a9572cb540310f9fdce062198257967
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/352833
Reviewed-by: Rong Chang <rongchang@chromium.org>
Implement the standard LED control scheme for gru, using a single PWM to
set the battery status LED color rather than the traditional GPIOs.
BUG=chrome-os-partner:54379
BRANCH=None
TEST=Manual on gru. Verify LED is green when charging w/ nearly full
battery, off when discharging w/ nearly full battery, amber when
charging otherwise.
Also verify LED control host commands work as expected:
ectool led battery green=1 // green
ectool led battery amber=1 // amber
ectool led battery red=1 // red
ectool led battery red=0 // off
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I184e72c552e6d2196aef2724af9292806e0ea8c0
Reviewed-on: https://chromium-review.googlesource.com/352520
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
It is necessary to be able to build usb_updater for both host and
board environments.
When building for board environments the appropriate compiler and
binutils are defined in the environment. Allow the environment
definitions to take precedence over local definitions.
BUG=none
TEST=inside and outside chroot:
. ran 'make clean; make; verified that command can be run on the
host.
inside chroot:
. ran 'emerge-kevin ec-utils' and verified using the 'file' utility
that the executable in /build/kevin/usr/sbin/usb_updater is built
for arm
Change-Id: If2ac4a4e7f7ece188eba5ff917a510363c6d1990
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353165
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
FUSE_CTRL_OVERRIDE overrides all rbox fuse values with the values in
RBOX_DEBUG not just the ones that are explicitly set. This change
removes the override from rbox.
BUG=chrome-os-partner:54238
BRANCH=none
TEST=on gru and kevin check that pressing 'c' registers on the EC.
Change-Id: I655e9ca96e52359a7d36e0d691f838c335df8cb8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/353033
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Previously our charger ISR called a deferred task which woke our charger
task. We can skip the deferred task and just wake our charger task
directly.
The other meaningful change here is to assume that we're using the
charger for VBUS detection / BC1.2 if we have a usb_chg task, which
holds true for all of our current boards with this charger.
BUG=None
TEST=Manual on kevin with subsequent commit. Verify charger connect /
disconnect detection works properly on both ports, with zinger, donette
and generic DCP charger.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iad4f3ea90947b50859c549b591675e325717209f
Reviewed-on: https://chromium-review.googlesource.com/352822
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This makes the boot time less painful since it requires a long delay
for FW loading after power on this chip. This also makes it easier to
upgrade FW as we don't need to power on the chip before doing upgrade.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=plug and unplug dongle and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: Ia344c748697a3b1d06c9b442e1bf1d7227861f9b
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/347181
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ANX7688 is a TCPCI compatible port controller with HDMI to DP converter.
The HDMI converter needs a reset every time after enabling its function.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=manual
boot elm proto
plug and unplug dingdong and check DP output
plug/unplug adapter and check pd 0 state
Change-Id: I774421d7b0b8d2cfd31e860fcd4eaed08ee48ac7
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Tang Zhentian1 <ztang@analogixsemi.com>
Reviewed-on: https://chromium-review.googlesource.com/340371
Commit-Ready: Koro Chen <koro.chen@mediatek.com>
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Enable charger interrupt for VBUS / BC1.2 detection on kevin / gru.
Also, keep our USB data switches connected while we figure out how to
implement USB mux control.
BUG=None
TEST=Manual on kevin with subsequent commit. Verify charger connect /
disconnect detection works properly on both ports, with zinger, donette
and generic DCP charger.
BRANCH=None
Change-Id: I602e7bd3180110d351ec4c2916a6b8612c7e5f82
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352821
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Shelley Chen <shchen@chromium.org>
The README points the reader back to the docs directory where the
CCD documentation lives. I've added information about the install
script, and about how the raiden module identifies a CCD serial
console.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I8714dffcad0b8c30f46529a8f2d670b5d432cda6
Reviewed-on: https://chromium-review.googlesource.com/352787
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
loader/key_ladder.c depends on debug_printf(). Refactor
the printf function so that key_ladder.c need not depend
on main.c.
This change being made in preparation for a future
change which introduces a dependency between RW and
key_ladder.o
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=build succeeds
Change-Id: I5c9bf7bd6dd9f76ab6410e6e797973bdb072ec16
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351760
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change implements distinct key derivation trees for
ECC and RSA key generation. The seed used for derivation
is HMAC(primary_seed, ALG), where ALG is either
"ECC", or "RSA".
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: Iee85731bdac02b7b1061e9220786bee52dbf6289
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351750
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This rule makes it easier to use CCD devices when the raiden module
can't be installed for some reason. The rule informs the usbserial
module that it should handle anything that looks like a simple serial
port for any CCD compatible USB devices.
The install script now detects failure when building and installing
the raiden module and offers the --fallback option in that case.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I617bbdfb4c5cb9e9803f4088c651f84e3f72bd28
Reviewed-on: https://chromium-review.googlesource.com/351873
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If i2c communication with the TCPC is failing after 300ms+ then it's
likely going to fail forever, so return an error to allow the PD task to
continue initialization.
BUG=chrome-os-partner:53815
BRANCH=None
TEST=Manual on reef. Disconnect TCPC, attach charger to other port, and
verify charge manager correctly sets current limit based on detection.
Change-Id: I2c12320971a77504292f75393791e609e34897b4
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352501
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Default setting is at 48MHz.
For PLL frequency at 24MHz:
1. USB module can't work, it requires 48MHz to work.
2. SSPI clock frequency is divide by two.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. uart, i2c, timer, and pd modules are function normally
at different PLL frequency settings.
2. use 'flashrom' utility to flash EC binary with different
PLL settings.
Change-Id: Iabce4726baff493a6136136af18732b58df45d7f
Reviewed-on: https://chromium-review.googlesource.com/347551
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since the pending bit of host access interrupt is set frequently if
PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering
S0. It's better to add checking enable bit of MIWU of it in case huge
latency between gpio interrupt and serving its own ISR in INT11's ISR.
Modified sources:
1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/352362
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
PP1800_PMU impacts the initial centerlogic voltage due to DVS circuitry.
Since there's no other sequencing dependency, turn it on earlier.
This fixes centerlogic from initially starting too high (1.5V).
BUG=none
BRANCH=none
TEST=Watch PPVAR_CENTERLOGIC and confirm that it starts at the target voltage
Change-Id: Icac076a7e8aef978401452a98d9f6bc8b373d94f
Signed-off-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/352247
Reviewed-by: Shawn N <shawnn@chromium.org>
There is only one charger IC and one interrupt PIN for both the ports
and also from the ISR it's not possible to decode from which port the
interrupt is triggered hence a deferred function is used to trigger
the wake event for the ports. As there is no additional benefit of
having an extra task, added code to use only one USB charger task for
both the ports.
BUG=chrome-os-partner:54272
BRANCH=none
TEST=Manually tested on Amenia. BC1.2 detection is success
and the battery can charge on both the ports (VBUS/VCC).
Change-Id: I2745a5a179662aaeef8d48c8c1763919e8853fd0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351752
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Leave USB-A charging enabled in S3, and move gru-specific code into
board hooks, out of the power state driver.
BUG=chrome-os-partner:54159
BRANCH=None
TEST=Manual on gru. Verify USB-A enable GPIOs are asserted in S0 and
deasserted in G3.
Change-Id: Icadeb771226dd0fda4ae96fdde9b3984d87fdd15
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351670
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Power-down sequence in reverse order of power-up, with delays extended
to 10ms, to allow rails extra time to decay.
BUG=chrome-os-partner:54159
BRANCH=None
TEST=Manual on gru. Verify repeated `powerbtn` commands on console
boot + power-down the SOC.
Change-Id: I2e8fb39f8f900e56deef6b386bae1c336aa1f963
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351520
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The motion sensors array as well as the config variables were copied
from another board and mostly wrong for Reef.
BUG=none
BRANCH=none
TEST=sensors which are connected successfully initialize, still need
to test lid sensors.
Change-Id: If8e1ec79803c7f378b21f4e9423a56bd6763eb4e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/349733
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
If the lid is initially closed, keyboard scan should be disabled.
BUG=chrome-os-partner:53566
BRANCH=none
TEST=Check ESC+Refresh+PwrBtn is detected.
Check keyscan is enabled if lid is open.
Check keyscan is disabled if lid is closed.
Check power button is functional if lid is opened.
Check power button is masked if lid is closed.
Change-Id: I2354a657d8bf0c13207517cc789547a68befd240
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/351534
Reviewed-by: Shawn N <shawnn@chromium.org>
In TCPCI specifiction R1.0 4.7.2, the last step of transmitting
hard reset message is enable PD message passing by writing to
RECEIVE_MESSAGE register.
BRANCH=none
BUG=chrome-os-partner:52815
TEST=manual
build and load on reference board with anx7688 port controller.
connect zinger to port 0, and use ec uart console to send hard
reset message:
pd 0 hard
check PD communication
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I52968b603f0227d7d9a112b0216cd5fd6362a0b2
Reviewed-on: https://chromium-review.googlesource.com/348142
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a certificate verifier, so that endorsement
certificates may be verified upon installation.
Doing so allows for catching certificate errors early.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=all tests in test/tpm_test/tpmtest.py pass
Change-Id: I9339a6bc36e4d82ae875ce774e31848ae983fa1f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/351031
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Section 5.3.1 TPM Register Space Decode of TCG PC Client
Platform TPM Profile (PTP) Specification Rev 00.43 allows
partial access to registers: "Software may access only part
of a register, e.g. read or write one byte of a 4 byte register."
BUG=chrome-os-partner:54286
BRANCH=none
TEST=tpm driver successfully sets TPM_STS_COMMAND_READY
(see more details in BUG)
Change-Id: I92995f04c6f6221ab7e00d086c4067e447557476
Signed-off-by: Andrey Pronin <apronin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/351701
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
State that needs to survive re-flashing
of RO+RW is stored in the INFO bank. An
example of such state is manufacture secrets,
which need to survive reflashing from the
personalize firmware to the initial TPM2
firmware.
This change adds support for writing to
the writeable flash info bank.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=manually verified info1 reads and writes
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I9226e2161e036d1dacccbe55b67724b449983008
Reviewed-on: https://chromium-review.googlesource.com/351274
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
LID_OPEN gpio is present on the daughter card and provided by the
EC. Add an internal pull-up on it for the cases when the daughter card
isn't plugged in.
This fix won't be required starting EVT.
BUG=chrome-os-partner:54143, chrome-os-partner:53566
BRANCH=None
TEST=Compiles successfully. "gpioget LID_OPEN" returns 1 without
daughter card.
Change-Id: Ieff281b489e4f3f8be184a55b7975fb2efcc1099
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/350460
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If our battery isn't able to provide enough power to the EC on boot, we
should not cut off our input power, regardless of dual role
determination or other charging policy.
BUG=chrome-os-partner:54058
BRANCH=None
TEST=Manual on gru. Drain battery completely, attach USB-C charger,
verify that "Battery critical, don't disable charging" is seen on the
console and the EC doesn't brown out.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I981f9dbf3d84390550bb696e561f5fa51ffc573a
Reviewed-on: https://chromium-review.googlesource.com/351224
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
