Enable hibernate on zinger for DVT. Note: this may break
some EVT zingers.
BUG=chrome-os-partner:28335
BRANCH=samus
TEST=make buildall
Hibernate tested in CL:220837
Change-Id: I65f4776d27ad88beee101fb00d0b6221ba272a26
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The valid and writable flags the EC sends back to the AP are incorrect.
They are a little bit different on differnt chips, so let's move it to
flash physical layer. This is not any causing problem, but we should fix
this.
BUG=chrome-os-partner:32745
TEST=make buildall
BRANCH=samus
Change-Id: Ibcda5ae770f5ea02cde094490997a5bc447df88f
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222661
Reviewed-by: Randall Spangler <rspangler@chromium.org>
USB PD spec now calls for HPD signal to be managed across the USB PD
protocal. In preparation this CL makes the HPD GPIOs outputs and
initially low.
This should NOT effect older revs of the design as GPIOs were unused
(had unstuffed option for external XTAL).
BRANCH=samus
BUG=chrome-os-partner:30645
TEST=compiles & runs. With reworked board can manually trigger HPD.
Change-Id: I0a64c1daf8d8c866f5de237c3daf4be028eecd63
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223462
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On STM32F0, we cannot work around the hard fault triggered when trying
to protect the whole flash. Therefore, we need to go with the
ALL_AT_BOOT approach. When write protect is enabled, instead of setting
ALL_NOW flag to immediately lock down the entire flash, we need to set
ALL_AT_BOOT and then reboot to have the protection take effect.
BUG=chrome-os-partner:32745
TEST=Along with the next CL. On Ryu:
1. Enable HW WP. Check the output of 'ectool flashprotect' and see
correct flags.
2. 'flashrom -p ec --wp-range 0 0x10000'. Check RO_AT_BOOT is set.
3. Reboot EC and check RO_NOW is enabled.
4. Boot the system and check ALL_NOW is set.
5. Update BIOS and reboot. Check software sync updates EC-RW.
6. 'flashrom -p ec --wp-disable' and check it fails.
7. Disable HW WP and reboot EC. Check RO_NOW and ALL_NOW are cleared.
8. 'flashrom -p ec --wp-disable' and check RO_AT_BOOT is cleared.
TEST=Enable/disable WP on Spring. Check RO_AT_BOOT/ALL_NOW can be set
properly.
BRANCH=samus
Change-Id: I1c7c4f98f2535f1c8a1c7daaa88d47412d015977
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222622
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The ADC interrupt does not clear the NVIC pending register. This
can cause the interrupt to fire more than once for a given
interrupt.
BUG=none
BRANCH=samus
TEST=Send hard reset from samus to zinger using "pd 1 hard" on
PD MCU console. This causes zinger to cut its output voltage
and go into voltage discharging mode. When voltage discharge is
complete, we get an ADC interrupt and switch back to current
monitoring. Before this CL, sometimes (1 out of 20) times the
ADC interrupt will fire twice, causing an OCP to be detected.
With this CL, we never see the double fire.
Change-Id: I91397a04773d04e263bc80a698c8799342b80a2e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223381
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is a preparatory work for the following change for write protection
support on STM32F0.
BUG=chrome-os-partner:32745
TEST=make buildall
BRANCH=samus
Change-Id: Ic4deea06e26c4a6ac024a5388e1a5783b40e9876
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222660
Reviewed-by: Randall Spangler <rspangler@chromium.org>
charge_manager is intended to manage charge limits from various tasks
(typically PD charge tasks and USB / BC 1.2 charge tasks). These tasks
can update the charge limit of a port by calling charge_manager_update
(thread-safe function). If the charge limit has changed,
charge_manager_refresh will be queued as a deferred task, which will
select the "best" charge port and set the proper charge limit.
In order to use charge_manager, a board needs to do the following:
1. Declare PD_PORT_COUNT in usb_pd_config.h
2. Implement board_set_charge_limit
3. Implement board_set_active_charge_port
4. Call charge_manager_update whenever the available charge on a port changes.
BUG=chrome-os-partner:31361
TEST=Manual on samus_pd, with subsequent commit. Insert and remove
various chargers, check console to verify PD charger always has priority
and correct current limit is set based upon 'best' charger.
BRANCH=samus
Change-Id: Iede120b69e0b46ed329bcf9b7e07c39ba5e9f77b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222723
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Makes a significant encoding change to existing opcodes and
adds several opcodes to allow for encoding the more complicated
patterns that we have on the lightbar (S0, etc.) as well as
condense the ones we technically could encode but couldn't
fit in the 192-byte footprint allotted to us (KONAMI).
We need this to remove sequences from the EC code.
BUG=chrome-os-partner:32203
BRANCH=ToT
TEST=run test programs on hardware and lightbar simulator
Signed-off-by: Eric Caruso <ejcaruso@chromium.org>
Change-Id: I12fe908d3a43a924aa39f24ad66adbe53f7f38e1
Reviewed-on: https://chromium-review.googlesource.com/222949
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
With only four LED segments, it's confusing to indicate a power
percentage by dimming the top segment unless you can see the
indicator smoothly ramping up from all-off. This does that.
Kind of pretty, if I say so myself.
BUG=chrome-os-partner:29041
BRANCH=ToT, Samus
TEST=make buildall
Run "ectool lightbar demo on", then press the T key to invoke the
pattern and the arrow keys to fake the charge state.
Change-Id: Ib6a56aea56078b8c1fc9edddda469d7f41735ff7
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223300
Reviewed-by: Alec Berg <alecaberg@chromium.org>
The PD task is using more space in the stack and I'm seeing frequent
stack overflow on Plankton. On Samus, we already increased the stack
size. Let's also increase this on Ryu and Plankton.
BUG=None
TEST=make buildall
BRANCH=None
Change-Id: I468985303b7fd38455dd1fed9db54544581c49cf
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223368
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Display battery percentage on the lightbar whenever AC status
changes.
BUG=chrome-os-partner:32894
BRANCH=samus
TEST=Plug and unplug AC in S0 and in G3 and make sure that lightbar
displays battery percentage each time
Change-Id: I281c9242d185da06b0c778de12e4f6340779a840
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223362
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Implemented source recovery time following a hard reset. According
to the spec:
After a hard reset, the source must dissipate output voltage
to vSafe5V. After establishing the safe voltage condition on VBUS,
the power supply shall wait tSrcRecover before powering VBUS to
vSafe5V.
BUG=none
BRANCH=samus
TEST=plug in a type-c to type-a adapter to samus. then issue a hard
reset from the console and verify that it takes nearly a second before
samus re-enables vbus.
Change-Id: Id21eb7cf03759b7ecd64ad11c3c57e66cf35370a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222935
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
For a sink, when there is no source cap packet within SinkWaitCapTimer,
then it sends a hard reset. Once the hard reset has been retried
nHardResetCount times then it shall be assumed that the remote
device is non-responsive, and we stop sending the hard reset.
BUG=none
BRANCH=samus
TEST=Tested with a non-PD charger. When plugged in, we see two hard
resets and then it stops
VBUS 1, 1!
C1 st3
C1 st14
C1 st2
HARD RESET!
[494.906344 HC 0x100]
C1 st3
C1 st14
C1 st2
HARD RESET!
[495.668624 HC 0x100]
C1 st3
> adc
C0_CC1_PD = 20
C1_CC1_PD = 1783
C0_CC2_PD = 36
C1_CC2_PD = 21
V_BOOSTIN = 5329
>
Change-Id: Ib0fc49642aba754015b8055cf1971577b48ac058
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222853
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add support for enabling Vconn on Raiden ports by defining
CONFIG_USBC_VCONN. This is enabled by default for ryu, samus,
and fruitpie.
BUG=chrome-os-partner:30445
BRANCH=samus
TEST=Load onto samus. Make sure we can still charge from zinger.
Plug in type-A to type-C adapter with pulldown and see that samus
becomes power source. Do a gpioget and verify that only one VCONN
GPIO is enabled (low), and the VCONN that is enabled is opposite of
the polarity queried by pd 1 state. Try both ports, both polarities
and make sure the correct VCONN gpio is enabled.
Change-Id: Icea4c18b9c813cf7e8e21fd4f455bbd5fb4dbc91
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222850
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Per alternate mode this GPIO should not be enabled until alternate
mode has been successfully entered.
BRANCH=none
BUG=chrome-os-partner:31192
TEST=manual, compile & boot on hoho gpioget PD_SBU_ENABLE = 0
Change-Id: Ide2a47851f30812b289221e302a930134a58a8a0
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223159
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Move the 3.3DSW_GATED rail to be enabled in transition to S0 and
disabled in the transition to S3.
This is the rail for the core regulator and temp sensors so it
does not need to be enabled in S5.
BUG=chrome-os-partner:32382
BRANCH=samus
TEST=build and boot on samus, successfully suspend/resume and
ensure that PP3300_DSW_GATED is turned off in S3.
Change-Id: Ic47f81860e3f0cb7b5d81ba96181b7ee7cf72f66
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223077
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reboot the PD device after a successful flash so that it will boot into
the new RW. This syncs the ectool PD update to the implementation in
flash_pd.py.
BUG=chrome-os-partner:31361
TEST="./ectool --name=cros_pd flashpd 0 1 ec.RW.bin", verify flashing
succeeds and PD is rebooted after flash.
BRANCH=samus
Change-Id: I14e7dffe59fcc7ca678c76890dbc825df5b19862
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223062
Reviewed-by: Alec Berg <alecaberg@chromium.org>
There's already an external pull-up to PP3300. The internal pull-up has
no use but provides a leakage path when the AP is off.
BUG=chrome-os-partner:31762
TEST=Repeatedly power cycle Ryu. Check the system goes to S0/S5.
TEST=Power off from the AP. Check the system goes to S5.
BRANCH=None
Change-Id: Id0ae966414de01e3a2b91314f661f37941175a87
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222625
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Wire up the discovery's four LEDs and one user
button as GPIOs that can be written and read using
the new USB GPIO driver. This also adds an extra
tool called usb_gpio that provides control of GPIOs
from the linux command line.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=cd board/discovery-stm32f072 ; make flash
cd extra/usb_gpio ; make
usb_gpio write 0x1e 0x00
Change-Id: I15115f82b15b6c35d1a34b83b7114a6bfa6a3d67
Reviewed-on: https://chromium-review.googlesource.com/218270
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Remove the meaningless version string in iSerialNumber, which was incorrect
since this string should be unique to a device if it exists.
Export the firmware version string as the configuration string, so it's
traceable to a given firmware build/sources.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=make buildall
from a workstation, do "sudo lsusb -v" and see the full version string
exported as the configuration name.
Change-Id: I557df2936421e2926ac0fc0003888370cec3e201
Reviewed-on: https://chromium-review.googlesource.com/222877
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
ectool has switched over to using getopt for command line options parsing.
This breaks temp_metrics' invocation of "ectool tmp006cal" command since
some of the coefficients are negative and therefore start with "-".
getopt treats that as another command line option causing ectool to
barf.
BUG=chromium:422160
TEST=On a Pixel issue "sudo start temp_metrics" and check
/var/log/messages to ensure that no new messages such as "init:
temp_metrics main process ended, respawning" show up.
BRANCH=none
Change-Id: I42232b3027ec6339814d226f1d8ab493e3420eea
Signed-off-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222845
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a compile-time configuration to make Twinkie behave as
a USB Power Delivery consumer/provider device rather than a
transparent sniffer.
To use it, edit board/twinkie/ec.tasklist:
enable the PD task and comment out the SNIFFER task.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=connect it to a Fruitpie and use "pd charger" command on Twinkie
console, see the Fruitpie receiving the source capabilities and
answering.
Change-Id: Ic2b4ba2d166ea1d3f5f9be410453a030a4ee7b68
Reviewed-on: https://chromium-review.googlesource.com/204168
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Change effects:
1. samus_pd: Acts as initiator of SVDM discovery once its reaches source
ready and upon identifying UFP with display port
alternate mode enters that mode.
2. hoho: Acts as responder for SVDM discovery providing its identity,
svids and svid capabilities which are display port only. If
asked to enter display port alternate mode it does.
3. fruitpie: Acts a initiator with mock display port mode.
BRANCH=none
BUG=chrome-os-partner:30645
TEST=manual,
Plug hoho into samus_pd
- see dpout
- from console
> typec 0
Port C0: CC1 451 mV CC2 111 mV (polarity:CC1)
Superspeed DP1
Change-Id: I1a76767353a69baeceffa3e79c37dcea77b8337d
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221354
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The BOS (Binary Device Object Store) descriptor was added to the USB
specification (3.0) to allow a richer set of device capability
specific descriptors.
The Billboard class is meant to expose (read-only) the status of USB
devices capable of alternate mode functions. It's required to use the
BOS descriptor type and at a high level looks like:
- BOS Device Descriptor (5bytes)
- Container ID Device Capability Descriptor (20bytes)
- Billboard Device Capability Descriptor (44byte + 4 * numSVIDs)
This CL adds:
1. Ability for Get Descriptor on BOS descriptors. Note hidden behind
CONFIG_USB_BOS as these descriptors change USB device requirements
to:
- bcdUSB >= 0201
- no interface descriptors
2. structures for all BOS, Container & Billboard descriptor elements
complete w/ CamelCase.
BRANCH=none
BUG=chrome-os-partner:32652
TEST=compiles with CONFIG_USB & CONFIG_USB_BOS enabled.
Change-Id: I1b24bc728f2ebba7d91840801d2ebe576e240e7c
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221570
When a control transfer requests a descriptor larger than 64 bytes, we
need to do several IN transfers to get the proper packet sequence :
SETUP IN IN IN .. IN OUT(null)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:32652
TEST=set USB_STR_VERSION to "012345678901234567890123456789ABCDEF",
then do "lsusb -v" on the host and check the USB transfers
with the protocol analyzer.
Change-Id: I6940095008cb2a34c6896b337c5eda4fa267adc1
Reviewed-on: https://chromium-review.googlesource.com/222700
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Decode Pericom registers to current limits.
BUG=chrome-os-partner:32003
TEST=Manual on samus_pd. Insert 1A Apple charger, verify current limit
is correctly detected as 1A.
BRANCH=samus
Change-Id: I310d9f22cef80e97c1734e6a56f0034ebe01df31
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222638
Reviewed-by: Alec Berg <alecaberg@chromium.org>
When charger is initialized disable the LEARN option i.e. reenable
charging on AC power
BUG=chrome-os-partner:32320
TEST=set DUT to discharge on AC and then reflash EC. Ensure that
charging begins again.
BRANCH=none
Change-Id: I3e83db27ab49548d5491548fa624899865c11bfb
Signed-off-by: Mohammed Habibulla <moch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222644
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Some platforms may need to take different actions depending on which
port is requesting a limit. Add a new port parameter to the
pd_set_input_current_limit API to accomodate this.
BUG=chrome-os-partner:32003
TEST=Manual on samus_pd. Verify zinger charges battery.
BRANCH=samus
Change-Id: I1578252c751b3a80b4da6ca68e2a958934283cbf
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222621
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This prepends EC_ a macro exposed in ec_commands.h, moves a
macro into lbcc that is not used elsewhere, and changes lb_program
structs to lightbar_program.
BUG=None
BRANCH=ToT
TEST=make buildall -j
Change-Id: I481562da72d91f846c64cf9af40338027641462c
Signed-off-by: Eric Caruso <ejcaruso@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222406
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If CONFIG_HIBERNATE is explicitly undefined for a board, the EC
shouldn't hibernate when the battery is running low. Otherwise, the EC
reboots because of the lack of hibernate support, and this actually
burns more power.
BUG=chrome-os-partner:32727, chrome-os-partner:32779
TEST=Drain the battery to 2% and verify the EC is behaving.
BRANCH=None
Change-Id: I2f9f5fd8fb4b5be4d8da113da4ef26c062869a07
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222615
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add support for enabling USB type-C Vconn by defining CONFIG_USBC_VCONN.
Enable Vconn support for samus, ryu, and fruitpie.
BUG=chrome-os-partner:30445
BRANCH=samus
TEST=make buildall
Change-Id: Ibe247286c96fd5a8fa12c88a4e3a5fea02997134
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222284
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The PD protocol no longer uses a SHA1 RW hash. Instead, it uses the
first 20 bytes of the SHA-256 hash. Update constants and comments
accordingly.
BUG=chrome-os-partner:31361
TEST='make buildall -j'
BRANCH=samus
Change-Id: Ice74b841dbd1d81205c1ef0079a5e18fca2153b6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222446
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Gets a little more coverage on the SET_COLOR control operand.
BUG=None
BRANCH=ToT
TEST=On hardware and simulator. Should appear exactly the same
as rainbow-shift.bin.
Change-Id: Id9c9948ae178884180e4d42e4fcceb58218423f8
Signed-off-by: Eric Caruso <ejcaruso@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222004
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This lowers the CPU temp at which the fans start up, from 55C to
43C. It also increases the slope a bit, so that they run a little
faster as well.
BUG=chrome-os-partner:32260
BRANCH=ToT,samus
TEST=manual
Visit www.fishgl.com/?full both before and after this CL.
Before, the keyboard got a little too warm. After, the fans come
on sooner and the keyboard is cooler.
Change-Id: I5c4947c5d2bb4a28c0ac449e109e2bd1af84068c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/222171
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Allows dingdong to receive initial USB PD communication (source
capabilities payload) and with some manual manipulation (see 'TEST=')
drive DPout.
CL is based heavily off hoho dongle where all files were copied from
board/hoho:
7b1e58c ectool: Add host command support to set fan RPM for each
fan separately
Files gpio.inc, board.h & board.c were modified but others should
be identical.
BRANCH=none
BUG=chrome-os-partner:31193
TEST=manual,
When attaching dingdong to samus_pd and configured via
'pd dualrole source'
I see following on samus_pd console:
C1 st9
Switch to 5000 V 900 mA (for 900/900 mA)
C1 st10
C1 st11
C1 st12
showing power constract and transition to SRC_RDY:
> pd 1 state
Port C1, Enabled - Role: SRC Polarity: CC1 State: SRC_READY
> typec 1 dp
Also if I connect in CC1 configuration and get access to dingdong
console I can
> gpioset PD_SBU_ENABLE 1
And see dingdong drive external monitor
Change-Id: I30ef6f8503a3fb015cfb8806bc36fb98f5150e40
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/221913
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
