- Add 3ms after write, found issue with SPI writes.
- Do not check FIFO if all sensors are disabled.
It contains garbage (0x848484....)
- Do not check FIFO length. It can be 0 even if there
is data in the fifo.
- Remove forever latch and do not reset Interrupt in the handler,
we are using level interrupt.
- Flush and exit when the FIFO is in a bad state.
BRANCH=smaug
BUG=chrome-os-partner:43339,chrome-os-partner:39900
TEST=Ran CTS tests. Check sensor is stable.
Change-Id: I5cbae819e780b4d50d02829fd8e1178cf34c3f84
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289839
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to call irq_handler and load_fifo even if the
first sensor is disable. Nothing is done on otherwise.
Move code to recalculate sample rate to the right place.
BRANCH=smaug
TEST=Check data is collected when accel is disabled.
BUG=chrome-os-partner:39900
Change-Id: Ia6025a670abaf2e71ccbe784bce24e08becf399e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289838
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We are very close from the current limit (456 bytes).
Increase the limit to 640 bytes.
BRANCH=smaug
TEST=Hit the limit while debugging, check the new limit.
BUG=none
Change-Id: I6673000bcac48b88599082eb797f0782c4fee454
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289837
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
SPI being much faster, need to add right sleep to wait for
sensor to change state from suspend.
Set the ODR before the range, an issue I did not have with i2c.
Fix test used when FIFO is disabled.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Check sensors are coming and rate/range are correctly set.
Change-Id: I5bf655626f1f4232478a04d1d4e1a0d443efbf0f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288517
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add interface to access the sensor using SPI interface.
BRANCH=smaug
TEST=compile and work on new Ryu board
BUG=chrome-os-partner:42304
Change-Id: I987259a7e378de8ada3b3b55b3662e5028ea31b2
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288515
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Like the implementation for mec1322, add a lock around spi_transaction.
It prevents 2 tasks from accessing a given bus at the same time.
BRANCH=smaug
TEST=Check the BMI160 FIFO corruption disappeared in SPI mode.
BUG=None
Change-Id: I9e8a9e39ca96ea56692e3125930ab05ae6ef143f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289856
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Modify i2c driver on mec1322 to change from sleeping and waking
on i2c interrupt, to just doing a blocking wait for i2c transfer
to complete. This greatly improves the i2c transaction time on
fast busses.
BUG=chrome-os-partner:43416
BRANCH=none
TEST=test on glados. test can talk to battery and PD MCU. Use
logic analyzer to see delay between bytes during an i2c transfer.
The delay goes from ~70us to ~4us.
Change-Id: Iee2a903d27b2e50e54d64bd6d5ed4920293fe575
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289667
Reviewed-by: Shawn N <shawnn@chromium.org>
Oak takes power from type-C charger. The default input current limit
should set to 512mA default, not the maximum current for battery
charging.
BRANCH=none
BUG=none
TEST=manual
load on oak and plug an empty battery. check EC uart console on PD
state change when plug type-C charger.
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I113fea5ff1e8afc053f76c21820f202e4b3edfec
Reviewed-on: https://chromium-review.googlesource.com/287610
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.
Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
Allow more than one SPI master.
Add CONFIG variables to address the system SPI flash.
To have SPI master ports, spi_ports array must be defined.
BRANCH=smaug
TEST=compile
BUG=chrome-os-partner:42304
Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288512
Commit-Queue: David James <davidjames@chromium.org>
The ec_date.h file had incorrect dependencies. $(objs) had no meaning
outside of the building the object files as it gets privately overidden
with the corresponding target objects (RO, RW, libsharedobjs). This
caused ec_date.h to only be generated once from a clean. This commit
fixes that by adding all of the RO and RW objects as dependencies (with
the exception of version.o).
BUG=chrome-os-partner:43373
BRANCH=None
TEST=Built ryu, checked build timestamp in build_info. Touched a file,
rebuilt, verified that build timestamp was updated.
TEST=make -j buildall tests
Change-Id: I0ab107efc1a504b4f871ebcf595754db1d414c7a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/289338
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Decrease default system stack size on stm32f05 which only has 8k
of RAM.
BUG=none
BRANCH=none
TEST=tested on glados. just ran glados_pd and plugged various
peripherals into type-C port and saw nothing unusual.
Change-Id: Ic051a1387903662414c8e4fdc431e6ecfd7ad57f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289555
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added macros to conditionally compile the console commands to save the
memory. These macros can be enabled/disabled in the board specific files.
BUG=none
TEST=make buildall -j
BRANCH=none
Change-Id: I108a072c333762cd24ea973612202c9cc4d40914
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/288950
Reviewed-by: Shawn N <shawnn@chromium.org>
Implement and enable custom charging profiles on glados to
allow us to charge faster.
BUG=chrome-os-partner:42864
BRANCH=none
TEST=load on glados and charge at room temp. verify using
"charger" command that the battery current matches the
expected fast charging current for the given temp range.
Change-Id: I7b213fd1724e9df09ada89ca27b05e0540b4de2a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288208
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Modify host_command_pd.c to loop over sending of PD status
host command and processing the response as long as the
alert GPIO is active.
This fixes a potential bug that if the alert line is held
low for more than one PD status host command, then we would
not process the return status.
Also, fix a bug in which we could call alert() for a
non-existent port.
BUG=none
BRANCH=strago
TEST=verified on samus and glados. connected charger and verified
that we negotiate a contract and set appropriate input currnet limit.
Change-Id: I3b2db87b51f55fc2b20a4695bd466ff8bb09ea55
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288819
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: David James <davidjames@chromium.org>
Chipset task is overflowing and causing runtime crash.
Increasing the chipset task stack size by 128 bytes.
BUG=chrome-os-partner:43329
BRANCH=none
TEST=Build/flash EC and boot the platform to OS.
Change-Id: I4e444cc48979c74810851ab2625b982fdabdeb73
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/289112
Reviewed-by: Shawn N <shawnn@chromium.org>
For multi-byte ACPI memmap reads, we previously had a mutex to ensure
data continuity. A better approach is to use a read cache. Since the
kernel will enable burst mode before reading a multi-byte memmap
variable and disable it afterward, we can populate the cache on the
first read after enabling burst. This solution removes deadlock bugs, is
contained entirely in acpi.c, and saves a deferred function.
BUG=chromium:514283
TEST=Manual on Glados. Add prints in acpi_read, verify that multi-byte
reads come from cache and non-burst reads continue to function as
before.
BRANCH=Cyan
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I74e4927bf2b433e31a9ff65d72820fa087c51722
Reviewed-on: https://chromium-review.googlesource.com/288871
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable Try.Src for Glados, Kunimitsu, Strago, and Oak so that they
default to sourcing power when connecting to other dual-role
devices.
BUG=none
BRANCH=strago
TEST=make -j buildall
Tested on glados by plugging in charger, hoho, and another
dual-role device and making sure we resolve roles appropriately.
Change-Id: I9393e30b35620eeda3ef1ef56366a97e59ba8054
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288247
Reviewed-by: Shawn N <shawnn@chromium.org>
active state is global, remove it from motion_sensor structure.
Reinit sensors when entering RW, fix regression introduced by CL:284616.
Improve EC polling rate calculation by excluding suspended sensors.
Wake up sensor thread in case the motion task was in deep sleep.
Do not send sense interrupt while suspened. Will revisit once wakeup
sensors are implemented.
BRANCH=smaug
TEST=Check when in RW the sensors are exposed.
Check EC rate are correct in different power state.
Check when jumping from RO to RW and back, after setting the
frequencies parameters via sysfs properly, AndroSensor acquires
the data properly.
BUG=chrome-os-partner:43132,chrome-os-partner:40741
Change-Id: Ie70732b135a432d64935eead4200ddc0e1a7c0b4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288201
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Define second DMA controller, to be used by SPI3 on STM32F373.
BRANCH=smaug
TEST=Check with dmahelp the DMA engine is activated.
BUG=chrome-os-partner:42304
Change-Id: Id2490ab91092b1ed738f5318bdeebfbe93f09171
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288511
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
There was a bug in this function where the bit for host_command was
being set in the ec_status variable. This caused the ALERT# GPIO
line to be held low which in turn caused the EC MCU to loop
and keep reading the ALERT register.
BUG=none
BRANCH=none
TEST=manual Tested against Zinger in both ports and Zinger and Samus
at connected into each port. Verified that it established a PD contract
for both ports and that the alert line was no longer being held low
Change-Id: I5540440a68581521eb002411f728a4eac2f22caf
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288252
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
The atomic_* functions are often used in contexts where the data they
will operate on are volatile (due to being shared between tasks or a
task and an interrupt handler). Adding volatile here makes using the
atomic_* functions a little easier in those cases and removes a cast
from the call sites (which could be obscuring a bug, if for instance
the variable was modified to be a uint16_t).
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I71356eb3cf2c0506df38532eee767c7d78f9240e
Reviewed-on: https://chromium-review.googlesource.com/287516
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Jerry is being used for FAFT in the lab. Remove Pinky instead.
BUG=chromium:511324
TEST=make buildall -j
BRANCH=none0
CQ-DEPEND=CL:288258
Change-Id: I03ddc74a4e72353f3408da8e374ad925baf00a35
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288237
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
After I2C unwedge, *all* I2C ports will be re-initialized in
i2c_raw_mode() by gpio_config_module(MODULE_I2C, 1);
This means *all* I2C pins will be programmed as GPIO then enable I2C
alternate function.
If I2C Unwedge happened while there is an active I2C transacation on
another port, the active I2C transaction will be corrupted, since the
pins will be temporary programmed as GPIO Output High.
BUG=chrome-os-partner:40519
TEST=Warm-reboot test on Cyan EVT and no discharging while AC is on.
BRANCH=none
Change-Id: I3be1d5c60bf4ab385bc077202406ec7abd8b2add
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/287493
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Denny Iriawan <denny.iriawan@intel.com>
This patch adds a module which runs on top of the SPS driver and
implements the TCG SPI TPM protocol.
Basic register read and write functions are implemented as well as
rudimentary TPM state machine (claiming/releasing locality).
An enhancement is made to the SPS driver to ensure that when the CS is
deasserted the transmit FIFO is reset too, on the off chance of the CS
going away mid transaction for whatever reason.
In this implementation the slave is guaranteed to stall the master for
a few bytes in both receive and transmit transactions, which is
further aggravated by the fact that RX FIFO threshold is set to 8
(this is the minimum number of bytes the master has to send to wake up
the slave). This could be fine tuned later, for instance made a
parameter of the receive callback registration function.
BRANCH=none
BUG=chrome-os-partner:43025
TEST=trunksd initialization (with minor changes to accommodate new
VID/DID and some status bits, to be published) succeeds with the
cr50 connected to the USB/SPI cable.
Change-Id: I28d37c3b57dde9adf59e81426efe4f58880cf0b0
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/285252
As new features come along the console channel space limited at 32
becomes very tight. But not all features are present all the time.
Let's make some of the channels compile time configurable. This makes
for uglier code but allows to support more channels.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Id21560d4aa05c0e5245872c50ae19340cda8fd3e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/286610
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
SPI slave and master interfaces require very different code to
support, they should have separate configuration options.
Host command code printouts should use their own console channel.
Using SPS to designate SPI Slave interface is not universally
acceptable, a bug has been opened to discuss the alternatives and
clean up the code.
BRANCH=none
BUG=chromium:512613
TEST=make buildall -j
Change-Id: I6683286a221c4689ecc247fdfe8ebca529f3f458
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/286469
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
FIFO should not collect events of suspended sensors.
It could still happen at boot, when sensors are set up suspended.
BRANCH=smaug
TEST=Check for invalid FIFO events in HAL code.
BUG=none
Change-Id: Ie363afc3f3263bb10e03a8d0a8ee34b8b92bb6b4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288200
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add ECST tool to modify the header used by npcx booter.
Modified drivers:
1. i2c.c: Modify for i2c_port design.
2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue.
3. hwtimer.c: Fixed bug whcih event expired time is behide current timer.
4. lpc.c: Add intializing host settings after pltrst is deasserted.
5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle
when gpio is any-edge trigger mode.
6. task.c: Add workaround method for hard fault issue.
7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE
8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO
9. lpc.c: fixed obe interrupt bug during 8042 initialization
10.Adjust path of flat files for new Makefile rules
11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5
Signed-off-by: Ian Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/284036
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
The mec1322 SPI driver toggles CS manually (CONFIG_SPI_CS_GPIO), so the
pin needs to be a normal GPIO, not functional.
BUG=chrome-os-partner:43160
TEST=Run "flashrom -p internal:bus=lpc -r read.bin" on glados, verify
that read.bin contains actual flash data and not all zeros.
BRANCH=None
Change-Id: Ibaee03b43b4d9c25f6c074c02688d1cba20c7a02
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288321
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2,
which is not defined by default in order to support existing boards.
BUG=chrome-os-partner:42933
TEST=Verify that Glados v1 board continues to boot AP. Verify
compilation on GLADOS_BOARD_V2.
BRANCH=None
Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/287291
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit enhances the config option check python script to
significantly reduce the number of false positives.
- Now only checks committed changes.
- Only checks additions, not the whole file.
- Only checks uses of CONFIG_* not in a comment for both C-style and
Make-style files.
- Suports a whitelist.
BUG=chromium:510672
BRANCH=None
TEST=Detected missing configs in Makefiles and C source files.
TEST=/* CONFIG_FOO */ was not detected.
TEST=' board-$(CONFIG_OPT)=board.o # CONFIG_OPT2' only CONFIG_OPT was
detected.
TEST=Changes in working dir were not detected.
TEST=Changes to config_option_check.py were not detected.
TEST=cros lint --debug util/config_option_check.py
TEST=CONFIG_FOO in a multi-line C comment was not detected.
Change-Id: I5fc2ccc77bb4f319a3c85b7d81c83027959dc96b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/287519
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Move TCPC initialized bit from alert register into error status
register. This is not part of the TCPCI spec, but the existing
code creates a bug that if TCPM reboots without TCPC also rebooting,
then we will never get the initialized alert from TCPC since
it has already happened, so the TCPM will loop indefinitely
waiting for TCPC to be ready. This fixes the bug by moving the
bit to a status register, which is more appropriate.
BUG=none
BRANCH=none
TEST=load on glados, reboot and make sure TCPM see's that the
TCPC is initialized.
Change-Id: I8e96b59031e01a4faec8f519727df1fa95f498bc
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288342
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
use (LID_OPEN == 0 && BASE_PRES_L == 0) as the lid closed condition to
avoid false triggers.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42110
TEST=on Smaug EVT2, play with magnets and the genuine lid,
check we get the right "lid open" / "lid close" messages on the console.
Change-Id: Ie0a34fb7e45e8a424ff1cfda7662543d4f336f1a
Reviewed-on: https://chromium-review.googlesource.com/287853
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Add a X-macro CONFIG_LID_SWITCH_GPIO_LIST to be able to optionally
specify more than one GPIO to check to find out whether the lid is open.
By default, use GPIO_LID_OPEN as before.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:42110
TEST=on Smaug EVT2, define CONFIG_LID_SWITCH_GPIO_LIST as
LID_GPIO(GPIO_LID_OPEN) LID_GPIO(GPIO_BASE_PRES_L) and play with magnets
and the genuine lid, check we get the right "lid open" / "lid close"
messages on the console.
Change-Id: I9e7c67bb39f36f254d31d5861d535d69db754faa
Reviewed-on: https://chromium-review.googlesource.com/287852
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
