We started printing the challenge as
generated challenge:
ABHNDKD4Q7P6KHTKPN9E7...full challenge
instead of
ABHND KD4Q7 P6KHT KPN9E
7FSQX P249S PCP64 LVA8S
W4XCH 7PZX6 FVWN5 QTUSK
U3KBJ HH7RQ SEE5T JX78X
add support for extracting the challenge from both formats.
BUG=none
BRANCH=none
TEST=try to open tot image, 0.4.7 image, and 0.3.4 image
Change-Id: I99a81f1f78284b21777242d27edaa474a0f12367
Signed-off-by: Mary Ruthven <mruthven@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1088130
Commit-Ready: Mary Ruthven <mruthven@chromium.org>
Tested-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Add "arm64" support to Makefile to use crossystem_arch.c
implementation from host/arm/lib directory, in order to avoid
the code duplication.
BUG=None
TEST='emerge-arm64-generic vboot_reference' works correctly
BRANCH=None
Change-Id: I349f8b2055c9be6ebaeb6f322e3b22260465dd5a
Reviewed-on: https://chromium-review.googlesource.com/1082195
Commit-Ready: Adam Kallai <kadam@inf.u-szeged.hu>
Tested-by: Adam Kallai <kadam@inf.u-szeged.hu>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mike Frysinger <vapier@chromium.org>
MT8183 uses a power sequencing inspired from RK3399, with fewer
signals.
We only have 1 signal from PMIC (PMIC_PWR_GOOD), active in S0/S3,
and 1 signal from AP (AP_IN_S3_L), active in S3/S5.
One particularity of this design is that we need to reboot the EC
to RO on every single cold boot/reboot.
For the forced transition to S5, we assert the WATCHDOG signal
to PMIC to shut it down, which should usually work, if the PMIC
was configured properly by AP. If not, we also assert power+home
key (PMIC_EN_ODL) until the PMIC shuts down for good.
BRANCH=none
BUG=b:109850749
TEST=make BOARD=kukui -j
Change-Id: Ibcde8b937d7f4cecb0f470b9a7e0809fc24efae6
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1092402
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Undo some of CL:1072637 so that battery_is_present() and
battery_hw_present() move back to baseboard.
battery_fuel_gauge.c now only includes code which is
directly involved with the fuel gauge.
BUG=b:109894491,b:80299100
BRANCH=none
TEST=make -j buildall
Change-Id: I8fc5be3856564601019d94514dcfc8ffb3071c2e
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1097954
Commit-Ready: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some things were coding errors, other things need to be fsb specific.
Most things here don't seem to matter all that much but better to get
it right.
Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It looks like this hardware has a bug where the display controller
does not work properly when dram is clocked 533MHz and the channels
are configured in non-stacked mode.
The workaround is to select stacked mode in this configuration.
Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There seems to be a hardware bug where the combination of non-stacked
channel settings, both channels populated and 533MHz dram speed cause
the display to be unusable.
The code to actually select stacked mode based on hardware
configuration will be add in a followup patch.
This patch does the following:
* Add option to the sysinfo struct for stacked mode
* Fix programming channel 1 DRB which needs special care for the last
populated rank in stacked mode
TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz)
Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GSMI Set Event Log is taking more than 1K in stack. This causes the
stack to overflow into the adjacent stack. This has the side effect of
causing any CPU waiting for the SMI handler to complete to crash when
the lock is unlocked because the return pointer has been smashed.
BUG=b:80539294
TEST=built on grunt and tested by running `halt` from the OS.
Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27033
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an
output and initialize it high (high = out of reset).
BUG=b:80089559
BRANCH=none
TEST=none
Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of
GPP_D8 as it needs a 3.3v gpio to provide enough power to also
directly power the camera LED.
BUG=b:79667559,b:78122599
BRANCH=none
TEST=none
Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Changed the ordering of the log levels in the documentation to
mate the code
Change-Id: Ief1930b73d833fdf675b039c98046591c0c264c1
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for GLK as it is for APL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E
enable bit. Define POWER_CTL_C1E_MASK to be used subsequently.
Change-Id: I7a5408f6678f56540929b7811764845b6dad1149
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27035
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move generators for the board status report and the kconfig options
report into a common directory and wrap them in a docker container.
Also rework to emit HTML not wiki syntax.
Change-Id: If42e1dd312c5fa4e32f519865e3b551bc471bc72
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of checking each directory in series, kick off the checks
in parallel and then wait for them to finish. Failures print out with
file information, so mixing output isn't a problem. This reduces
the time it takes to run on lumberingbuilder by 60%.
This could probably be sped up even more by splitting up src/mainboard
into smaller sections.
This method does skip a few control files at the top level - .gitignore,
.checkpatch.conf, gnat.adc, etc. These could be added to the list of
files to check, but I didn't think it was needed.
Change-Id: I171977e713a9956cf4142cfc0a199e10040abb35
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/27011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
LPC and eSPI logical device configuration is mostly common.
Create common subroutines for LD configuration. Fix bugs
in LPC LD configuration for ACPI, EMI, Port80. Add work-
around for APL LRESET# changing when LPC clock is not
running.
BRANCH=none
BUG=None
TEST=Build all boards using chip mchp. Test LPC and eSPI
communication with host chipset via EC/Host UART logs.
CQ-DEPEND=CL:1053576,CL:1053827,CL:1053880,CL:1053949
Change-Id: Ie40245c20627178a0e518eafc028d194c1f176a6
Signed-off-by: scott worley <scott.worley@microchip.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1053884
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There is no need to add hardcoded .test suffix when determining the
base RMA key file name.
BRANCH=none
BUG=none
TEST=succeeded signing both prod and pre-pvt images.
Change-Id: I59a5eb4ff8c093110c4d29969974148c99bd62a0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1099731
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The blob includes 65 bytes of the public key and one byte of the key
ID, 66 bytes total.
BRANCH=cr50, cr50-mp
BUG=b:73296606, b:73647182
TEST=none
Change-Id: I0adf844a487776b0a93eae404f7bc74566d003fc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1099730
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Per PCI specification, function 0 must be present,
so functions 1 to 7 can be skipped in this case.
For a device that is not multi-function, it may not
decode function number in the hardware at all. To
avoid registering such a device eight times, skip
scanning functions 1 to 7.
Without the latter fix, a single-function PCI bridge
may call pci_scan_bus() second time and secondary
side devices would get appended second time in the
array devices[]. At that point, quicksort() apparently
hits an infinite recursion loop.
Since pci_scan_bus() is called in part of the early
modules->init() sequence early in main(), the errors
here left coreinfo payload completely silent when
PCI module was built-in on affected system.
Terminal screen was cleared, though.
Change-Id: Ifc6622f050b98afb7196de0cc3a863c4cdfa6c94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With platforms moved to RELOCATABLE_RAMSTAGE, these
overrides no longer have a meaning.
Overrides existed because AGESA ramstage did not fit within
the default 1 MiB of RAMTOP - RAMBASE, when placed low.
Change-Id: I0185875dc550de74877c94f36128d5979e5553d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26813
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
