Edward Hill 36e7c2498c stoney: Rename PGOOD GPIOs ...

Rename stoney power signals for clarity:
SPOK -> S5_PGOOD
VGATE -> S0_PGOOD

BUG=none
BRANCH=none
TEST=power grunt on and off

Change-Id: Iee8307138600c10868981a22971beace2de1ca91
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/978952
Reviewed-by: Justin TerAvest <teravest@chromium.org>

2018-03-26 02:07:27 -07:00

..

apollolake.c

intel_x86: Move chipset reset logic to common code

2018-03-25 00:50:40 -07:00

apollolake.h

power: Group Intel x86 power sequencing common code

2017-01-20 22:40:32 -08:00

braswell.c

kunimitsu: hibernate: enable PseudoG3 support at board level

2016-02-18 17:35:16 -08:00

build.mk

power: create CONFIG_CHIPSET_GEMINILAKE

2018-03-20 14:38:42 -07:00

cannonlake.c

intel_x86: Move chipset reset logic to common code

2018-03-25 00:50:40 -07:00

cannonlake.h

Meowth: Added initial board file.

2017-11-15 20:21:12 -08:00

common.c

debugging: Correcting console channel to chipset instead of switch

2018-03-06 09:59:15 -08:00

ec_driven.c

ryu: add a dummy power module for controlling sensors.

2014-11-18 05:19:47 +00:00

intel_x86.c

intel_x86: Move chipset reset logic to common code

2018-03-25 00:50:40 -07:00

intel_x86.h

intel_x86: Handle RSMRST signal in Intel x86 common code

2017-01-21 10:03:45 -08:00

mediatek.c

cleanup: DECLARE_CONSOLE_COMMAND only needs 4 args

2016-08-24 16:30:10 +00:00

rk3399.c

scarlet: shutdown PP900_S0 power rail when S3

2018-02-09 10:51:29 -08:00

rockchip.c

cleanup: DECLARE_CONSOLE_COMMAND only needs 4 args

2016-08-24 16:30:10 +00:00

skylake.c

intel_x86: Move chipset reset logic to common code

2018-03-25 00:50:40 -07:00

skylake.h

skylake: Add workaround for boards that cannot save reset flags

2017-05-25 12:25:20 -07:00

stoney.c

stoney: Rename PGOOD GPIOs

2018-03-26 02:07:27 -07:00