- changed the pad assignment for plt_rst_l from DIOA13 to DIOM3;
- removed the board property used to keep uart rx disabled, Uart0 is
now enabled by default on Cr50.
- removed resetting fallback counter on USB updates for reef boards,
they are going to use the same mechanism as kevin and gru.
BRANCH=none
BUG=chrome-os-partner:56540
TEST=Tested on Reef Board ID 1 and Gru Board ID 1. Verfied that
plt_rst_l signal is being detected and that there are no
interrupt storms related to not having a pullup resistor on the
uart rx line. Verified that both platforms successfully boot into
chrome OS using cr50 TPM.
Change-Id: I300a0c75e60acbecf93500b46aced303955a192a
Signed-off-by: Scott <scollyer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391140
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
9cd10a5a47