usbpd1 futility image type is deprecated and should not be used for
new designs. This adds proper support for rwsig image type.
Key and signatures are added at linker stage step (futility cannot
directly create such signed images). Thanks to VB21 header, rwsig.c
can now tell how many bytes of the RW image need to be
cryptographically verified, and ensure that the rest is blank (0xff).
BRANCH=none
BUG=chromium:690773
TEST=make BOARD=hammer; flash, RW image is verified correctly.
TEST=make runtests -j
TEST=For the rest of the tests:
Change config option to CONFIG_RWSIG_TYPE_RWSIG
TEST=make BOARD=hammer; flash, hammer still verifies correctly.
TEST=cp build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig;
futility sign --type rwsig --prikey build/hammer/key.vbprik2 \
build/hammer/ec.RW.bin
diff build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig
=> Same file
TEST=Add CONFIG_CMD_FLASH, flashwrite 0x1e000, reboot, EC does
not verify anymore.
TEST=dump_fmap build/hammer/ec.bin shows KEY_RO and SIG_RW at
correct locations.
Change-Id: I50ec828284c2d1eca67fa8cbddaf6f3b06606c82
Reviewed-on: https://chromium-review.googlesource.com/441546
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable CONFIG_USB_PD_TCPC_LOW_POWER, and add cable detection handling.
BRANCH=none
BUG=chrome-os-partner:62964
TEST=on poppy, connect USB-A keyboard to ANX port via A-C adapter:
keyboard works; charging works
Change-Id: I0751cc7b5fc8ba71388f08b7001c0daceda37bb6
Reviewed-on: https://chromium-review.googlesource.com/443747
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit 18327455c1 ("ANX74xx: add TCPC low power mode for different
DRP state") introduced new code to put ANX74xx in low power mode.
However, this broke existing boards that do not enable
CONFIG_USB_PD_TCPC_LOW_POWER (and therefore do not implement cable
detection interrupt).
BUG=chrome-os-partner:59841, chrome-os-partner:61640
BUG=chrome-os-partner:62964
BRANCH=none
TEST=on poppy, connect USB-A keyboard to ANX port via A-C adapter:
keyboard works
Change-Id: I4b66511b816afee402a7e769aa6d2c323724d071
Reviewed-on: https://chromium-review.googlesource.com/443865
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Should be close to the STM32L476 in the STM32L4 family.
Slightly different flash/RAM.
It's currently running from the internal clock (HSI) at 16Mhz,
we need to upgrade to 80Mhz (or 48Mhz if this is fast enough to save us
the PLL locking time).
The internal flash write/erase/protection is still not implemented for
the whole STM32L4 family.
Upgrade the SPI master support and verify that the TX works.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:62893
TEST=make BOARD=eve_fp
run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES)
Change-Id: I87be7d4461aedfbd683ff7bb639c3a6005ee171e
Reviewed-on: https://chromium-review.googlesource.com/442466
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Use the motion sensor to manage ALS as well.
The current interface (via memmap) is preserved, but
we can also access the sensor via cros ec sensor stack and
send the ALS information to ARC++.
BUG=chrome-os-partner:59423
BRANCH=reef
CQ-DEPEND=CL:424217
TEST=Check the sensor is working via ACPI sensor and
cros ec sensor. Check ARC++ sees the sensors.
Change-Id: Iaf608370454ad582691b72b471ea87b511863a78
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/424323
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There are two batteries being evaludated for Eve and there needs to be
a batteery_info struct for each one for situations where the gas gauge
can't be read and the charge state machine uses these parameters.
BUG=chrome-os-partner:62711
BRANCH=none
TEST=Verifed that battery_type is read correctly for both LG and
LISHEN battery units.
On Lishen unit Drain battery completely, then reconnect type C
charger. Verified that battery is now charging. Prior to this CL, the
LISHEN bat would not charge because the internal overcurrent protection
mode would not tolerate the 256 mA precharge current that's specified
for the LG battery.
Tested that both Lishen and LG recovered after forcing a battery
disconnect.
Change-Id: I201eaf61ad03d3dc0d199ab441b07c371bceddde
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/440514
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This change adds an option to pdchipinfo command to force ec to get
the version from the chip instead of the cache (if it's available).
This option will be used after firmware update, which makes the cache
value stale.
BUG=chrome-os-partner:62383
BRANCH=none
TEST=Run ectool as follows:
localhost ~ # /tmp/ectool pdchipinfo 0 on
vendor_id: 0xaaaa
product_id: 0x3429
device_id: 0xad
fw_version: 0x15
localhost ~ # /tmp/ectool pdchipinfo 1 on
EC result 2 (ERROR)
Change-Id: Icefe96d7fc1208b991a4caa13aaf4f04052edba7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441271
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The firmware version formats may vary chip to chip. fw_version field is
changed to a union of a 8 byte string and an 64-bit integer.
BUG=chrome-os-partner:62383
BRANCH=none
TEST=ectool pdchipinfo 0/1 on Electro
Change-Id: Id51e66c44338a09ed897ee61f54cd6a394400e63
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441270
With this change, only DEV images will have the capability to unlock the
Cr50 console.
BUG=chrome-os-partner:62727
BRANCH=None
TEST=Build a prod image, flash Cr50, try to unlock the console. Verify
that access is denied and console remains locked.
TEST=Attempt to read EC and AP flash over ccd. Verify that it fails.
TEST=Remove AC and battery. Plug in AC. Verify that console is still
locked.
TEST=Plug in AC, unplug battery, verify that write protect is disabled.
Verify that console is still locked and cannot be unlocked.
TEST=Build a dev image, verify that console can be locked and unlocked.
Change-Id: Ic47aa34f42ee295e74ba3a40b709ac42c34a30b7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439764
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Make FIFO a stack variable to save static memory,
Remove auto_inc argument, always set
Remove constant for rate 0.
Force board to declare sensor private data.
Avoid name collision in stm_mems_common
Include stm_mems_common.h in accel_lis2dh.h, caller only need to
include accel_lis2dh.h.
BUG=none
BRANCH=none
TEST=Compile with discovery_stmems board.
Change-Id: Id52b54dd4ec3cf217247c5511ad5a506067ad293
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/441144
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: mario tesi <mario.tesi@st.com>
The trackpad interrupt is input only to the EC and should not ever
be driven from here.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build and boot on eve p1
Change-Id: I3ffa2ddb4990550b57c9191b5d721ab0ba206aca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439829
In preparation for adding the rollback protection block, pass
EC_FLASH_PROTECT_RO/ALL_AT_BOOT to flash_[physical_]protect_at_boot,
instead of an enumeration no protection/RO/ALL.
This will later allow us to protect/unprotect the rollback region only,
by adding a EC_FLASH_PROTECT_ROLLBACK_AT_BOOT flag.
BRANCH=none
BUG=chrome-os-partner:61671
TEST=Build hammer with CONFIG_CMD_FLASH command, so that write protection
can be checked with flasherase/flashwrite.
TEST=On hammer (stm32f072):
flashinfo => RO+RW not protected
flashwp true; reboot => only RO protected
flashwp rw; reboot => RO+RW protected
flashwp norw; reboot => only RO protected
TEST=On reef (npcx):
deassert WP, flashwp false; flashinfo => RO+RW not protected
flashwp true => only RO protected
reboot => only RO protected
flashwp rw => RO+RW protected
reboot => only RO protected
Change-Id: Iec96a7377baabc9100fc59de0a31505095a3499f
Reviewed-on: https://chromium-review.googlesource.com/430518
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Poppy uses SPI, Plt_Rst, and USB to AP. Its strapping option is 1M PU
on both DIOA9|DIOA1 which gives it a strap_config value of 0xA.
Rowan uses I2C and it's strapping option is 5k PD on DI0A12 and 5k PU
on DI0A6 which gives it a strap_config value of 0x30.
BRANCH=none
BUG=chrome-os-partner:59833
TEST=manual
Used H1 dev board with external PU/PD resistors to replicate both the
Poppy and Rowan configurations.
With Poppy config console shows:
[0.004468 Valid strap: 0xa properties: 0x45]
With Rowan config console shows:
[0.004460 Valid strap: 0x30 properties: 0x2]
Change-Id: I569960114c6f1844a55912fbf7f3d97008f9f71f
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428000
Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
When --raiden is passed as a command line parameter, do not proceed
programming as if it were not present, alert the user and refuse to
proceed instead.
Need to jump though a couple of extra hoops to avoid printing the
error message twice.
BRANCH=none
BUG=none
TEST=tried running with boards supporting and not supporting
programming over CCD.
$ ./util/flash_ec --board=oak --raiden --image rowan.ec.bin
INFO: Using ec image : rowan.ec.bin
ERROR: raiden mode not supported on oak
$ ./util/flash_ec --board=kevin --raiden --image rowan.ec.bin
INFO: Using ec image : rowan.ec.bin
INFO: Flashing chip npcx_spi.
INFO: Using raiden debug cable.
...
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ia40f348e6dde57fc2f4c49719bc2a0947036dcc1
Reviewed-on: https://chromium-review.googlesource.com/440051
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This removes CONFIG_USB_PD_TCPC_FW_VERSION.
board_print_tcpc_fw_version is removed since it's no longer called.
PD chip info is printed in usb_pd_protocol.c.
BUG=none
BRANCH=none
TEST=buildall. Boot Electro, verify chip info is printed.
Change-Id: I2ff860c2a1b17ceea124644ba8feb356b9cca2eb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/434911
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added code to put the ANX74xx in low power mode for different DRP state.
1. When nothing attached or system is in S3 or S5 disable the auto
toggling and put ANX74xx system in Analog control mode.
2. Using the CABLE_DET interrupt pin (attach event) enable normal power
mode.
BUG=chrome-os-partner:59841, chrome-os-partner:61640
BRANCH=None
TEST=Manually tested on Reef using below dut-control command
dut-control pp3300_pd_a_mw -r <n>
1. S0, S3, S5 - Nothing connected, ANX in low power mode.
2. In S0 SNK (display/USB dongle, eMark cable) connected & put
system to S3, ANX remains in normal mode.
3. In S0 SNK connected & put system to S5, ANX in low power** mode.
4. In S0 nothing connected, put system to S3 or S5, attach
SNK, ANX in low power** mode.
5. Attach SNK at S3/S5 & boot to S0, ANX in normal mode.
6. SRC (AC adapter) with/without eMark cable are detected in
S0, S3, S5, and continue to charge the system after S-state
transition.
low power**: ANX74xx hardware limitation that Ra/Open (Ex: E-Mark cable
only) detection will trigger CABLE_DET continuously, therefore ANX74xx
will go to normal power mode momentarily and then low power mode in a
loop.
Change-Id: I30f7fd7a85e31987fb77e2cab2fe140d59dd3629
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/415580
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Shorten certain long prints and reduce the precision of timestamp prints
when CONFIG_CONSOLE_VERBOSE is undef'd.
BUG=chromium:688743
BRANCH=gru
TEST=On kevin, cold reset the EC, boot to OS, and verify cros_ec.log
contains all data since sysjump and is < 2K bytes (~1500 bytes).
Change-Id: Ia9390867788d0ab3087f827b0296107b4e9d4bca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438932
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
If PD is negotiated and the EC is reset, a source partner port will
continue providing its negotiated voltage (eg. 20V in the case of
zinger). Ensure the partner port is in a known state by providing Rp
for a brief period after resetting to RO.
BUG=chrome-os-partner:62281
BRANCH=Reef
TEST=On kevin, attach zinger, wait for 20V negotiation, and press F3 +
power to cause EC reset. Verify VBUS drops to approximately 0V before
going back to 5V / 20V. Verify the same with kevin OEM charger as well.
Also verify kevin boots with no battery.
Change-Id: I1b769a76188d8a9a515388996fbc4cb3d46840a5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433367
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Electro is able to boot on 15w to Depthcharge but requires 18w or above
to boot to the logon screen. This patch allows 15w charger to boot
Electro to Depthcharge (as before) but prevents it from booting after
that unless the EC in RW negotiates with the charger and gets 18w or
more.
Without the patch:
1. Boot without battery
2. EC sysjumps to RW
3.a. With 18w charger, Depthcharge proceeds to boot
b. With 15w charger, Depthcharge proceeds then browns out
4. Boot without battery
5. Reboot by FSP for RTC well drop
6. Charger goes to disabled state
7. EC fails to negotiate with charger, hard resets charger
8. Brownout
9. Repeat from #4
With the patch:
1. Boot without battery
2. EC sysjumps to RW
3.a. With 18w charger, Depthcharge proceeds to boot
b. With 15w charger, Depthcharge times out and shuts down the system
So, the outcome is same. With the patch, the user at least is (or will
be) given a chance to know battery is the problem. I suppose we have to
add a screen showing battery is drained or dead. I currently see no
such code in vboot_select_and_load_kernel.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=chrome-os-partner:61801
BRANCH=none
TEST=Hack the code to enforce syslock. Disconnect battery.
Use 18w charger to boot the system. Use 15w charger not to boot.
Change-Id: I00d79a96221f1d3b8c6d529de9b8e4588d6112aa
Reviewed-on: https://chromium-review.googlesource.com/440390
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current fast charge assumes only one battery voltage threshold range for
charger profile override. However we have multiple battery voltage
threshold ranges for few batteries hence added a code which can consider
multiple battery threshold ranges and choose respective charge profile.
BUG=chrome-os-partner:62653
BRANCH=none
TEST=Manually tested on Electro. Manipulate smp_cos4870 & sonycorp
battery voltage & temperature ranges and observed correct charge
profile is selected.
Change-Id: Icddc047e608cc8f63cd0c19be716e0f7908ca715
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/438804
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Take in account that sensors are down in S3, reinit them back when
moving from S3 to S0.
Do this only for board version 3 and older. board v4 will have
sensors powered in S3.
BUG=chrome-os-partner:61502
BRANCH=reef
TEST=Check EC power sensors up coming from S3 to S0:
[1.627437 power state 6 = S3->S0, in 0x00cf]
[1.627994 Port 80: 0x1001][1.628600 chipset -> S0]
[1.637391 TCPC p1 Low Power Mode]
[1.645020 Lid Accel: Done Init type:0x0 range:2]
[1.647733 Lid Accel ODR: 10000 - roundup 1 from config 1 [AP 0]]
[1.649015 TCPC p1 Low Power Mode]
[1.662231 TCPC p1 Low Power Mode]
[1.670560 Base Accel: MS Done Init type:0x0 range:2]
C0 st15
[1.679813 PB task 6 = released]
[1.680783 PB PCH pwrbtn=HIGH]
[1.681108 PB task 0 = idle, wait -1]
[1.683463 Base Accel ODR: 10000 - roundup 1 from config 1 [AP 0]]
[1.686275 Base Gyro: MS Done Init type:0x1 range:1000]
[1.697973 Base Gyro ODR: 0 - roundup 0 from config 0 [AP 0]]
[1.776627 Base Mag: MS Done Init type:0x2 range:2048]
[1.786490 Base Mag ODR: 0 - roundup 0 from config 0 [AP 0]]
...
Change-Id: Icb9961a0f3ce1b478c47057716211e6e14c13674
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/428125
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
(cherry picked from commit 37e6fb246495ac972e0bc4ff6fcc16b9bf2eee7b)
Reviewed-on: https://chromium-review.googlesource.com/440511
Commit-Ready: Ravi Chandra Sadineni <ravisadineni@chromium.org>
Tested-by: Ravi Chandra Sadineni <ravisadineni@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
x86 devices use TPM_RST_L to detect the AP state, so we set
device_states[DETECT_AP].detect to GPIO_TPM_RST_L on those boards.
board_update_device_state uses this signal to poll the AP state once a
second to detect if the device is off.
If for some reason TPM_RST_L is deasserted, but the tpm reset handler
has not yet set the state to 'on', we will catch it when we poll the AP
state with board_update_device_state. It will call device_state_on with
TPM_RST_L. In that case device_state_on used to silently disable the
TPM_RST_L interrupt and not change the AP state. This change modifies
device_state_on to notify the tpm reset handler and prevent it from
disabling the tpm reset interrupt.
BUG=chrome-os-partner:62748
BRANCH=none
TEST=disable the deferred_tpm_rst_isr call in
configure_board_specific_gpios. Close the lid and wait 5 minutes. Open
the lid. Verify cr50 prints "device_state_on: tpm_rst_isr hasn't set the
AP state to 'on'" and the system boots normally.
Change-Id: I6e5b722fab6e7b0acb91dda0e5207e4411e97363
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439816
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a host command to get PD chip info.
For PS8751, tcpci_get_chip_info will fail if the chip is in
low power mode. It can be woken up by reading a random register
first then wait for 10ms.
This code doesn't have the wake-up read to avoid 10ms delay.
Instead, we call this function immediately after the chip is
initialized because it'll gurantee the chip is awake.
Once it's called, the chip info will be stored in cache, which
can be accessed by tcpc_get_chip_info without worrying about
chip states.
localhost ~ # ectool pdchipinfo 0
vendor_id: 0xaaaa
product_id: 0x3429
device_id: 0xad
fw_version: 0x15
localhost ~ # ectool pdchipinfo 1
vendor_id: 0x1da0
product_id: 0x8751
device_id: 0x1
fw_version: 0x37
BUG=chrome-os-partner:62383
BRANCH=none
TEST=ectool pdchipinfo 0/1. make buildall
Change-Id: I3f1667d00ce1826936d90882ada1df6ed6b0ea37
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433166
This commit changes the Cr50 write protect behaviour to simply follow
the state of the battery present pin. The state can still be overridden
both ways by using the `wp` console command. A user can either force
write protect enabled or force write protect disabled. Additionally,
the behaviour can be reset to follow the state of the battery pin by
issuing `wp follow_batt_pres`. However, the ability to force the write
protect state requires an unlocked console.
BUG=chrome-os-partner:62726
BRANCH=None
TEST=Plug in battery, verify that WP is enabled. Plug in AC and unplug
battery, verify that WP is disabled.
TEST=Unplug battery, unplug AC, plug in AC, verify that WP is disabled.
TEST=Unplug battery, verify that WP is disabled. Use `wp' command to
enable WP, verify that it is enabled.
TEST=Plug in battery, disable WP using `wp` command, put cr50 into deep
sleep, wake it up, verify that WP is still disabled.
TEST=Plug in AC, plug in battery, disable WP using `wp` command, unplug
and plug battery connector, verify that WP is still disabled.
Change-Id: I83d9820067800801ddbde311eab0853c3c2216d3
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/439485
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
In case there is a sudden power loss to PCH, then there are no eSPI VW
messages sent from the PCH to EC indicating power state transition into
S5. Instead, the eSPI compatibility spec defines such events as global
reset events. For global reset events, eSPI_Reset# signal is asserted
without SLP_SUS# being asserted. This acts as an indication to the EC
that there was a global reset event.
Add a callback chipset_handle_espi_reset_assert that takes any necessary
action whenever eSPI_Reset# pin is asserted. On skylake, it would check
if power button was being pressed and release the button.
BUG=chrome-os-partner:62014
BRANCH=None
TEST=Verified that apshutdown works as expected.
Change-Id: I409afa0d00faca55ae3aa577743cedac58d4d877
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438935
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
After configuring tpm_rst_l to be connected to the correct pin, check
the level of GPIO_TPM_RST_L to make sure we did not miss the rising
edge. If we did then call the tpm reset handler
BUG=chrome-os-partner:62748
BRANCH=none
TEST=verify electro boots, close the lid, wait 5 minutes, open the lid
and verify it still boots
Change-Id: I1a229fa53664767f0e5cad5f80285f5f030f2197
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439879
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The loss between PS8751 and Type-C connector is large and requires
a larger EQ and low squelch threshold for compensation.
- USB Type-c connector facing receiver equalization setting:
Compensate for channel loss up to 10.9dB
- High Speed Signal Detector threshold adjustment: -25%
BUG=chrome-os-partner:61101
BRANCH=none
TEST=Boot & charge
Change-Id: Ie74e2d0b8ad7206f5e60fb013613c382980c0eac
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/433846
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The ap uart tx signal is disconnected if servo is attached, but it is
never reconnected when servo is detached. The 'ccd uart enable' command
only reconnects the EC uart tx signal, so if servo is detached the only
way to reenable ap uart tx is to detach and reattach suzyq. This can
cause cr50 to lose some ccd state.
This change reconnects the ap uart when servo is detached.
BUG=none
BRANCH=none
TEST=manual
disconnect servo
attach suzyq
verify the ap console is read write
attach servo
verify the ap console is read only
detach servo
verify the ap console is read write
Change-Id: I11cdd932b14d968ec77b18adf93dd0d3808fb2e9
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439704
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Without this, keyboard columns 10 and 11 do not work, as registers
for port F are never set.
Let's also remove port D, since we do not use it as part of the
keyboard scanning.
BRANCH=none
BUG=chrome-os-partner:62751
TEST=flash hammer, all keys work.
Change-Id: I0c07dc2420d7cd570ad8450c76f91a2bad9a50a5
Reviewed-on: https://chromium-review.googlesource.com/439908
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add driver for acc sensor ST lis2dh/lis2dh12
Support interrupt management for FIFO watermark
Starting to share common code with other devices
like lsm6dsm/lsm6dsl (acc/gyro) or new lis2mdl (mag)
TODO: Add all embedded functions support (click,
tap and so on)
BUG=none
BRANCH=master
TEST=Tested on discovery BOARD with sensor connected on
EC i2c master bus. Added motion sense task on discovery
board task list, added gpio info in board configuration
file and tested with motion sense console commands. Data
for acc seems ok: can successfully change ODR and
full scale range. Also FIFO and interrupt tested
Device tested is lis2dh (lis2dh12 simply differs for low
pin count but share the same registers)
Change-Id: I16abeac3f139a604094b38d8d8b857a62c93a242
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/412700
Commit-Ready: mario tesi <mario.tesi@st.com>
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
