After talking with Simon Glass about this we concluded that this was an
optimization that is not needed, as such, and since it is only used in
one location and only available from one chip family I'm removing it.
This further simplifies the GPIO API and removes more uses of port/mask
pairs.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I40754a385e0a4fa3a56d67fca1dd59fc8f3cc85a
Reviewed-on: https://chromium-review.googlesource.com/323827
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The new gpio_reset function simplifies the pattern used in this code,
that of returning a GPIO to its original configured state. It also
removes a few instances of using port/mask pairs.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I6e411aaf2f0fbc18aca0ed8742c400a0efe5690d
Reviewed-on: https://chromium-review.googlesource.com/324059
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In rare case, executing i2c_interrupt function will generate unnecessary
START condition if START bit is 1 in SMBCTL1.
Please see the layout of SMBCTL1 register below.
Bit [7] - STASTRE
Bit [6] - NMINTE
Bit [5] - GCMEN
Bit [4] - ACK
Bit [3] - EOBINTE
Bit [2] - INTEN
Bit [1] - STOP
Bit [0] - START
In order to set or clear bits of INTEN and NMINTE, we need to read SMBCTL1,
or the bit2,6 and write back to register. But we will issue unnecessary
START condition if bit 0 is 1. (ie. Start condition is not sent yet)
Then FW will receive unexpected SDAST interrupt and sometime it collapses
state machine when i2c receives NACK condition.
The solution is enabling these two bits in i2c_init_bus function. Using
task_enalble/disable_irq (NVIC register) to enable or disable i2c interrupts
instead.
Modified sources:
1. i2c.c: Fixed the bug of i2c caused by writing START bit in SMBCTL1.
2. i2c.c: Add more debug messages for unexpected bus state.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I37dbb0e5b61f4a5ba12f0638535f8031522c1711
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322883
Reviewed-by: Randall Spangler <rspangler@chromium.org>
1. The previous EC2I module does not meet section
'7.17.5 EC2I Programming Guide'. We need to correct it to prevent
conflict with H2RAM (LPC I/O cycles 800h ~ 9ffh) which cause LPC keeps
long wait states.
NOTE:
If EC is using EC2I internal bus to access PNPCFG registers while host
accessing EC ram through H2RAM interface at the same time,
the symptom will appear.
2. Remove 'CONFIG_IT83XX_PNPCFG_HOST_ACCESS'.
We don't allow the host access PNPCFG registers.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. To use console command 'rwreg' to r/w PNPCFG registers and
there is no error code return.
2. To create a stress test for this change.
- EC use 'ec2i_read()' and 'ec2i_write()' to access PNPCFG
registers per-10ms.
- run ectool 'version' command per-100ms.
Before the change was made, LPC will keep in long wait states
immediately.
After the change, we run the test of ectool 'version' command
over 20000 times.
Change-Id: I84e86fc17ef624d4a60a1a051bc301ebdf56a3da
Reviewed-on: https://chromium-review.googlesource.com/323563
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Convert some uses of gpio_set_flags_by_mask to plain gpio_set_flags.
The result is usually more readable due to being able to use the
GPIO_* enum names, and it removes more instances of port/mask
implementation details leaking outside the gpio.c chip specific code.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I06a7ad8a53e553a8e432a6abb5b38c25a98df6c6
Reviewed-on: https://chromium-review.googlesource.com/323815
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds a temporary secure storage interface for the EC to be able
to store small amounts of data from the host that is locked until the
chipset resets. This is used by pre-memory verified boot on x86 systems
where we need to know which RW slot to boot and what the hash is to
ensure that we can resume from S3 safely.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados and samus
Change-Id: I5fa91046437479bcae69a8fca4c989b0ef554bbf
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315222
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
There are hooks for chipset power sequencing but not one to indicate
that the system has reset at runtime. Add a hook for this and
implement for lm4 and mec1322. The hook is notified on any platform
reset, including those that happen on the way into S3/S5 state.
There is a new config variable added because the hook is notified in
the interrupt handler and needs a deferrable function that needs to
be added to every board.
BUG=chrome-os-partner:46049
BRANCH=none
TEST=tested on glados and samus
Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315221
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good
idea:
- INPUT / PULL_UP is not necessarially the lowest-power state (for
example, if there is an onboard pull-down).
- Most GPIOs should already be in lowest-power state when we're in S5.
- For the few GPIOs that need to be in a different state for hibernate,
we can use a board-level callback.
In addition, remove mec1322 code related to restoring from hibernate
state, since we always reset coming out of hibernate.
BUG=chrome-os-partner:49608
BRANCH=glados, strago
TEST=`hibernate` on chell console when in S5 and AC removed. Verify that
EC power is roughly equivalent to low-power idle power. Attach Zinger,
verify that device wakes and boots, and charges from charger.
Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322937
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
the third_party tpm library, part 2.
This is a continuation of commit 5496242945 ("Move platform
independent stub calls back to the third_party tpm library.")
and moves _cpri__EccGetCurveCount() over to third_party/tpm2.
TEST=compilation succeeds
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
CQ-DEPEND=CL:323416
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I03fa2125060cdef013e403e37414e4a559f29617
Reviewed-on: https://chromium-review.googlesource.com/323352
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
If we are doing a cold reset or if Deep S5 is disabled we will go into S5
and need to be able to power up again, but we do not have enough information
to know what direction the sequencing may go from S5 (to G3 or up to S0).
So limit the RTCRST check to just the explicit G3->S5 path and let the normal
checking of SLP_S4 signal happen otherwise.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=pass FAFT testing finally
Change-Id: I202234e58281e6b007ad2b98396994222d0831b2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/323087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since battery pin 5 is the voltage across internal 10Kohm
thermistor and is not either 0V or 3.3V, typically 330mV
with external 100Kohm.
Using GPIO configuration to detect this pin causes extra
power consumption and this pin is reconfigured as ADC.
BUG=cros-bug-49610
BRANCH=glados
TEST=check if battery is detected. Use 'adc' console command
and check if it shows 'BATTPRES' with volatage in mV.
Change-Id: I907b94629b0581a6a27e6f0cecda12ddef09a4f0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/322771
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
The power state machine goes through POWER_S5 state both when
sequencing up and down, but we only should check for it to
time out on the way up. In order to know what direction it
is going add a variable to indicate the direction.
On samus where this was done before it did not go through
POWER_S5 on the way down, instead going directly to POWER_S5G3
so I did not run into this same issue.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=successfully power down without the EC thinking it is
timing out and trying to reset RTC.
Change-Id: I1f53f3a252bdc2ec8c656e30b3de7f98aaa661a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322898
Reviewed-by: Shawn N <shawnn@chromium.org>
Each pair of protect bits locks 4K, so for parts with 64K flash, don't
bother checking STM32_OPTB_WRP23.
BUG=chrome-os-partner:49354
TEST=Run flashrom to protect PD MCU (see repro steps on linked crbug),
reboot and verify system boots into dev mode with all_at_boot and
all_now protect flags set on PD MCU.
BRANCH=glados
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic375d97c30bfd68940350641c44d5535b0402a2f
Reviewed-on: https://chromium-review.googlesource.com/322823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
To reduce the boot & resume time in EC, set the power button
debounce time to zero in PMIC PBCONFIG Register.
BRANCH=glados
BUG=None
TEST=Put the device in S3. Press the power button and observe
SLP_SUS_S3 is getting released 30ms earlier than the previous
configuration
Change-Id: I184fa056b9b6aed1bcccae9f38eaff3f3bb4e2bb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/321341
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the device is discharging, but has a battery percentage greater
than 97 show a solid green LED.
BUG=chrome-os-partner:48661
BRANCH=none
TEST=make BOARD=lucid
Change-Id: Ia5c0946fbc47e37a295db3419a0edf925aacf484
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322738
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable CONFIG_BOARD_HAS_RTC_RESET and add a board_rtc_reset() function
to assert RTCRST to the PCH that will be called if the board fails to
sequence out of the S5 state.
This does not do anything on EVT devices but will be present in DVT.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell
Change-Id: If0be091349a7ef7e8e1335ade029570c5f97a30e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322725
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to pulse RTC reset to the PCH when power sequencing exit fails we
need to watch for SLP_S4 to deassert and if it does not then assert RTCRST
using a board specific method. This is attempted up to 5 times before giving
up and staying in G3.
On skylake the RSMRST passthru needs to be honored when the task is woken up,
so while waiting call handle_rsmrst() if woken up early. This is needed
because it is RSMRST that actually tells the PCH to try and wake.
This is all wrapped in a config option and board specific method because not all
boards have a GPIO to control RTCRST and if they do they may not all use the
same method to assert it.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell EVT:
First, ensure board sequences properly if everything is OK for a normal boot.
Next, modify handle_rsmrst() to not pass through the signal in order to
simulate being stuck in S5, and ensure that the EC attempts to assert RTCRST
and power up again 5 times before giving up and staying in G3.
Change-Id: Ia3c13069c92762b51beb682a19e5a074194a3c26
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322724
Reviewed-by: Shawn N <shawnn@chromium.org>
We found the deviation of 115200 UART baud-rate is too large when core
clock is 16 or 12MHz. It causes failure during FAFT since sometime EC
could not receive correct commands to proceed test. We adjusted core
clock from 16/12 to 15/13 to reduce the deviation of 115200. Both of
them have run FAFT and stress tests for weeks and no UART issues were
found.
Since the lowest source clock of i2c is 6.5MHz, we modified tSCLL, tSCLH
and hold time directly for better i2c timing when freq is 400K. And if
freq is 100K, we introduced normal mode to handle it.
Modified sources:
1. clock.c: Adjust core clock from 16/12 MHz to 15/13 MHz.
2. clock_chip.h: Set target core clock as 15 MHz.
3. uart.c: Add baud-rate support for 15/13 MHz.
4. register.h: Add new register definitions of SMBus.
5. i2c.c: Modified tSCLL, tSCLH and hold time directly for better i2c
timing.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ie5d22e87875c064b49338046c99a178f8fadf32b
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/322320
Reviewed-by: Shawn N <shawnn@chromium.org>
If we're asked to compute a hash of an image on a region of storage, we
may find that the region actually contains no image. In that case, we
need to compute a hash of zero bytes. Properly handle this case from
image size detection to hash computation to hash invalidation.
BUG=chrome-os-partner:49529
TEST=Manual on chell. `dd conv=notrunc if=/dev/zero of=ec.bin bs=131072
count=1`, then write ec.bin and verify SW sync occurs, RW hash is
computed correctly, and the system boots into dev mode.
BRANCH=glados, strago
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie5a023d13d2521f9c224615666950aea8fbc22bb
Reviewed-on: https://chromium-review.googlesource.com/322750
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously there were only two uses of gpio_config_pins, one was
gpio_config_module, which passed in GPIO_CONFIG_ALL_PORTS (the only
place this is used), the other was the common I2C code when it needs to
return the SDA and SCL lines to their alternate function after unwedging
the bus.
These uses are so different that it doesn't make much sense to keep a
single API for them. This change adds a gpio_config_pin that is
simpler to use as it just takes a gpio_signal enum to select the GPIO
to configure and makes gpio_config_pins and GPIO_CONFIG_ALL_PORTS
internal to gpio.c
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I92bfb0b520b0aa2165655b2ff5076e428c88631f
Reviewed-on: https://chromium-review.googlesource.com/322437
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When a sysjump host command is received, there is a (usually) small
period of time when the EC has sent a reply packet back to the host, but
interrupts are still enabled. If the host sends a new host command,
STATUS_PROCESSING will be set by the EC ISR, but the host command will
never be handled due to pending sysjump. In this case, STATUS_PROCESSING
will still be set, so we need to clear it on LPC post-sysjump re-init.
BUG=chrome-os-partner:49318
TEST=Add 200ms msleep before call to interrupt_disable() in
jump_to_image(), boot to software sync, and verify host commands are
handled successfully post-sysjump and system continues to boot.
BRANCH=glados, cyan
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id0878df738541f7d5d158821a68988a8e6dc6759
Reviewed-on: https://chromium-review.googlesource.com/322431
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
As proposed by e.lam@cirro.nl, update the number of USB interface in the
descriptor when we are in 'sink mode' : the vendor interface for the
sniffer endpoint is not exported in this mode, so we have only one
interface.
This should the Windows USB driver used by libusb/Zadig.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chromium:570287
TEST=./board/twinkie/build_rw_variant
Change-Id: I5948643d552030481a52adb8c0937a42e7ae8ae1
Reviewed-on: https://chromium-review.googlesource.com/322371
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
the third_party tpm library.
Some files in the third_party TPM2 source are
omitted from compilation (e.g. CpriHash.c) as they
contain platform dependent code. Subsequently all
the functions necessary for compilation were moved
to stubs.c. However, some of these functions are
platform independent, and should remain in the
third_party implementation.
The corresponding change CL:321375 adds such functions
to third_party/tpm.
TEST=compilation succeeds
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
CQ-DEPEND=CL:321375
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I6a41085332c94dcbe7ecfdeceea0a7015e4ac693
Reviewed-on: https://chromium-review.googlesource.com/321930
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Previously the flash test used the GPIO string name to identify the
write protect GPIO. Change to use the GPIO signal enum. This is faster
and removes a use of gpio_list.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I4203c33cfa6d2b25d73d886b5248857a0c271565
Reviewed-on: https://chromium-review.googlesource.com/321913
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The GPIOs were set incorrectly in EVT so invert them in the EC
so we can keep an incrementing board version.
BUG=chrome-os-partner:49357
BRANCH=glados
TEST=test that 'version' reports 1 for EVT board instead of 4
Change-Id: I520c3e09c7c3f0797b46807932f859aa490ac4c7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321929
Reviewed-by: Shawn N <shawnn@chromium.org>
Use a static buffer rather than 256 bytes of stack when scanning for the
end of an image.
BUG=chrome-os-partner:49396
TEST=Verify "ectool echash abort; ectool echash start 0xfffffffe 100"
doesn't panic on glados.
BRANCH=glados
Change-Id: Ia864fe77134533bce079dab3b253142b14410ded
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322283
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
If no charger connected, battery LED blinks when battery is
low/critical; and it should stop blinking once system is in
S5/G3.
BUG=chrome-os-partner:48718
BRANCH=none
TEST=Verified on Kunimitsu when OS shutdown system due to
critical battery and enter S5/G3, battery LED stops blinking.
Change-Id: I9349a9938a548ce675999579f749bd5dae3c399f
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/321794
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb
and npcx_evb_arm.
For better power consumption, we disable ADC, tri-state spi pins, all inputs
of wake-ups to prevent leakage current caused by input floating and set
necessary GPIOs' states in hibernate function.
Modified drivers:
1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate.
2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate.
3. wheatley/board.c: Add hibernate_wake_pins array for hibernate.
4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting
GPIOs' status related to board for better power consumption.
5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt
will disable before it is called.
6. register.h: Add WKINEN definition and declarations used for hibernate.
7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs'
state and wake-up inputs before entering hibernate.
8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field.
9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/321466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
flash_ec is used for both ec chips accessed over servo, and
standalone stm32 devices. It's not necessary to have a servo
conencted to update the standalone devices over usb.
This is useful for servo v4 and servo micro.
BUG=chromium:571477
TEST=Verify servo micro/discovery can be flashed without servo v2.
BRANCH=none
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I9deee1616d93feeac4d6675bc3a4f573d4906f7b
Reviewed-on: https://chromium-review.googlesource.com/321925
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@google.com>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
There is no indication that PMIC is ready for communication
EC should check i2c response from PMIC first before initializing
rest of registers.
BUG=None
BRANCH=master
TEST=check if there is message, "PMIC init failed", in EC log.
Change-Id: Ic790edf3639acfb2b5357e2638c88dc8d59bebf0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/319631
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Updated the permissions of ec_uart_pty to match the permissions of the
other PTYs.
BUG=None
BRANCH=None
TEST=cros_workon hdctools ec-devutils, run servod, ls -l on ec_uart_pty
from dut-control, verify that permissions are 666.
Change-Id: I71c72645c5a435fea562084185b80ff6d31652b4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321371
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Includes support for encrypt / decrypt,
and sign / verify; padding schemes OAEP /
PKCS1; supporting bignum library.
RSA key sizes must be a multiple of 32-bits
(with the top bit set). Keying material,
input and output buffers are required to be
word-aligned.
BRANCH=none
TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316942
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This commit adds support for the EC-3PO interpreter to disconnect and
reconnect to the EC UART. This is handy so that other tools that need
to use the raw UART directly can do so without interference from
EC-3PO.
BUG=chromium:571170
BRANCH=None
TEST=For both enhanced and non-enhanced EC images, issue disconnect
command and verify that no debug prints were emitted and no commands
were sent to the EC. Then issue reconnect and verify that the console
works as normal and that no commands were buffered.
TEST=./util/ec3po/run_tests.sh
Change-Id: Ic572e25d24d5e45fbe2eeb84a534235c4ec98d38
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321084
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If a user had already run util/ec3po/run_tests.sh, and then never
modified any ec3po files, the presubmit check would list every file in
the EC repo that was newer since the the last run. This included
files such as build artifacts.
BUG=chromium:575032
BRANCH=None
TEST=Run ./util/ec3po/run_tests.sh once. Run make -j buildall, try to
upload and verify that no nag message to run ec3po tests is presented.
TEST=Touch an ec3po file, try to upload, verify that nag message about
running ec3po unit tests is presented.
Change-Id: I4f09bb76dcd85b570b57030197f4887bed85f1a7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321134
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Replace Makefile with real link file in order to build sources in board folder.
Modified drivers:
1. Makefile: change file type to link file
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Iba80166369869d661c8f6da989e3bc1c586047e7
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320901
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
if CONFIG_USB_PD_TCPM_VBUS is enabled, a race condition may happen:
In function pd_set_input_current_limit() and typec_set_input_current_limit(),
EC may notify AP power change event before PD send the up-to-date
POWER_STATUS TCPC alert to EC. It will cause the AP get the stale power
status. Move the power change event notification to board_set_charge_limit(),
it will be called after EC receives POWER_STATUS TCPC alert, and sending
power change event notification only if the "charge limit" or "charge port"
or supplier is changed.
BUG=chrome-os-partner:48801
BRANCH=none
TEST=make buildall -j; Tested on Oak by plug/unplug AC adapter to
type-C ports and verify the UI battery icon shows the correct status
instantly.
Change-Id: I52f0e268fdebc45e609d843847540ae48cd0a9eb
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/320066
Reviewed-by: Rong Chang <rongchang@chromium.org>
