Convert some uses of gpio_set_flags_by_mask to plain gpio_set_flags.
The result is usually more readable due to being able to use the
GPIO_* enum names, and it removes more instances of port/mask
implementation details leaking outside the gpio.c chip specific code.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I06a7ad8a53e553a8e432a6abb5b38c25a98df6c6
Reviewed-on: https://chromium-review.googlesource.com/323815
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good
idea:
- INPUT / PULL_UP is not necessarially the lowest-power state (for
example, if there is an onboard pull-down).
- Most GPIOs should already be in lowest-power state when we're in S5.
- For the few GPIOs that need to be in a different state for hibernate,
we can use a board-level callback.
In addition, remove mec1322 code related to restoring from hibernate
state, since we always reset coming out of hibernate.
BUG=chrome-os-partner:49608
BRANCH=glados, strago
TEST=`hibernate` on chell console when in S5 and AC removed. Verify that
EC power is roughly equivalent to low-power idle power. Attach Zinger,
verify that device wakes and boots, and charges from charger.
Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322937
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
the third_party tpm library, part 2.
This is a continuation of commit 5496242945 ("Move platform
independent stub calls back to the third_party tpm library.")
and moves _cpri__EccGetCurveCount() over to third_party/tpm2.
TEST=compilation succeeds
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
CQ-DEPEND=CL:323416
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I03fa2125060cdef013e403e37414e4a559f29617
Reviewed-on: https://chromium-review.googlesource.com/323352
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Since battery pin 5 is the voltage across internal 10Kohm
thermistor and is not either 0V or 3.3V, typically 330mV
with external 100Kohm.
Using GPIO configuration to detect this pin causes extra
power consumption and this pin is reconfigured as ADC.
BUG=cros-bug-49610
BRANCH=glados
TEST=check if battery is detected. Use 'adc' console command
and check if it shows 'BATTPRES' with volatage in mV.
Change-Id: I907b94629b0581a6a27e6f0cecda12ddef09a4f0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/322771
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
To reduce the boot & resume time in EC, set the power button
debounce time to zero in PMIC PBCONFIG Register.
BRANCH=glados
BUG=None
TEST=Put the device in S3. Press the power button and observe
SLP_SUS_S3 is getting released 30ms earlier than the previous
configuration
Change-Id: I184fa056b9b6aed1bcccae9f38eaff3f3bb4e2bb
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/321341
Commit-Ready: Kevin K Wong <kevin.k.wong@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the device is discharging, but has a battery percentage greater
than 97 show a solid green LED.
BUG=chrome-os-partner:48661
BRANCH=none
TEST=make BOARD=lucid
Change-Id: Ia5c0946fbc47e37a295db3419a0edf925aacf484
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322738
Reviewed-by: Shawn N <shawnn@chromium.org>
Enable CONFIG_BOARD_HAS_RTC_RESET and add a board_rtc_reset() function
to assert RTCRST to the PCH that will be called if the board fails to
sequence out of the S5 state.
This does not do anything on EVT devices but will be present in DVT.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell
Change-Id: If0be091349a7ef7e8e1335ade029570c5f97a30e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322725
Reviewed-by: Shawn N <shawnn@chromium.org>
As proposed by e.lam@cirro.nl, update the number of USB interface in the
descriptor when we are in 'sink mode' : the vendor interface for the
sniffer endpoint is not exported in this mode, so we have only one
interface.
This should the Windows USB driver used by libusb/Zadig.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chromium:570287
TEST=./board/twinkie/build_rw_variant
Change-Id: I5948643d552030481a52adb8c0937a42e7ae8ae1
Reviewed-on: https://chromium-review.googlesource.com/322371
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
the third_party tpm library.
Some files in the third_party TPM2 source are
omitted from compilation (e.g. CpriHash.c) as they
contain platform dependent code. Subsequently all
the functions necessary for compilation were moved
to stubs.c. However, some of these functions are
platform independent, and should remain in the
third_party implementation.
The corresponding change CL:321375 adds such functions
to third_party/tpm.
TEST=compilation succeeds
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
CQ-DEPEND=CL:321375
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I6a41085332c94dcbe7ecfdeceea0a7015e4ac693
Reviewed-on: https://chromium-review.googlesource.com/321930
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The GPIOs were set incorrectly in EVT so invert them in the EC
so we can keep an incrementing board version.
BUG=chrome-os-partner:49357
BRANCH=glados
TEST=test that 'version' reports 1 for EVT board instead of 4
Change-Id: I520c3e09c7c3f0797b46807932f859aa490ac4c7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321929
Reviewed-by: Shawn N <shawnn@chromium.org>
If no charger connected, battery LED blinks when battery is
low/critical; and it should stop blinking once system is in
S5/G3.
BUG=chrome-os-partner:48718
BRANCH=none
TEST=Verified on Kunimitsu when OS shutdown system due to
critical battery and enter S5/G3, battery LED stops blinking.
Change-Id: I9349a9938a548ce675999579f749bd5dae3c399f
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/321794
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb
and npcx_evb_arm.
For better power consumption, we disable ADC, tri-state spi pins, all inputs
of wake-ups to prevent leakage current caused by input floating and set
necessary GPIOs' states in hibernate function.
Modified drivers:
1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate.
2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate.
3. wheatley/board.c: Add hibernate_wake_pins array for hibernate.
4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting
GPIOs' status related to board for better power consumption.
5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt
will disable before it is called.
6. register.h: Add WKINEN definition and declarations used for hibernate.
7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs'
state and wake-up inputs before entering hibernate.
8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field.
9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/321466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
There is no indication that PMIC is ready for communication
EC should check i2c response from PMIC first before initializing
rest of registers.
BUG=None
BRANCH=master
TEST=check if there is message, "PMIC init failed", in EC log.
Change-Id: Ic790edf3639acfb2b5357e2638c88dc8d59bebf0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/319631
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Includes support for encrypt / decrypt,
and sign / verify; padding schemes OAEP /
PKCS1; supporting bignum library.
RSA key sizes must be a multiple of 32-bits
(with the top bit set). Keying material,
input and output buffers are required to be
word-aligned.
BRANCH=none
TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316942
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Replace Makefile with real link file in order to build sources in board folder.
Modified drivers:
1. Makefile: change file type to link file
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Iba80166369869d661c8f6da989e3bc1c586047e7
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320901
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
if CONFIG_USB_PD_TCPM_VBUS is enabled, a race condition may happen:
In function pd_set_input_current_limit() and typec_set_input_current_limit(),
EC may notify AP power change event before PD send the up-to-date
POWER_STATUS TCPC alert to EC. It will cause the AP get the stale power
status. Move the power change event notification to board_set_charge_limit(),
it will be called after EC receives POWER_STATUS TCPC alert, and sending
power change event notification only if the "charge limit" or "charge port"
or supplier is changed.
BUG=chrome-os-partner:48801
BRANCH=none
TEST=make buildall -j; Tested on Oak by plug/unplug AC adapter to
type-C ports and verify the UI battery icon shows the correct status
instantly.
Change-Id: I52f0e268fdebc45e609d843847540ae48cd0a9eb
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/320066
Reviewed-by: Rong Chang <rongchang@chromium.org>
For TCPMs with an off chip TCPC, PD MCU host event status can be handled
in a common way. When a status flag is updated (ex. from
charge_manager), notify the AP through the host event, and save the
status flag for later retrieval.
BUG=chrome-os-partner:49124
BRANCH=None
TEST=Verify `cat /sys/class/power_supply/CROS_USB_PD_CHARGER1/online` on
chell reflects the actual online status of the charger. Also verify UI
charge icon tracks the online status correctly.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I63bc70205627474590e38ffd282faedaea3bcc66
Reviewed-on: https://chromium-review.googlesource.com/320796
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In order to support rpm mode, we use a TICK function (fan_tick_func) to
monitor tacho value and adjust PWM duty. In this version, fan driver always
enables clock source of MFT to make sure it can present real-time tacho value.
For better performance, the feedback value to adjust PWM duty is various.
We also change fan & pwm settings for SUNUN 4-pins pwm-type fan.
Modified drivers:
1. npcx_evb/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
2. npcx_evb_arm/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
3. fan_chip.h: Remove unnecessary default_count field of mft_t structure
4. fan.c: Add support for rpm mode
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I25e7bd2f3f726b40fd4e0d9a1049a4d82bbd830d
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320510
Reviewed-by: Randall Spangler <rspangler@chromium.org>
x86 systems will auto-power-on when power is applied to the EC. When
the battery level is critically low, power-on is prevented, except when
the system is unlocked. So, when unlocked, some systems will
auto-power-on regardless of battery level, overcurrent the charger /
battery, and then repeat forever.
Prevent this reboot loop by ignoring auto-power-up when the battery is
critically low, regardless of system unlocked status.
BUG=chrome-os-partner:48339
TEST=Verify power-up is prevented on no-battery chell w/ donette. Then,
run 'powerbtn' on EC console and verify system powers on (and
overcurrents).
BRANCH=None
Change-Id: Ia631b5a8c45b42ec805e4a0c3f827929a0efd236
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/319187
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Pull floating pins high, don't duplicate external pull ups, and make a
few other minor changes.
BUG=chrome-os-partner:48109
TEST=Verify chell continues to boot and S5 power is reduced to
~5.5 mW.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaee0cc926149dae1f4189e6b9e4f7e3a4da6ba1c
Reviewed-on: https://chromium-review.googlesource.com/319165
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Use custom charging profile to enable charging at a faster rate.
BUG=chrome-os-partner:48662
BRANCH=none
TEST=load on lucid and charge at room temp. Use "chgstate" command to
verify that battery current matches the expected fast charging current
for the given temp range and voltage.
Change-Id: Ie508d29db091593ff2cfda9d135c73f6a3de5a9a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/319493
Commit-Ready: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In 0% battery case, if the charger can provide power at least
15 Watt(CONFIG_CHARGER_LIMIT_POWER_THRESH_CHG_MW), will allow system to
boot up.
BUG=chrome-os-partner:48339
BRANCH=none
TEST=Verified in Kunimitsu system, system with 0% battery can boot up
normally once charger power is 15 Watt.
Change-Id: I0c7b23d4ac1e7bd2807ceeb068fc9018a99a03c4
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/318891
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
1. KSO[0-15] and KSI[0-7] can be used as GPIO input if they are not set for
keyboard scan function.
2. Critical section for gpio_set_level().
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=console commands: gpioset, gpioget, and version.
Change-Id: I8edae122525e6dcebaa3489116642d8e48520569
Reviewed-on: https://chromium-review.googlesource.com/318112
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
stm32f03x and stm32f070 officially do not support an HSI48 clock, so
configure our 48MHz clock using HSI8 and PLL.
BUG=chromium:568717
BRANCH=None
TEST=Verify snoball 1us timer is accurate and we can execute
approximately 48 million NOPs in a second.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347
Reviewed-on: https://chromium-review.googlesource.com/317459
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable the RSA verification of the RW partition,
so we are using the RW partition by default and
the USB PD flashing VDMs are able to update
the firmware over the Control Channel.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:47823
TEST=run the following sequence on a Samus connected to Honeybuns :
ectool --name=cros_pd infopddev 1
ectool --name=cros_pd flashpd 5 1 ec.RW.bin
ectool --name=cros_pd version
and see the honeybuns properly updated and running the new version.
Change-Id: I8f1612ee153a412620bae5822d1b354ad8072916
Reviewed-on: https://chromium-review.googlesource.com/312998
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
A typical EC image includes two similar in their functionality
subsections, RO and RW. CR50 has a small RO subsection, all it does -
detects a proper RW image to run and starts it up. To provide for
reliable firmware updates, the CR50 image needs to include two RW
sections, while the code is running from one RW subsection, the other
one can be upgraded.
This patch adds the ability to generate two identical RW sections,
mapped half flash size apart, and include them into the resulting EC
image.
To keep things simple the previously existing RW section's name is not
being changed, while the new (identical) RW section is named RW_B.
Two configuration options need to be defined to enable building of the
new image type: CONFIG_RW_B to enable the feature and
CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the
flash.
A new rule added to Makefile.rules allows to generate a different lds
file from the same source (core/cortex-m/ec.lds.S) by defining a
compile time variable to pick a different base address for the
rewritable section, when RW_B is built.
BRANCH=none
BUG=chromium:43025
TEST=as follows:
- make buildall -j still succeeds
- verified that regular CR50 image starts successfully
- modified chip/g/loader/main.c to launch RW_B first, re-built and
re-run the image, observed on the console:
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
cr50 bootloader, 20151118_11218@80881, no USB, full crypto
Valid image found at 0x00084000, jumping
--- UART initialized after reboot ---
[Reset cause: power-on]
[Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com]
[0.001148 Inits done]
This FPGA image has no USB support
Console is enabled; type HELP for help.
> [0.002212 task 2 waiting for events...]
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
(note that the image base address is 0x840000, which is RW_B).
Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/316703
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If deep sleep S5 is supported RSMRST to the PCH should not be high
when the PCH is in S5 unless the board is sequencing out of deep sleep
and S5 state. Therefore, ensure RSMRST is low when the EC goes into
hibernate. This assumes deep sleep S5 is employed. A more appropriate
fix is to honor RMSRST state prior to going into hibernate state.
Without this change the behavior on certain platforms do not sequence
out of S5 when coming out of hibernate.
BUG=chrome-os-partner:48133
BRANCH=none
TEST=tested on a failing EVT chell board at the factory
Change-Id: Ia4a1cdb59c25a3fc704c64fbe6beb01ede90d777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
two port PD will keep interrupt low, and cause
EC.PDCMD task stuck with exchange status loop before
entering task-while-loop
BUG=chrome-os-partner:48232
BRANCH=lars
TEST=`make BOARD=lars -j`, OS can boot up normally
Change-Id: I493c6d02170c731af430f28abf8ade38b47aff0f
Signed-off-by: Ryan Zhang <Ryan.Zhang@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/315362
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previous HW didn't correctly support 20V charging. The HW has been
corrected and now there is no need to keep 20V mode disabled in FW.
BUG=chrome-os-partner:48217
BRANCH=none
TEST=Tested in the lab by jguerin@ against Samus
Change-Id: I952872affb302c7aa2ddb97466cd5ce459d2ac54
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/315219
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
