The GFX Programmer's Reference Manuals (PRMs) aren't clear on this but
it's pretty clear from the processor datasheets which SKUs expose which
pins: All U/Y processors lack DDI D.
Change-Id: I84c40b6bc01091de8a512e21354243c74643e0f5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use GMA.Setup_Default_FB() to allocate framebuffers in the stolen
memory. To help with setups where we can't unload the i915 driver,
back up and restore the current GTT setup and framebuffer contents.
Also add a wrapper script and update the README.
Change-Id: I10790d35d38b7b211f41b2452f6d2baf17372e31
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20604
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Calling this is necessary for VGA text mode on at least Skylake, where
the legacy VGA registers are inaccessible otherwise.
Change-Id: I48ba1738bcc7babd4e666e5266f775dcd06b2a3f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21323
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>
After reset DPLL_CTRL2 is initialized to 0. Which means some clock
disable bits are not set and might cause some hassle later. Set them
and close the related TODO.
Change-Id: I1a470dff55e317e8119906b3e397f6f2314abcbd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20648
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We initialize the timeout variable before the first event on the other
side (i.e. us sending a request to PCODE). With very slow debug output
sending the request itself might take longer than the timeout period.
Reorder the code to check the timeout condition only after the first
try and thereby make sure that we always try at least twice. Also issue
a debug message in case we timed out.
Change-Id: I8cdeb3e36d7eafbef8a1a8e13670f3f9838a2f38
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20647
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
First, allow updates to voltage swing too during channel equalization.
Spec just says to adjust the settings as requested.
Second, the loop conditions differ from the clock recovery phase. We
have only 6 tries in total but no particular order is enforced.
Change-Id: I4673390d8c0f9a5642702872e5b4ab11f54797c7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21215
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On DVI-I connectors the DDC is shared between the analog and digital
parts. To decide which path to take we checked the digital input bit
of the EDID. We did this overeagerly for all ports, which broke com-
patibility with DP adapters (the DP realm is very complex and we are
supposed to discover the whole downstream hierarchie, which obviously
would be overkill).
Change-Id: Ifc53e8ab985695e6e4ff1d42659826710a50eae9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20135
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new public procedure Setup_Default_FB() to configure a framebuffer
in stolen memory. The optional parameter `Clear` tells it to clear the
configured framebuffer.
Also remove Setup_Default_GTT() from the public interface.
Change-Id: I6ece4f56bbd34126ef34f0107d5ccdbde8a007ac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20603
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Honor the `Offset` field of the given framebuffer and add preconditions
that ensure we won't overflow the GTT or its target address space.
Change-Id: I6577e98e154610228734baee7674ee54b9a922e8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To be compatible with HW.PCI.Dev implementations that do actual register
accesses, we have to account for hardware state updates.
Change-Id: I86e42163d7847f7011bcf9a0ef5c2c7f25b4b1be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21207
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Adrian-Ken Rueegsegger <ken@codelabs.ch>
Remove `MMIO_Base` option from Initialize() and try to derive it
using libhwbase' PCI mechanism instead.
Change-Id: Iacd4d098954bb96c1c6b40fdfb2636191d9517c7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20600
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a configuration option to override the default HDMI translation.
It's not exported yet, as we've never seen a non-default value being
used. So this is just to have a common place for the defaults.
Also sets the recommended default value for Broxton as defined in the
PRM.
Change-Id: I59fae0fb4f444d9193a98b6a0edf337ecbba3b62
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20165
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This simple program scans all ports and configures pipes for the first
three available displays. It presumes that there is enough framebuffer
mapped for all pipes and fills it with test images.
The only command line parameter ist the path to a PCI-device node in
sysfs. On exit, the hardware is left in the configured state. So the
user has to make sure, that he either can work without the gfx hard-
ware or has another driver to restore a working state.
Change-Id: I2144300589e113e711db7959aa68fa96c3844568
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18786
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Using the same type (Pos64) as in the actual calculation below, helps
current SPARK Pro to prove absence of overflows (SPARK GPL 2016 still
works too ofc).
Change-Id: Ifde556f9201f3333be0eb8566bf69b7f9df11277
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18809
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add new configuration flags for Broxton and hook up its DDI_Phy
implementation in the shared Haswell DDI code. Haswell and Skylake
get DDI_Phy stubs.
Tested (in Linux userspace) on ASRock J3455-ITX which exposes the
following ports:
o VGA through an active eDP to VGA converter chip
o HDMI 2.0 through an active DP to HDMI converter chip
o DVI-D connected to the SoC
Change-Id: If72b228c6a4c45487261e6e7435d281ec2d97f38
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18426
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Other than for the DDIs of the Core processor series, we don't select
signal levels from a preconfigured set but have to program the indivi-
dual values.
Change-Id: I3ab4d5e2ed47db0d4ce47a17c4a5fb08b5416bc2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18425
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
PLL parameter selection is a much simplified version of what's done in
i915 on Linux. We just assume the error in the resulting clock of a
valid parameter tuple is always small enough. Trying to speak mathe-
matically, since the only calculated parameter M2 is given as a frac-
tion of 2^22, the error should stay below 2^-22.
As the PLLs are tied to specific DDI ports, they won't ever be shared
among ports and the allocation boils down to just configuring the PLL.
Change-Id: I206675506f1dbbb57d65bfdc308de1891ccbf61a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18423
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
DDI PHYs is a concept common to current Atom processor series. It
seems the PHYs are implemented on the same die as the graphics core
but still need to be configured separately. Based on the assumption
that we start with disabled PHYs and it was always us if they are
enabled, we only have to do a small share of what Linux' i915 does.
v2: Wait for GRC done only if we want to copy its results.
Change-Id: I1e59f80daa08dc64b8c3dff34202ace5dd4c5f73
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18422
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
It's close to the respective code for Skylake but still different
enough for a separate implementation. We start with a default CDClk
of 288MHz which is enough for resolutions up to 2560x1600.
Change-Id: I44364191236f421b2b89c9a019a50713f7c20525
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18243
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Current plan is to support all DDI outputs of Apollo Lake. This
includes one eDP (DDI A) and two fully fledged DDIs (B, C) that can
be either configured to DP 1.2 or HDMI 1.4. MIPI/DSI outputs won't
be supported for now.
Since there doesn't exist any public documentation, the code will be
solely based on analysis of Linux' i915 driver.
Everything is a stub. In the existing code, at least DDI configu-
ration will also have to be adapted.
v2: Escape hash characters in config file
Change-Id: I4a79d4531d238049ba00ab4f03e270e6b58f81ab
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18421
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The corresponding bits in PCH_ADPA reflect the current state of the
connection and not a change in the state. This was interpreted wrong
since some PRMs state that these bits can be cleared. It seems they
can't be, though. Linux' i915 also doesn't try to clear them and only
interprets their state as presence of a display.
Change-Id: I8e8bfd30937f393e5c411b7d48668a4f5f7b0129
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18167
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>
This is useful when we only want to probe for connected displays while
another entity currently controls the outputs.
Also introduce an `All_Ports` list, that can be used when it's unknown
which ports are actually implemented (the default now, when no port
list is provided to `Scan_Ports()`).
Change-Id: I5d8e289a907fe99c673084afbce54da65ba98e9c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18123
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For cold plugging, we don't wait for a hot-plug event. But, even if we
are not supposed to wait for a hot-plug event, we have to clear any
pending event. Also, a failed DP training can result in another hot-plug
event.
A stale event would be spuriously interpreted as a disconnect, resul-
ting in an infinite loop of cycling the pipe on and off.
Change-Id: I4c7bbe0ac792553c94e928ba0a5eeb822a857f9c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18122
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
To support arbitrary configuration changes, we have to disable all
changed pipes first before we enable any new outputs.
Currently if an output moved from one pipe to another we might have
enabled it twice on different pipes.
Change-Id: Ibf601b8b5044aff4dd9e0a9c15cec20db6907aa5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18120
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Checking for hotplug events should be done before any other work to
reduce load and (spurious) debug output. Therefor, use the simpler
`Port_Type` in the interface of `Hotplug_Detect()` so we don't have to
fill the whole `Port_Cfg` before checking for events.
Also, now that it's possible, factor the disabling of a single output
out of `Update_Outputs()`.
Change-Id: I2a0ba5530c8d511fa95f9cac12297ad428a40d77
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18119
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The only time these settings are referenced is when we are about to
tear down a pipe. But we don't need the current state to do this. On
retraining due to a hotplug event, we start the whole configuration
again for simplicity. So we won't need it on that path either.
Change-Id: I01662e4a4a6150a0b05c57a016171fa3f0e7b93a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18117
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Shuffle things around to let the caller decide when to output the
settings. This removes spurious "DP" outputs for FDI configuration
which reuses the DP_Info infrastructure.
Change-Id: I9e6d6946002ef758b6c31f7de797dc6d329cae74
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18116
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
