This prints all the boards that are part of the build. This will be
used on coreboot's build system for running coverity. This allows
the builds to keep in sync as platforms are added, and as anything is
added to the "skip_boards" list.
for board in $(make showboards); do
make proj-$board CROSS_COMPILE="arm-eabi-"
done
BUG=none
BRANCH=none
TEST=make showboards shows boards, and excludes skip_boards list
Change-Id: I34d8bc95cc5c7d05b4f2ec38b16b75f9f0c72c6f
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/403498
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
BRANCH=none
util/ectool.c:1158 merror: taking address of packed member 'size' of class
or structure 'ec_params_usb_pd_fw_update' may result in an unaligned
pointer value [-Werror,-Waddress-of-packed-member]
For this case, the pointer is always aligned but clang complains.
Workaround using double pointer casts to char and uint.
uint32_t *data = &(p->size) + 1;
BUG=chromium:665240
TEST=Builds now
Change-Id: Ibccf0f6e409b9724fc9e5acf28dde570e9d341e3
Reviewed-on: https://chromium-review.googlesource.com/411384
Commit-Ready: Manoj Gupta <manojgupta@chromium.org>
Tested-by: Manoj Gupta <manojgupta@chromium.org>
Reviewed-by: Yunlian Jiang <yunlian@chromium.org>
Keep the pull-up enabled all the time on the GPIO connected to the load
switch enable pin.
This is not ideal but the pull-up bit is no-op in output mode on npcx
and this avoids glitching the enable when transition from the 3A mode
(output strong one) to the 1.5A mode (input with a weak pull-up).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=gru
BUG=chrome-os-partner:59679
TEST=on Kevin, plug a USB key on port 0, then plug another USB device on
port 1 and see that the key on port 0 is no longer
disconnecting/re-enumerating.
Change-Id: I075dacb1549239f1b60763659dac006f5b838e2c
Reviewed-on: https://chromium-review.googlesource.com/411220
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: David Schneider <dnschneid@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 16ab6c66c957832c5943f4750dd1970355a697e1)
Reviewed-on: https://chromium-review.googlesource.com/411760
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
We don't use the hid endpoint and any work we do now to get it to
suspend would probably need to be done again when adding the full
functionality. This change removes the hid endpoint entirely.
BUG=chrome-os-partner:57726
BRANCH=none
TEST='cat /sys/bus/usb/devices/1-7/power/runtime_status' shows the
device is suspended
Change-Id: Id948fb02cf1a8ab605a35d028c563c2f78b91a64
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/411531
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear
the wake masks when the SMI is invoked. For S0ix, EC sets and clears
the wake mask via this patch.
These functions are directly invoked from the state machine transition
states. During S0ix entry, the wake mask for lid open is enabled.
During S0ix exit, the wake mask for lid open is cleared. All pending
events are also cleared.
BRANCH=none
BUG=chrome-os-partner:58740
TEST=test lidopen in S0ix
Change-Id: I398fdba2b9bba1f6caef46f8dc71c7de3b669d08
Signed-off-by: Archana Patni <archana.patni@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401070
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Some functions are only defined if CONFIG_HOSTCMD_EVENTS is set,
leading to link-time failures.
In particular, do not call these functions from keyboard_scan,
and do not define PD host event commands if the configuration
option is not set.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make buildall -j
Change-Id: I0da31cdec08f86f148aa883698a44f462de46d8e
Reviewed-on: https://chromium-review.googlesource.com/410923
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since the ec binaries are so tight on space, it would be nice to be
able to see just how much changes are affecting the size. This allows
users to easily do before/after comparisons.
Sample output:
build/sweetberry/RW/ec.RW.flat shrank by 44 bytes: (43828 to 43784)
build/twinkie/RO/ec.RO.flat shrank by 64 bytes: (46312 to 46248)
build/twinkie/RW/ec.RW.flat shrank by 40 bytes: (45900 to 45860)
build/wheatley/RW/ec.RW.flat shrank by 40 bytes: (102692 to 102652)
Compared 156 of 156 files.
81 files changed.
Total size change: -3100 bytes.
Average size change: -38 bytes.
BRANCH=none
BUG=none
TEST=make clobber buildall -j; make savesizes
[change some code that changes file sizes]
make clobber buildall -j ; make newsizes
[Shows size differences]
Change-Id: I48b440063eb6eb6c00900af3d0dfa075be6f9ec7
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410860
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
To keep things simple it has been decided to use a certain key ID bit
as an indication of a prod versus dev key type.
The key ID value is derived from the key value, and is easy to enforce
(by generating another key in case the value does not match the
required key type).
This information will also be available through the cr50 userspace
tool.
BRANCH=none
BUG=chrome-os-partner:58230
TEST=ran the new code on prod and dev devices; On prod:
> sysinfo
Reset flags: 0x00000800 (hard)
Chip: g cr50 B2
RO keyid: 0x3716ee6b(dev)
RW keyid: 0xb93d6539(dev)
DEV_ID: 0x015bb2a9 0x04656742
on dev:
> sysinfo
Reset flags: 0x00000800 (hard)
Chip: g cr50 B2
RO keyid: 0xaa66150f(prod)
RW keyid: 0xde88588d(prod)
DEV_ID: 0x0180305d 0x04656742
Change-Id: I37b12e02eb62f4f86bb58468ee301e77446451da
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410291
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The `idlestats` command was not behind the CONFIG_CMD_IDLE_STATS option;
this commit fixes that.
BUG=None
BRANCH=glados
TEST=build a board that uses mec1322. Undef CONFIG_CMD_IDLE_STATS;
verify that the command isn't present in the build.
Change-Id: Id17c8377f812ee2a63dc4507766c1c557704dcb1
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/411518
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This add basics for acc and gyro sensor ST lsm6dsm
Still need to add interrupt management for embedded
functions and FIFO
BUG=none
BRANCH=master
TEST=Tested on discovery BOARD with sensor connected on
EC i2c master bus. Added motion sense task on discovery
board task list, added gpio info in board configuration
file and tested with motion sense console commands. Data
for acc/gyro seems ok, can successfully change ODR and
full scale range for acc and gyro.
Change-Id: Ie50c8c0ee366994ed97f7ff3252633893b813ac2
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/406947
Commit-Ready: mario tesi <mario.tesi@st.com>
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Chrome seems to pay attention to the tablet mode switch reported by the
EC. However, for some devices that don't actually have a switch and use
the lid angle as a "virtual" switch, it's possible for invalid tablet
mode change events to be reported. This is because a single reading
could flip the switch.
This commit adds some debouncing to the tablet mode event changes.
Instead of having a single event be able to change the tablet mode
switch, we will now perform TABLET_MODE_DEBOUNCE_COUNT number of
calculations of the new tablet mode value. If those calculations all
agree, then we'll flip the switch. This should help mitigate false
tablet mode change events caused by spurious forces.
BUG=chrome-os-partner:59203
BUG=chrome-os-partner:59480
BRANCH=gru
TEST=flash kevin; open lid to pi/2 rad; rotate device counter-clockwise
pi/2 rad; shake device and verify that tablet mode doesn't change
easily.
TEST=verify that tablet mode still works.
Change-Id: Id020f7db28e93e53b276b3f0d28a40251f035f0b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/410942
Commit-Ready: Gwendal Grignou <gwendal@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
This change removes the uart disable in rdd_disconnect. It used to be
necessary because we used to disable device state detection in
rdd_disconnect. Without device state detect we had to disable the AP and
EC uart to make sure there were no interrupt storms. Now we keep device
state detection running all the time. It handles enabling/disabling the
AP and EC uart when it senses the RX signals aren't pulled up.
UART is only enabled/disabled when cr50 detects that the AP or EC state
changed from off to on or on to off. If the debug cable is detached and
then reattched the uart will be disabled on detach, but it won't be
reenabled until the AP/EC are rebooted.
BUG=chrome-os-partner:58222
BRANCH=none
TEST=Detach and reattach suzyq without rebooting the AP or EC and make
sure both consoles come back after reattaching the cable.
Change-Id: Id104e12dc533e8d7047f32aebd41abd1c959d267
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410269
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Enable fast charging profile config (CONFIG_CHARGER_PROFILE_OVERRIDE)
so that the battery desired current & voltage can be selected for given
rated performance values.
BUG=chrome-os-partner:59779
BRANCH=none
TEST=Manually overrode the temperature and voltage. Observed correct
charge profile config is selected for each tests.
Change-Id: I080a3ace6d2f77bb6b97911b7705a44ec563258b
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/410824
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
PD alternate mode is covered in tcpc interface. So tcpci_tcpm_init()
doesn't reset HPD. If keeping HDMI/DP type-C cable connected, doing
sysjump sets HPD signal to high while it's already high(this high comes
from previous state), then OS doesn't output to HDMI/DP monitor.
BUG=None
BRANCH=none
TEST=make buildall
Change-Id: Ic3bc75b1e5579816d8c1b294fe2eb65a20e3eae3
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/409751
Commit-Ready: Keith Tzeng <keith.tzeng@quantatw.com>
Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Added battery charging profile settings as given in the datasheet.
BUG=chrome-os-partner:58553
BRANCH=none
TEST=Manually verified on reef. VBAT is equal to battery voltage.
Previous/current Charge status is equal to the conditions given
in the datasheet.
Change-Id: Ie04619a122fe52d6768c03ff5156b368e3f2d340
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/398080
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This changes the usb descriptor to set the MaxPower to 0mA instead of
500mA.
BUG=chrome-os-partner:59564
BRANCH=none
TEST=Verify 'lsusb -vd 18d1:5014 | grep MaxPower' shows the power is 0mA
Change-Id: Ieeb8dec6c205f4fe51392f8106b3a0ed7d3ea0a5
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/410288
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
This allows custom TPM commands to be declared using the a
DECLARE_VENDOR_COMMAND macro instead of the original (and still
unchanged) DECLARE_EXTENSION_COMMAND macro.
The new commands are nearly identical, but they are encapsulated
using the vendor-specific protocols described in the TPMv2 spec.
Our original extensions use a non-standard command code, and
return a non-standard struct on completion, which can be
confusing to standard TPM drivers and tools.
Demonstrating the use of the new macros, this adds commands to
obtain the state of the Cr50 restricted console lock, or to set
the lock. There is intentionally no command to unlock the
console.
Note that this CL just adds the commands to the Cr50. We still
need to provide a nice userspace utility for the AP to use.
BUG=chrome-os-partner:58230
BUG=chrome-os-partner:57940
BRANCH=none
TEST=make buildall; load, boot, test, and update again on Reef
On Reef, I can use the trunks_send tool to send the raw TPM bytes
to invoke these commands:
Get the lock state:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000D00000000001000
The last byte 00 indicates that the lock is NOT set, so set it:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000C000000000011
Success. On the Cr50 console, I see it take effect:
[480.080444 The console is locked]
Query the state again:
# trunks_send 80 01 00 00 00 0C 20 00 00 00 00 10
80010000000D00000000001001
and now the last byte 01 indicates that the console is locked.
And of course the existing extension commands still work as
before. In addition to uploading firmware, I can use the
usb_updater from my build machine to query the running firmware
version:
$ ./extra/usb_updater/usb_updater -f
open_device 18d1:5014
found interface 4 endpoint 5, chunk_len 64
READY
-------
start
Target running protocol version 5
Offsets: backup RO at 0x40000, backup RW at 0x4000
Keyids: RO 0x3716ee6b, RW 0xb93d6539
Current versions:
RO 0.0.10
RW 0.0.9
$
Change-Id: I7fb1d888bf808c2ef0b2b07c782e926063cc2cc4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409692
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890
BRANCH=none
TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption
Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/399882
Reviewed-by: David Hendricks <dhendrix@chromium.org>
If PS8751 goes into low power mode during sysjump, then tcpm_init will
fail since PS8751 is not accessible via I2C, so force it to wake up
during hook_init.
BUG=chrome-os-partner:59693
BRANCH=none
TEST=Verified PS8751 port on reef is functional after sysjump.
Change-Id: I2aa5a80b2ea9c17a01e4cba04493f83cb0a39955
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/410132
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Various cryptographic operations leak timing
information if comparisons are not executed
in constant time. This change adds DCRYPTO_equals(),
a constant runtime comparator.
Also replace crypto related callsites that used
memcmp() as a binary comparator.
BUG=none
BRANCH=none
TEST=tcg tests pass
Change-Id: I3d3da3c0524c3a349d60675902d1f2d338ad455f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/410163
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The firmware provision job running in the lab calls the flash_ec
script with the --chip parameter, instead of the --board parameter.
So only check if the board name is in the raiden list if it is a
non-empty board.
BRANCH=none
BUG=chrome-os-partner:58039
TEST=Manually triggered the flash_ec command:
$ flash_ec --chip=npcx_spi --image=${IMAGE} --port=9999 --raiden
Change-Id: I25fef906d93803a94c544f7699ce494a84c46bd8
Reviewed-on: https://chromium-review.googlesource.com/410162
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
CTS task wakes up A and C then goes to sleep:
CTS -> A, C -> A -> B -> C
Since C has a higher priority, C should run first. This should result
in C running one more time than A (or B).
BUG=chromium:663873
BRANCH=none
TEST=cts.py -m task
Change-Id: I89c733ba3aab09b293edf8583d6ed73791531e59
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409535
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Task A wakes up B and goes to sleep. Task B wakes up C then goes to
sleep. Task C wakes up A then goes to sleep. This is repeated
repeat_count times:
A -> B -> C -> A -> ...
It's expected all tasks to run exactly repeat_count times. Tick task
runs to inject some irregularity.
BUG=chromium:663873
BRANCH=none
TEST=cts.py -m task
Change-Id: Ib7227f05f09b7a49f8528aff6e6e8d3e6df93ba7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409534
Reviewed-by: Randall Spangler <rspangler@chromium.org>
These keys are much quicker to verify (259ms to 51ms on a -M0 at
48 Mhz), so they can be used when timing is critical and
verification needs to be performed on the board.
BRANCH=none
BUG=chromium:663631
TEST=make buildall -j && make run-rsa
TEST=make run-rsa3 (next commit)
Change-Id: I0da4b3e21543bb6f7b18e8b6ddc5e153046a61b8
Reviewed-on: https://chromium-review.googlesource.com/408006
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When bus obfuscation is enabled we have the chance of doing a security
reset when resuming from sleep. Since we cannot disable bus obfuscation
on current boards, we need to disable sleep.
BUG=chrome-os-partner:57994
BRANCH=none
TEST=make buildall
Change-Id: I6f49278a9b41c1d15c646838044e34f03b979479
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409576
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When kernel get EC_HOST_EVENT_PD_MCU event and query power state, we may
not done refresh here. Delay EC_HOST_EVENT_PD_MCU event to avoid this
race.
BUG=chrome-os-partner:59499
BRANCH=gru
TEST=Manual on kevin, check power state correct after unplug charger
Change-Id: Ib88acf5a39c2780c6e40144ccebfba17cf84f77c
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/408131
Commit-Ready: Douglas Anderson <dianders@chromium.org>
Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a nested interrupt test to eCTS. Higher priority IRQ is fired,
followed by lower priority IRQ. Handlers should be executed
sequentially.
P1 *-----*
/ \
P2 / *-----*
/ \
task_cts ----* *----
B C A D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m interrupt; make buildall
Change-Id: Ia9f1bf4205cefe8bdc11cc0aa3ad2057359b73ef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/409611
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add a nested interrupt test to eCTS. Lower priority IRQ is fired,
followed by higher priority IRQ. Handler executions should be nested.
P1 *-----*
/ \
P2 *----* *----*
/ \
task_cts ----* *----
A B C D
BUG=chromium:653195
BRANCH=none
TEST=cts.py -m gpio, interrupt, timer; make buildall
Change-Id: I34dc7b4e819051b9070a11e69d13d6be704f2e5f
Reviewed-on: https://chromium-review.googlesource.com/408797
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
