The CONFIG_FLASH_NVMEM option implements persistent, reliable storage
regions in flash. This adds CONFIG_FLASH_NVMEM_VARS, which uses one of
those storage regions for free-form variables.
Refer to the comments in include/nvmem_vars.h and common/nvmem_vars.c
for usage and implementation details.
BUG=chrome-os-partner:61107
BRANCH=none
TEST=make runtests
This CL includes a number of new tests, specifically for this feature.
No target boards use this feature yet so there's nothing to test on
actual hardware, but the test/nvmem_vars executable includes console
commands ("get", "set", "print") to try it out.
Change-Id: I8597415dc3b00a1462f5b164eeb5073129030525
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414194
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Modified the SPI NOR flash driver to implement
and expose a read JEDEC ID command as well as
support block (64KiB) erase operations.
BUG=None
BRANCH=None
TEST=Built all targets. Tested on two different EEPROMs.
Before:
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0x1940ef
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 4m0.440s
user 0m6.674s
sys 0m11.998s
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0xc21a20c2
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 5m57.291s
user 0m9.964s
sys 0m18.363s
-------------------------------------------
After:
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0x1940ef
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 1m33.176s
user 0m2.327s
sys 0m5.050s
-------------------------------------------
$ ~/haven_updater$ ./read_jedec_ftdi
[+] JEDEC_ID=0xc21a20c2
$ ~/haven_updater$ time ./chip_erase_ftdi
[+] Success!
real 2m41.923s
user 0m4.191s
sys 0m8.576s
-------------------------------------------
Change-Id: Ic20372ca9966499977a52a700d6492d3f648d7b2
Signed-off-by: Nadim Taha <ntaha@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/416903
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Common code is more flexible and supports more parts, so delete the
npcx-only register translation code.
BUG=chrome-os-partner:60029
BRANCH=gru
TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28
gets written to SR1, which matches our desired 'protect botton 128KB',
according to the datasheet. Also run 'flashrom -p ec --erase' then read
back EC SPI contents, verify ROM is erased except for first 128KB
region.
Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413228
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365)
Reviewed-on: https://chromium-review.googlesource.com/415498
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
On the bd9995*, back boosting may occur when actual battery voltage
drops below VBAT register setting. Maintain the VBAT register at the
battery-requested charge voltage even when not charging to ensure the
bd9995* doesn't become a back boosted animal.
BUG=chrome-os-partner:56139,chrome-os-partner:54248
BRANCH=gru
TEST=Manual on kevin, unplug AC, run 'charger', verify that 'V_batt' is
maintained at 8688 mV. Attach charger, verify 'V_batt' stays at 8688 mV
and device charges.
Change-Id: Ia0cc7f9279cb460e20a8faf332ad432067dc5482
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400087
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
This reverts commit c459c8278e
as the fix is not straightforwad, some host command codes in
private repos are expressed using C preprecessor which
breaks the assumption of this patch that all host commands
are expressed as four digit hex numbers.
Change-Id: I922de9ae8dbab6eef048463c5c09b1f338152083
Reviewed-on: https://chromium-review.googlesource.com/414492
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chrome-os-partner:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
100bca94 R __hcmds
100bca94 R __host_cmd_0x0000
100bcaa0 R __host_cmd_0x0001
100bcaac R __host_cmd_0x0002
100bcab8 R __host_cmd_0x0003
100bcac4 R __host_cmd_0x0004
100bcad0 R __host_cmd_0x0005
100bcadc R __host_cmd_0x0006
100bcae8 R __host_cmd_0x0007
100bcaf4 R __host_cmd_0x0008
100bcb00 R __host_cmd_0x0009
100bcb0c R __host_cmd_0x000a
100bcb18 R __host_cmd_0x000b
100bcb24 R __host_cmd_0x000d
100bcb30 R __host_cmd_0x0010
100bcb3c R __host_cmd_0x0011
100bcb48 R __host_cmd_0x0012
100bcb54 R __host_cmd_0x0013
100bcb60 R __host_cmd_0x0015
100bcb6c R __host_cmd_0x0016
100bcb78 R __host_cmd_0x0017
100bcb84 R __host_cmd_0x0025
100bcb90 R __host_cmd_0x0026
100bcb9c R __host_cmd_0x0029
100bcba8 R __host_cmd_0x002a
100bcbb4 R __host_cmd_0x002b
100bcbc0 R __host_cmd_0x002c
100bcbcc R __host_cmd_0x0044
100bcbd8 R __host_cmd_0x0045
100bcbe4 R __host_cmd_0x0046
100bcbf0 R __host_cmd_0x0047
100bcbfc R __host_cmd_0x0061
100bcc08 R __host_cmd_0x0062
100bcc14 R __host_cmd_0x0064
100bcc20 R __host_cmd_0x0065
100bcc2c R __host_cmd_0x0067
100bcc38 R __host_cmd_0x0087
100bcc44 R __host_cmd_0x008c
100bcc50 R __host_cmd_0x008d
100bcc5c R __host_cmd_0x008f
100bcc68 R __host_cmd_0x0092
100bcc74 R __host_cmd_0x0093
100bcc80 R __host_cmd_0x0096
100bcc8c R __host_cmd_0x0097
100bcc98 R __host_cmd_0x0098
100bcca4 R __host_cmd_0x0099
100bccb0 R __host_cmd_0x009e
100bccbc R __host_cmd_0x00a0
100bccc8 R __host_cmd_0x00a1
100bccd4 R __host_cmd_0x00a8
100bcce0 R __host_cmd_0x00a9
100bccec R __host_cmd_0x00b6
100bccf8 R __host_cmd_0x00b7
100bcd04 R __host_cmd_0x00d2
100bcd10 R __host_cmd_0x00d3
100bcd1c R __host_cmd_0x00db
100bcd28 R __host_cmd_0x0101
100bcd34 R __host_cmd_0x0102
100bcd40 R __host_cmd_0x0103
100bcd4c R __host_cmd_0x0104
100bcd58 R __host_cmd_0x0110
100bcd64 R __host_cmd_0x0111
100bcd70 R __host_cmd_0x0112
100bcd7c R __host_cmd_0x0113
100bcd88 R __host_cmd_0x0114
100bcd94 R __host_cmd_0x0115
100bcda0 R __host_cmd_0x0116
100bcdac R __host_cmd_0x0117
100bcdb8 R __host_cmd_0x0118
100bcdc4 R __host_cmd_0x011a
100bcdd0 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX
100bcdd0 R __hcmds_end
BRANCH=none
Change-Id: Ideb9951b318763f71915e2c4e5052f4b4bfab173
Reviewed-on: https://chromium-review.googlesource.com/405528
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This describes a 5-finger touchpad. The physical/logical dimensions
of the trackpad are hardcoded for the time being.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
Change-Id: I04a0833a28c013395974104ebdd6fcb29e5d6680
Reviewed-on: https://chromium-review.googlesource.com/407742
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Charger BGATE is off on POR hence the voltage to the battery pack is
not applied immediately from the VBUS. To overcome this issue, BGATE
is turned on (CHG_EN) at charger initialization. If the voltage across
VBATT is high but I2C is still failing, battery is booting from ship
mode hence overwrite the battery as not present till I2C on battery
is success and INIT bit is set.
BUG=chrome-os-partner:59308
BRANCH=none
TEST=Reef can boot to OS from shipmode battery.
Change-Id: If1b212612e27fd65a822675a9609f0a8c03d8add
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/411360
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
In the future, we'd like to have different HID devices on different
endpoints (keyboard, trackpad, etc.), so we'd like to separate the
keyboard handling.
For other chip implementing usb_hid.c (namely, chip/g), we, for now
just rename the config option and endpoint/interface definitions.
Making the code more generic can be done at a later stage.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make buildall -j
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
Change-Id: Iad1b00fa226f7635c0f34aae6a435dc53a3ea555
Reviewed-on: https://chromium-review.googlesource.com/409256
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This add basics for acc and gyro sensor ST lsm6dsm
Still need to add interrupt management for embedded
functions and FIFO
BUG=none
BRANCH=master
TEST=Tested on discovery BOARD with sensor connected on
EC i2c master bus. Added motion sense task on discovery
board task list, added gpio info in board configuration
file and tested with motion sense console commands. Data
for acc/gyro seems ok, can successfully change ODR and
full scale range for acc and gyro.
Change-Id: Ie50c8c0ee366994ed97f7ff3252633893b813ac2
Signed-off-by: Mario Tesi <mario.tesi@st.com>
Reviewed-on: https://chromium-review.googlesource.com/406947
Commit-Ready: mario tesi <mario.tesi@st.com>
Tested-by: mario tesi <mario.tesi@st.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
BUG=chrome-os-partner:55158,chrome-os-partner:55889,chrome-os-partner:55890
BRANCH=none
TEST=on reef use ina (pp3300_pd_a_mw) to check tcpc power consumption
Change-Id: I5a2904f4e549b7da22242848bb3b1887331ecadd
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/399882
Reviewed-by: David Hendricks <dhendrix@chromium.org>
These keys are much quicker to verify (259ms to 51ms on a -M0 at
48 Mhz), so they can be used when timing is critical and
verification needs to be performed on the board.
BRANCH=none
BUG=chromium:663631
TEST=make buildall -j && make run-rsa
TEST=make run-rsa3 (next commit)
Change-Id: I0da4b3e21543bb6f7b18e8b6ddc5e153046a61b8
Reviewed-on: https://chromium-review.googlesource.com/408006
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Simple API to set/get the tablet mode. It can be set via lid angle
calculation or if a board has a dedicated HAL sensor/GPIO.
Merged from glados branch, add MKBP switch support.
BUG=chromium:606718
BRANCH=gru
TEST=Check with Cave that both mode works.
Reviewed-on: https://chromium-review.googlesource.com/402089
Reviewed-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit c940f36ceabcf2425284001298f03ebdb4c3079e)
Change-Id: I2ee5130f3e0a1307ec3ea543f7a32d66bc32b31d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/404915
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
BUG=chrome-os-partner:54668
BRANCH=none
TEST=Verified SNK is detected in S0 (toggle on), S3 (toggle off),
and S5 (force sink). SRC is detect in S0 only, stays detected when
entered S3, but unplug/plug while in S3 will not re-detect until
system back in S0. When go to S5, SRC will get disconnected until
back in S0, and hotplug SRC in S5 will not get detected. Checked
power role swap with another chromebook in the above scenario also.
Change-Id: I2a487fca5cb04c45524aa3efde84fcd10ff0579e
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/396918
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This board function allows workarounds to be applied to a board after all
power rails are up but before the AP is out of reset.
Most workarounds for power sequencing can go in board init hooks, but for
devices where the power sequencing is driven by external PMIC the EC may
not get interrupts in time to handle workarounds.
For x86 platforms and boards which support RSMRST# passthrough this board
callback will allow workarounds to be applied despite the PMIC sequencing
by ensuring that the function is executed before RSMRST# deassertion.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=test IMVP8 workaround on multiple eve boards
Change-Id: I0569494084000a4b1738ee18aafce5c96900dc4b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/402591
Reviewed-by: Shawn N <shawnn@chromium.org>
Add the default undefined state for CONFIG_ESPI and rename
CONFIG_VW_SIGNALS to CONFIG_ESPI_VW_SIGNALS.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=pass presubmit checks
Change-Id: I45242d545915c16bb46f751532a01ab937cee5f0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400032
Reviewed-by: Shawn N <shawnn@chromium.org>
The host command parameter and response buffers should be explicitly
aligned by the LPC/SPI/I2C drivers. But the host command handlers don't
know that, and the structs are all __packed, so the compiler generates
horribly inefficient ARM Cortex-M code to cope with unaligned accesses.
Add __ec_align{1,2,4} to force the param / response structs to be
aligned. Use it in a few structs now which were straightforward to
test. It should be added to more structs as space is needed, but that
would make this change unwieldy to review and test.
Add CONFIG_HOSTCMD_ALIGNED to enable the additional alignment.
Currently, this is enabled only for LM4 and samus_pd, so that EC code
can be tested without affecting other non-samus ToT development (none of
which uses LM4).
Fix the two handlers that weren't actually aligned (despite one of
them having comments to the contrary).
Also, add a CHROMIUM_EC define that can be used to determine if a file
is being compiled for an EC target. We need that so that we only force
structure alignment for EC binaries. On the AP side, buffers may not be
aligned, so we should not force alignment.
BUG=chromium:647727
BRANCH=none
TEST=Flash samus and samus_pd. Boot samus and run a bunch of ectool
commands (with and without --dev=1, so it tests both EC and PD).
System boots and all commands return expected results.
Change-Id: I4537d61a75cf087647e24281288392eb85f22eba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/387126
Shifted pd_task debug level by 1 so that debug level 1 will
enable printing the pd state name.
Added a CONFIG flag to remove ability to change debug_level
during runtime and debug print level will be fixed.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I545813bafa8084355cedc2d8334c3aec5a2b6739
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/339935
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
CONFIG_TABLET_MODE_SWITCH was incorrectly defined by default.
BUG=none
TEST=Kevin still have TABLET_MODE_SWITCH included.
BRANCH=none
Change-Id: I0748151e61eab5370be50be4512d2a851f705011
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/396384
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
BMI INT2 can be input or output.
It is not used currently, but configure it properly nevertheless.
BUG=none
BRANCH=none
TEST=On cave, (int2 is output), ensure FIFO headers are free of
interrupt information.
Change-Id: I9c058689a8676593aad542e33601cc11da105838
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/394066
The sysinfo and syslock commands aren't needed by all boards that
compile common/system.c, so let's make them individually
selectable.
BUG=none
BRANCH=none
TEST=make buildall; try on Gru
Confirm that by default these commands are still present
everywhere that they were before (since they're #defined by
default). Also confirm that it's possible to #undef them and
still build.
Change-Id: I7a5d21d1f0b9887f3562b9410063616ed8f41163
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/395366
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
The application may need to read/write/erase the flash memory,
but we not want console users to do so. This CL adds
CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH
to be undefined while still providing the chip-specific
flash_physical_* accessor functions.
There aren't many board.h files that needed changes, since
CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
See that it still boots, updates, wipes, restores, etc. without
linking common/flash.o in the production image; and that the
flash commands are still there in the dev build.
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93
Reviewed-on: https://chromium-review.googlesource.com/391188
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
We have a large number of config.h options to enable/disable
specific console commands. This adds a few more that we will want
to control.
BUG=chrome-os-partner:57408
BRANCH=none
TEST=make buildall; try on Gru with and without CR50_DEV=1
Change-Id: Id41f0e9f44fc77feaf56853f357a6b33bb685b0c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391614
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We have a bunch of options to enable/disable individual console
commands, but they're not quite sorted. Now they are.
BUG=none
BRANCH=none
TEST=make buildall
Change-Id: I186b9f82dc40c2f9fc66f493b4b6cccda020224c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391613
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added i2ctest console command to test the reliability of the I2C.
By reading/writing to the known registers this tests provides the
number of successful read and writes.
BUG=chrome-os-partner:57487
TEST=Enabled the i2ctest config on Reef and tested the
i2c read/writes.
BRANCH=none
Change-Id: I9e27ff96f2b85422933bc590d112a083990e2dfb
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/290427
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously, there was no way to identify which flash chip was used by
the EC, for ECs using an external SPI flash. Now, 'ectool flashinfo'
will print more information about the SPI flash chip in these cases.
BUG=chrome-os-partner:56765
BRANCH=any EC with MEC1322 or NPCX still going through factory
TEST=define CONFIG_HOSTCMD_FLASH_SPI_INFO, then
'ectool flashspiinfo' on samus indicates no SPI flash info,
and prints additional info on chell and kevin. Without
the config defined, all platforms report no spi flash info.
CQ-DEPEND=CL:386368
Change-Id: I3c162f7ad12ed4b30ab951c03f24476683382114
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/385702
Reviewed-by: Shawn N <shawnn@chromium.org>
Except the CHIP_ID and charger name code is common between BD99955
and BD99956. Hence renamed the code to BD9995X so that valid
output is printed from console commands.
BUG=chrome-os-partner:57519
BRANCH=none
TEST=Manually tested on Reef. 'charger' console command prints
charger name as 'bd99956'
Change-Id: I3c995757941bcc5a6a8026dd807d76a7a47c9911
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/387119
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
AL3010 is Dyna-Image ambient light sensor.
Here is add basic driver and functions.
BUG=chrome-os-partner:52915
BRANCH=elm
TEST=Flash on base board "glados" with ASUS
al3010_init is return success.
al3010_read_lux is return the lux success.
Change-Id: Ie3b97d0889b150c43d19bc84d84f04c13e415c31
Signed-off-by: Rocky Hsiao <rocky.hsiao@dyna-image.com>
Reviewed-on: https://chromium-review.googlesource.com/356874
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Thomas Lin <thomas.lin@dyna-image.com>
The BD99956 charger has a power save mode that it can enter once VBUS or
VCC is removed. This commit adds an optional config option that can be
used to select the power save mode:
CONFIG_BD99955_POWER_SAVE_MODE
By default, no power save mode will be enabled. However, a board can
device what level of power savings they wish to use.
The levels are the following:
BD99955_PWR_SAVE_LOW /* BGATE ON w/ PROCHOT# monitored only system
* voltage. */
BD99955_PWR_SAVE_MED /* BGATE ON w/ PROCHOT# monitored only system
* voltage every 1ms. */
BD99955_PWR_SAVE_HIGH /* BGATE ON w/o PROCHOT# monitoring. */
BD99955_PWR_SAVE_MAX /* BGATE OFF */
BUG=chrome-os-partner:55631
BRANCH=kevin
TEST=make -j buildall
Change-Id: Ibab7ad30d5f1ae9917b46b40d6f2800ef19e52dd
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/382877
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When tablet mode is detected, send an event to the AP.
BUG=chromium:606718
BRANCH=none
TEST=Check with evtest that events are sent when the tablet goes in tablet
mode and back to device mode.
Change-Id: I49f2404b5ecf87e71fa5aef4c8ce9c9beda26a15
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/380414
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Using the lid angle, detect if we are in tablet mode or not.
We are in tablet mode when the lid angle is large enough:
tablet_mode:
1 | +-----<----+----------
| \/ /\
| | |
0 |------------------------>----+
+------------------+----------+----------+ lid angle
0 240 300 360
BRANCH=kevin
BUG=chrome-os-partner:55702,b:27849483
TEST=Check on Kevin event are sent on tablet mode transition.
Change-Id: Id9935ce4dd717e2c20fa6c9520defb504a1760d9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383073
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
When lid is closed, the lid angle can move to 358, 360, 0, 359 ...
Prevent transition 0 from/to 360 by keeping the last calculated value.
BRANCH=kevin
BUG=chrome-os-partner:55702
TEST=Check transition does not happen anymore.
Change-Id: Ifa8415470f425c893e2c3662c84c8fd0156e0524
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/373040
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
This adds support for the GD25LQ40 NOR flash chip which is identical
to W25Q40 for the purposes of write-protection support for the ranges
that we care about.
BUG=chrome-os-partner:57015
BRANCH=none
TEST=needs testing
Change-Id: I09ad02e04fab4c539b9558180d73bf6c31da6aed
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382641
Reviewed-by: Shawn N <shawnn@chromium.org>
This CL includes changes in Cr50 required to support TPM via
the I2CS interface.
BRANCH=none
BUG=chrome-os-partner:40397
TEST=manual
Limited testing so far. Verified that the I2CS interface is
initialized properly and that register reads occur when
initiated on the AP console via command i2cget -y 8 0x50 0x1 w
Change-Id: I16ac17c7c82d420a384908e4b5a9867a3b24bc9e
Reviewed-on: https://chromium-review.googlesource.com/356241
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To save space of working image, make the console memory commands
optional.
BRANCH=veyron
BUG=b:27849483
TEST=Compile, save 320 bytes.
Change-Id: Ia538b30b4c06955c44b29eb22ed1a09fad83bd9e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/379115
Reviewed-by: Randall Spangler <rspangler@chromium.org>
TPM2.0 needs more NvMem space and currently the whole block is
contiguous in memory with 2 partitions. This CL removes the
requirement that the partitions are in contiguous which allows for 1
partition to placed at top of RW_A and the other at RW_B.
This CL does not change the size of each partition as that will be
done in a subsequent CL.
BRANCH=none
BUG=chrome-os-partner:56798
TEST=manual
Tested with the unit test 'make runtests TEST_LIST_HOST=nvmem' and
verified that all tests pass.
Tested on Kevin, erased the existing NvMem area and verified that TPM
was still manufactured and executed the command: trunks_client --own
Erased parition 0 and 1 in the new locations and repeated the tests.
Change-Id: I295441f94dccdf5a152c32603c2638ffac23f471
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378675
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Tested-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This is for boards on which AC_PRESENT can be expected to fluctuate
over a much longer period than the code was originally designed for.
Specifically, USB-PD systems may require several hundred milliseconds
for the state machine to settle before making decisions based on
AC_PRESENT status, for example, changing LED state.
BUG=chrome-os-partner:56471
BRANCH=none
TEST=Tested on Reef with follow-up patch
Change-Id: I370048cb79d1593a14077563ec8db8e8282afb16
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378755
CONFIG_POWER_TRACK_HOST_SLEEP_STATE has a dependency on
CONFIG_POWER_COMMON, so remove it from test builds that don't have a
chipset task, rather than heavy-handedly removing it from all test
builds.
BUG=chrome-os-partner:56197
BRANCH=None
TEST=`make BOARD=gru tests`
Change-Id: I86e20b4dccbb01ee285054a47093d6f60abc2166
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/378119
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
stm32f446 uses a synopsys designware USB block
rather than the typical ST one. This change adds driver support
for the new block, including usb console support.
BUG=chromium:608039
TEST=usb console works
BRANCH=None
Change-Id: I0e143758ae0b5285f1c94ea2ec5aee159e22e00c
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365448
Reviewed-by: Randall Spangler <rspangler@chromium.org>
