There are 3 methods to power on the system:
1) Pulling PWRKEY low (User presses PWRKEY)
2) Setting BBWAKEUP high
3) Valid charger plug-in
We should ensure that BBWAKEUP should be high when release PWRKEY.
Due to the RTC driver of coreboot will move to ramstage, and the
setup timing of BBWAKEUP will be postpone. In order to ensure PMIC
keeping the power until coreboot pull BBWAKEUP up, it needs to
increase the PMIC power key press time to avoid PMIC turn the
power off. This change is related to:
https://chromium-review.googlesource.com/#/c/257389/
BRANCH=none
BUG=none
TEST=manual
Update coreboot with above patch, press power key and system
should power on normally.
Change-Id: I7fabc49e0b3956885cb83a0b40c31c60080d0cbc
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/290538
Reviewed-by: Rong Chang <rongchang@chromium.org>
Oak rev3 has 2 dual-color LEDs to indicate the AP power & battery
status. The behavior has been redefined and distinguish from rev2
by board version API.
BRANCH=none
BUG=none
TEST=manual
1. define CONFIG_BOARD_OAK_REV_2 in board.h
make -j BOARD=oak
2. define CONFIG_BOARD_OAK_REV_3 in board.h
make -j BOARD=oak
both cases should be built successfully.
And Check the PWR & BAT LED.
Change-Id: Ic60d6f91002c3534e4c12a27e5c89bc2d0a1ecfd
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/290061
Reviewed-by: Rong Chang <rongchang@chromium.org>
The AP warm reset pin is changed from rev3 of oak board.
PB3 is stuffed before rev3 and connected to PMIC RESET pin to
reset the AP. For rev3, the AP reset mechanism is changed:
PC3 connects to PMIC SYSRSTB, pull PC3 to low, to reset AP.
BRANCH=none
BUG=none
TEST=manual
1. define CONFIG_BOARD_OAK_REV_2 in board.h
make -j BOARD=oak
2. define CONFIG_BOARD_OAK_REV_3 in board.h
make -j BOARD=oak
both cases should be built successfully and run "apreset" command.
AP should be reset normally.
Change-Id: I979e93acf755509f8cb7a12dd77eb7c9e7a98ccc
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/289476
Reviewed-by: Rong Chang <rongchang@chromium.org>
In S3, the EC isn't expecting AP host commands, so it's safe to enable
sleep
BRANCH=none
BUG=none
TEST=Check sleep mask in S0 and S3.
Also check sleep mask after sysjump with AP on and with AP off.
Change-Id: I9dcfe996e8e92e6703d71bbe966cd2447c6b14fe
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/290002
Reviewed-by: Rong Chang <rongchang@chromium.org>
Fix buffer overrun bug when retrieving a PD message. Bug was
introduced in CL:289005
BUG=chrome-os-partner:43482
BRANCH=none
TEST=tested on samus. plug and unplug zinger on both ports and
make sure PD MCU never crashes.
Change-Id: I9d2dec0cab07f389fd935d616ab7443da412d4bd
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290417
Reviewed-by: Shawn N <shawnn@chromium.org>
Configure boards whose chipset cannot be a USB UFP to disconnect
USB lanes when the data role is UFP.
BUG=none
BRANCH=strago
TEST=make -j buildall. tested on glados by adding ccprintf to
usb_charger_set_switches(). verified when we are DFP, USB 2
switches are connected and when we are UFP, they are disconnected.
Change-Id: Ic8c817a0cc21b56ee67239e8cc81d5cbbda8d4de
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290422
Reviewed-by: Shawn N <shawnn@chromium.org>
Modify the GPIO seeting according to the Oak rev3 schematic.
BRANCH=none
BUG=none
TEST=manual
1. define CONFIG_BOARD_OAK_REV_2 in board.h
make -j BOARD=oak
2. define CONFIG_BOARD_OAK_REV_3 in board.h
make -j BOARD=oak
both cases should be built successfully.
Change-Id: I0336624a5a2d356a4c2eb9ffb812ebffb4f5f7c3
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/289475
Reviewed-by: Rong Chang <rongchang@chromium.org>
The flash_ec script is called by the lab infrastructure to flash
the EC firmware of DUT. To prevent the EC flashing tool hanged
forever (may be caused by some bugs), set a 10-minute timeout to
force it to be killed.
BRANCH=none
BUG=chromium:514810
TEST=Patched the change to servo v3. Triggered flash_ec to flash EC
on Jerry. Set the timeout to a small value to force to kill itself.
test2:
./flash_ec --board=hadoken # or samus, anything using openocd
remove the USB cable half way through (openocd hangs)
ps au | grep openocd
Change-Id: I39ad8659b41764fd0dba30a86eca301fbbc5243f
Signed-off-by: Tom Wai-Hong Tam <waihong@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289247
Commit-Queue: Myles Watson <mylesgw@chromium.org>
system_get_chip_revision() would return a string which lacked the
terminating null. Increase the string length and enforce termination.
BUG=chromium:511405
BRANCH=none
TEST=version; should show chip revision without garbage chars at end
Change-Id: Icb9e36c5bfdf7de7400e5316934ccf28b4b57898
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290392
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
BUG=chrome-os-partner:42156
TEST=Manual on Glados. Boot to S0, run "temps". Verify that temperatures
start around 28C and begin to increase after system is powered-on for a long
duration.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3bebba4864c8e5b5b23e78947522e58311298bbd
Reviewed-on: https://chromium-review.googlesource.com/289936
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Add support for ADC / thermistor reads on the BD99992GW PMIC.
BUG=chrome-os-partner:42156
TEST=Manual on Glados with subsequent commit. Boot to S0, run "temps".
Verify that temperatures start around 28C and begin to increase after
system is powered-on for a long duration.
BRANCH=None
Change-Id: Ic15f41046130317a0e0c3bce4a923ba624328c0d
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289935
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In order to pass the test case "firmware_ECPowerButton",
I change the value of DELAY_FORCE_SHUTDOWN from 11s to 10s.
The test case holds down power button about 10s to shut down
without powerd.
BRANCH=none
BUG=none
TEST=manual
run "firmware_ECPowerButton" test case.
Change-Id: I3da93769f1cb52b04c447df9a7795d3c28ab2bf0
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/282153
Reviewed-by: Rong Chang <rongchang@chromium.org>
Don't enable try.src when battery is not present or <1% because
try.src will temporarily cut off power to system.
BUG=chrome-os-partner:43413
BRANCH=samus
TEST=tested on samus using "battfake" ec command. when battery
<1%, verified that try.src is disabled and when battery >=1% and
the AP is on (dual-role toggling is on), then try.src is enabled.
verified boot without battery succeeds on samus and glados.
Change-Id: I64816bb7c9669bfeca61687bcd9a48da32e67945
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289854
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add RX message buffer to the TCPC (currently two deep). If
the buffer is full and message is received, don't send goodCRC.
BUG=chrome-os-partner:43482
BRANCH=none
TEST=tested on glados. saw that with back to back PD
packets, we send goodCRC to both packets and process them in
order, taking about 7ms per packet. also tested buffer size
of 1 and verified that with back to back PD packets, we don't
send goodCRC to second packet.
Change-Id: I7f44b3c3a186ae61be8ca03017deec6e6b6c6f9f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289005
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch implements FIFO mode state machine transitions as described
in Table 22 of the PC Client Platform document.
The 'go' command is still not being handled, as processing needs to
run on a task, not on interrupt context. FIFO block integrity is
somewhat verified by comparing the actual block size to the length
value in the block body.
BRANCH=None
BUG=chrome-os-partner:43025
TEST=not much. Observed trunksd happily initializing the session and
sending the Startup command. The target reports:
fifo_reg_write: received fifo command 0x0144
Change-Id: I76d8b0fc3a52db2cc487c781fe92799df0ee259e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288365
Reviewed-by: Utkarsh Sanghi <usanghi@chromium.org>
Now that HOOK_INIT hooks are called from a task switching context, most
calls to task_start_called() should no longer be needed. This commit
removes them.
BRANCH=None
BUG=chrome-os-partner:27226
TEST=make -j buildall tests
TEST=Flash EC image onto samus and verify EC boot, AP boot, keyboard,
lid, and tap-for-battery all functional.
TEST=Flash EC image onto samus_pd and verify charging still works.
TEST=Flash EC image onto ryu(P3) and verify that EC boot.
TEST=Added ASSERT(task_start_called()) to the places where I removed
task_start_called(). Booted samus, samus_pd, cyan, and ryu with AC
inserted and verified that no ASSERT's were hit upon boot.
Change-Id: Ic12c61862e85ca3a0a295beedbb4eeee6d5e515b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/285635
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
When LPC mode is used, there is an assumption that the first
2 sensors are accelerometers, and the optional 3rd is a gyro.
Put the code that fill lpc_data with #ifdef.
Prevent lpc space corruption if more than 3 sensors are present.
BRANCH=smaug
TEST=Compile. Smaug works
BUG=None
Change-Id: I12c9b823efb57d7b190a1813228f6f02fa0bebcb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290073
Inhibit AP power-on through the BATLOW pin, even if the system is
unprotected, until our charger and current limit are initialized.
Note that this feature is only functional on glados v2 since other
skylake boards do not have BATLOW connected.
BUG=chrome-os-partner:41258
TEST=Manual on glados v1 with rework. Remove battery and attach Zinger.
Verify EC powers on and AP doesn't boot. Run `powerbtn`, verify that AP
boots. Remove all power and attach battery, verify that EC powers on
and AP boots. Also verify compilation on glados v2.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I55de857f7006777640f7853b7bde98ba97e8bd13
Reviewed-on: https://chromium-review.googlesource.com/287378
Check IN_POWER_GOOD signal in S0 and go to S3 if IN_POWER_GOOD is lost.
Finally it will go to S5(G3).
Check suspend and power good signal after POWER_DEBOUNCE_TIME to
avoid transient state.
BRANCH=none
BUG=none
TEST=manual
Test power related commands such as "shutdown -P now" or "apshutdown".
Change-Id: Ia06fc7d8334c0dfbb0263474f57e4dca7313d331
Signed-off-by: YH Huang <yh.huang@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/282680
Reviewed-by: Rong Chang <rongchang@chromium.org>
The AC presence input from the charger only goes to the EC and it
needs to provide this signal to the PCH. At init time it is set to
the current value and whenever the status changes it will be updated.
This is used by PCH internal logic to determine whether to transition
into Deep S3/S5 as those are not intended to be used when running on
AC power.
This is similar to how it worked on Samus except since the EC is off
in G3 we don't need to force it low in that state and since there
are not yet any additional hacks/workarounds here we can just do the
work in a simple HOOK_AC_CHANGE handler.
BUG=chrome-os-partner:41885
BRANCH=none
TEST=boot on glados and verify PCH_ACOK is asserted when the device
starts to charge and is deasserted when no cable is connected.
Change-Id: Id7e6ca674e35c98594d09b86ab5bdf518f8b3984
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288922
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Remove the last pieces of external Sensor Hub support:
- Sensor hub UART exported over case closed debugging
- Sensor hub related GPIOs
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:38333
TEST=plug Suzy-Q to Smaug and test debug UARTs and SPI flashing
Change-Id: I47b42f63647735bae37b9256e2704303c48b5854
Reviewed-on: https://chromium-review.googlesource.com/290115
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
boards version 6 / 7 / 8 have an I2C bus to sensors.
board version 0+ has a SPI bus to sensors
On board v0, enable 3rd SPI port and use it to accel the accelerometer.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Check accel on SPI enabled Ryu board,
on v7 and v0 boards, check closed case debugging and type-C features
Change-Id: Ic8de2bb0f9d8a15f86a2c1ea98ef27613f090b22
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289960
Using the LSB bit of motion_sensor addr field, we can
select at run time if a sensor is using SPI or I2C.
When the hardware stabilize, this CL can be removed.
BRANCH=smaug
TEST=Check that same image works on both i2c and SPI devices.
BUG=chrome-os-partner:42304
Change-Id: I9aef9a4dc739366a3d4e2f6fafe063ecfb5199c6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289925
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Enable 3rd SPI port and use it to accel the accelerometer.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Check accel on SPI enabled Ryu board.
Change-Id: If17eff36e2a3ea0fe59d6677aa41ba5f802e33b6
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288516
- Add 3ms after write, found issue with SPI writes.
- Do not check FIFO if all sensors are disabled.
It contains garbage (0x848484....)
- Do not check FIFO length. It can be 0 even if there
is data in the fifo.
- Remove forever latch and do not reset Interrupt in the handler,
we are using level interrupt.
- Flush and exit when the FIFO is in a bad state.
BRANCH=smaug
BUG=chrome-os-partner:43339,chrome-os-partner:39900
TEST=Ran CTS tests. Check sensor is stable.
Change-Id: I5cbae819e780b4d50d02829fd8e1178cf34c3f84
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289839
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We need to call irq_handler and load_fifo even if the
first sensor is disable. Nothing is done on otherwise.
Move code to recalculate sample rate to the right place.
BRANCH=smaug
TEST=Check data is collected when accel is disabled.
BUG=chrome-os-partner:39900
Change-Id: Ia6025a670abaf2e71ccbe784bce24e08becf399e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289838
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We are very close from the current limit (456 bytes).
Increase the limit to 640 bytes.
BRANCH=smaug
TEST=Hit the limit while debugging, check the new limit.
BUG=none
Change-Id: I6673000bcac48b88599082eb797f0782c4fee454
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289837
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
SPI being much faster, need to add right sleep to wait for
sensor to change state from suspend.
Set the ODR before the range, an issue I did not have with i2c.
Fix test used when FIFO is disabled.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Check sensors are coming and rate/range are correctly set.
Change-Id: I5bf655626f1f4232478a04d1d4e1a0d443efbf0f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288517
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add interface to access the sensor using SPI interface.
BRANCH=smaug
TEST=compile and work on new Ryu board
BUG=chrome-os-partner:42304
Change-Id: I987259a7e378de8ada3b3b55b3662e5028ea31b2
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288515
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Like the implementation for mec1322, add a lock around spi_transaction.
It prevents 2 tasks from accessing a given bus at the same time.
BRANCH=smaug
TEST=Check the BMI160 FIFO corruption disappeared in SPI mode.
BUG=None
Change-Id: I9e8a9e39ca96ea56692e3125930ab05ae6ef143f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289856
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Modify i2c driver on mec1322 to change from sleeping and waking
on i2c interrupt, to just doing a blocking wait for i2c transfer
to complete. This greatly improves the i2c transaction time on
fast busses.
BUG=chrome-os-partner:43416
BRANCH=none
TEST=test on glados. test can talk to battery and PD MCU. Use
logic analyzer to see delay between bytes during an i2c transfer.
The delay goes from ~70us to ~4us.
Change-Id: Iee2a903d27b2e50e54d64bd6d5ed4920293fe575
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289667
Reviewed-by: Shawn N <shawnn@chromium.org>
Oak takes power from type-C charger. The default input current limit
should set to 512mA default, not the maximum current for battery
charging.
BRANCH=none
BUG=none
TEST=manual
load on oak and plug an empty battery. check EC uart console on PD
state change when plug type-C charger.
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I113fea5ff1e8afc053f76c21820f202e4b3edfec
Reviewed-on: https://chromium-review.googlesource.com/287610
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.
Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
Allow more than one SPI master.
Add CONFIG variables to address the system SPI flash.
To have SPI master ports, spi_ports array must be defined.
BRANCH=smaug
TEST=compile
BUG=chrome-os-partner:42304
Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288512
Commit-Queue: David James <davidjames@chromium.org>
The ec_date.h file had incorrect dependencies. $(objs) had no meaning
outside of the building the object files as it gets privately overidden
with the corresponding target objects (RO, RW, libsharedobjs). This
caused ec_date.h to only be generated once from a clean. This commit
fixes that by adding all of the RO and RW objects as dependencies (with
the exception of version.o).
BUG=chrome-os-partner:43373
BRANCH=None
TEST=Built ryu, checked build timestamp in build_info. Touched a file,
rebuilt, verified that build timestamp was updated.
TEST=make -j buildall tests
Change-Id: I0ab107efc1a504b4f871ebcf595754db1d414c7a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/289338
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Decrease default system stack size on stm32f05 which only has 8k
of RAM.
BUG=none
BRANCH=none
TEST=tested on glados. just ran glados_pd and plugged various
peripherals into type-C port and saw nothing unusual.
Change-Id: Ic051a1387903662414c8e4fdc431e6ecfd7ad57f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289555
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Added macros to conditionally compile the console commands to save the
memory. These macros can be enabled/disabled in the board specific files.
BUG=none
TEST=make buildall -j
BRANCH=none
Change-Id: I108a072c333762cd24ea973612202c9cc4d40914
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/288950
Reviewed-by: Shawn N <shawnn@chromium.org>
Implement and enable custom charging profiles on glados to
allow us to charge faster.
BUG=chrome-os-partner:42864
BRANCH=none
TEST=load on glados and charge at room temp. verify using
"charger" command that the battery current matches the
expected fast charging current for the given temp range.
Change-Id: I7b213fd1724e9df09ada89ca27b05e0540b4de2a
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288208
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Modify host_command_pd.c to loop over sending of PD status
host command and processing the response as long as the
alert GPIO is active.
This fixes a potential bug that if the alert line is held
low for more than one PD status host command, then we would
not process the return status.
Also, fix a bug in which we could call alert() for a
non-existent port.
BUG=none
BRANCH=strago
TEST=verified on samus and glados. connected charger and verified
that we negotiate a contract and set appropriate input currnet limit.
Change-Id: I3b2db87b51f55fc2b20a4695bd466ff8bb09ea55
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288819
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: David James <davidjames@chromium.org>
Chipset task is overflowing and causing runtime crash.
Increasing the chipset task stack size by 128 bytes.
BUG=chrome-os-partner:43329
BRANCH=none
TEST=Build/flash EC and boot the platform to OS.
Change-Id: I4e444cc48979c74810851ab2625b982fdabdeb73
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/289112
Reviewed-by: Shawn N <shawnn@chromium.org>
