Servo_v4 requires the ability to have a different default state per
port. In previous devices, the assumption was that each supported port
had the same default usb pd state and power role. This CL moves the
by the default power role which in turn is derived from
CONFIG_USB_PD_DUAL_ROLE. In addiiton to moving the location, it now
uses 'port' as argument so it can be port specific if required.
PD_DEFAULT_STATE was a board.h specific config, but in practice each
instance used to date was set to PD_STATE_SNK_DISCONNECTED if
CONFIG_USB_PD_DUAL_ROLE was defined and set to
PD_STATE_SRC_DISCONNECTED otherwise.
BUG=chrome-os-partner:61878
BRANCH=servo
TEST=Manual run 'make -j buildall' to verify that all instances of
PD_DEFAULT_STATE were removed.
Change-Id: Iaf40718668732f525485ed7942ee7fc246d3f75d
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431787
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If battery is not present, input current is set to PD_MAX_CURRENT_MA.
If the input power set is greater than the maximum allowed system power,
system might get damaged. Hence, limit the input current to meet maximum
allowed input system power.
BUG=chrome-os-partner:58498
BRANCH=none
TEST=Manually tested on Reef. Removed the battery & using 'charger'
console command observed the following.
With Zinger charger at 20V - Input current is set to 2.25A
With Type-C & other chargers - Input current is set to 3A
Change-Id: Ife8686f322e095aa74b740a7c469bfe87107fb9a
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/397865
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
charge_manager may request a charge current limit less than the
capability of the supply in certain cases (eg. during PD voltage
transition, to make an effort to comply with reduced load spec).
Depending on the battery / system state, setting a reduced charge
current limit may result in brownout.
Pass the uncapped / max negotiated current to board_set_charge_limit()
so that boards may use it instead of the requested limit in such
circumstances.
BUG=chrome-os-partner:56139
BRANCH=gru
TEST=Manual on kevin with subsequent commit, boot system with zinger +
low-charge battery, verify devices powers up to OS without brownout.
Change-Id: I2b8e0d44edcf57ffe4ee0fdec1a1ed35c6becbbd
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/383732
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When the charger is detached, the host event would sometimes be
sent before the charge info was updated, resulting in the host
thinking that the charger was still connected.
BUG=chrome-os-partner:55584
BRANCH=none
TEST=Connected charger to kevin 15 times and verified that the
icon was removed in 2-seconds or less.
Change-Id: I1a4e4e0f7cc23010210570fc261da8308d8e8070
Reviewed-on: https://chromium-review.googlesource.com/367809
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This feature is inconsistent. Not all boards have such a symlink
(for a obvious reason).
This feature is fragile. It's most likely not tested and going to be
broken if not already. Developers won't like it if they have to test
two different ways to build boards before submitting patches.
This feature is not necessary. If you build EC in the standard way
(e.g. make BOARD=samus), these symlinks are not needed.
This feature is wasteful. Extra disk spaces are used and extra lines
are added to Makefile (increasing code complexity slightly).
BUG=chromium:626776
BRANCH=none
TEST=make buildall
Change-Id: Id5444284d773cb0e9225f39abd877441b8f61440
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/359321
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Not everything with a temperature sensor uses thermal throttling. This
change modifies the conditional build to enable building temp sensor
source without thermal throttling.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I8c0753f12899e9f203c04477ae520bcda40d5fd8
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356484
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Added console commands for the debugging purpose
psys - Can be used to measure the system power
amonbmon - Can be used to measure AMON/BMON voltage diff, current
BUG=chrome-os-partner:54273
BRANCH=none
TEST=Manually tested on Amenia
psys - Ran fish task and observed psys value changes.
amonbmon - AMON & BMON voltage & current are same as measured
across sense resistors.
Change-Id: I6653e814d9b00efe7dae9ce1fbd7ddbc2356f8e0
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/353043
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously CONFIG_USB_PD_TCPM_VBUS had two uses which were independent:
- When operating as a TCPC, it indicated that the VBUS level should be
tracked (through GPIO inputs) and sent to the external TCPM when
appropriate.
- When operating as a TCPM, it indicated that the VBUS level should be
obtained by querying the TCPC.
These two independent uses have been split into
CONFIG_USB_PD_TCPC_TRACK_VBUS and CONFIG_USB_PD_VBUS_DETECT_TCPC, which
sould be more clear.
In addition, CONFIG_USB_PD_VBUS_DETECT_* CONFIGs have been added for
other means of VBUS detection.
BUG=chromium:616580
BRANCH=None
TEST=Verify kevin continues to boot + charge.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I936821481d6577e17e3e9c61ff97c037574d6923
Reviewed-on: https://chromium-review.googlesource.com/348950
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Previously the maximum number of deferred routines was specified by the
the default maximum number of deferred routines you had to override
this, and if you wanted fewer, you still payed the price of having the
defer_until array statically allocated to be the maximum size.
This change removes that define and instead creates the RAM state of
the deferred routine (the time to wait until to call the deferred) when
the deferred is declared.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
manually test on discovery-stm32f072
Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc
Reviewed-on: https://chromium-review.googlesource.com/335597
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Previously calls to hook_call_deferred were passed the function to call,
which was then looked up in the .rodata.deferred section with a linear
search. This linear search can be replaced with a subtract by passing
the pointer to the deferred_data object created when DECLARE_DEFERRED
was invoked.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
CQ-DEPEND=CL:*255812
TEST=make buildall -j
Change-Id: I951dd1541302875b102dd086154cf05591694440
Reviewed-on: https://chromium-review.googlesource.com/334315
Commit-Ready: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Various voltage rails will be enabled / disabled by the PMIC when
GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
by approximately 25ms in order to allow V1.00A to sufficiently discharge
first.
BUG=chrome-os-partner:52047
TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges
faster than V0.85A.
BRANCH=glados
Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337325
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
After a charger is attached, we may set a charge limit based upon BC1.2
or USB-C Rp before PD negotiation completes. Therefore, allow 2 seconds
for all negotiation to complete. Previously this behavior was implicit
when using SW charge ramp.
BUG=chrome-os-partner:51280
BRANCH=glados
TEST=Manual on chell. Insert stock charger, verify that it is detected
as TYPE_UNKNOWN until timeout.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I52f02de46fa92b66a9fbaddb94a062310688f028
Reviewed-on: https://chromium-review.googlesource.com/334312
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is keyboard test mechanism request for "multiple key press test",
we can thru the testing to scan out kso ksi pins shortting or keyboard has
multiple key pressing, below was the testing steps:
1. Turn off internal keyboard scan function.
2. Set all scan & sense pins to input and internal push up.
3. Set start one pin to output low.
4. check other pins status if any sense low level.
5. repeat step 3~4 for all keyboard KSO/KSI pins.
6. Turn on internal keyboard scan function.
BUG=chrome-os-partner:49235
BRANCH=ToT
TEST=manual
Short any KSO or KSI pins and excute "ectool kbfactorytest", it shows failed.
if no pins short together, it shows passed.
Change-Id: Id2c4310d45e892aebc6d2c0795db22eba5a30641
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/332322
Reviewed-by: Shawn N <shawnn@chromium.org>
Currently when in suspend the LED blinks white no matter what the
state of the battery or charging is. This is very confusing for
users who expect to be able to plug in a charger with the system
in suspend and see that it starts to charge.
Past platforms from this OEM have had two LEDs so this has not
been an issue.
BUG=chrome-os-partner:49151
BRANCH=glados
TEST=put chell in suspend, plug in charger to see amber LED and
then remove the charger and see that it blinks white again.
Change-Id: I60e849d7b8b717fb568d7d5d64046621c1c34157
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/332625
Reviewed-by: Shawn N <shawnn@chromium.org>
With commit e9883124ff, a GPIO_INT macro was added. That change
also required that all instances of GPIO_INT in a board's
gpio.inc file come before any GPIO macros, or the interrupt
handler wouldn't work properly.
This CL just adds a warning comment about requirement to all
gpio.inc files.
BUG=chromium:471331
BRANCH=none
TEST=make buildall, test image on Cr50
This is a change to comments only. There is no new behavior to
verify, although I did run try out one new image just to be sure
nothing stupid happened.
Change-Id: I83f7819929a53bce3a8bae04d15b3ee3bda11738
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/329334
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Previously these were often done in board.c files, which made it
impossible to include the gpio.inc anywhere else. As part of
refactoring the GPIO code we now need to be able to include gpio.inc
from common/gpio.c. Moving these defines into gpio.inc makes them
available wherever gpio.inc is included.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I28e7b5a1d40b113ae824b18f020b2d1e51e0c08a
Reviewed-on: https://chromium-review.googlesource.com/328822
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
EC boot / hash computing can be a bottleneck for system boot time.
Reduce this bottleneck by running our processor at 48 MHz through boot,
until vboot hashing of RW completes.
BUG=chrome-os-partner:49583
TEST=Boot chell, verify vboot hash completes within 1 sec of EC boot and
'cbmem' delta between 'vboot select&load kernel' and 'finished EC
verification' is reduced to ~250 ms (which includes sysjump time).
BRANCH=glados
Change-Id: I18d87e685b89decef761e51517bfcfc43dcf8ef0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326792
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Blink the LED in S3 as well as S0iX states so there is no user visible
difference in their behavior.
BUG=chrome-os-partner:49274
BRANCH=glados
TEST=Enter S0iX on chell (need SKU4) and verify LED blinks. Also verify
that the LED still blinks in S3.
Change-Id: I91b123de17787159f4e7d6aca2e86b80885b8f4e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/326740
Reviewed-by: Shawn N <shawnn@chromium.org>
Setting battery charging maximum value of temperature.
If battery temperture is over than 45 degree, set charge current to
0 mA, and charge state to idle. Then LED will turn to white in idle
state.
BUG=chrome-os-partner:49695
BRANCH=glados
TEST=check the battery will not charge when battery temperture is
over than 45 degree, and LED turn to white. Then temperture is less
than 45 degree, the battery will charge and LED turn to amber.
Signed-off-by: Bruce.Wan <Bruce.Wan@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/323982
Reviewed-by: Shawn N <shawnn@chromium.org>
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 4994d85d3b6c589e3ac297697aeb36456f2401a6)
Change-Id: Ic7d3fe0c482fab76041c5ae3f35402e529576b1c
Reviewed-on: https://chromium-review.googlesource.com/325487
Enable the config option for S0IX power control and set the GPIO to
use power_signal_interrupt_S0.
BUG=chrome-os-partner:49274
BRANCH=glados
TEST=echo freeze > /sys/power/state
Unfortunately currently SLP_S0_L is not asserting so this is difficult
to actually test the EC behavior
Change-Id: I302da7735c9622975e0386a0b4542f41c7231df9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324567
Reviewed-by: Shawn N <shawnn@chromium.org>
Shut down all PMIC-supplied power rails rather than initiating EC / PD
hibernate. This results in considerable power savings.
BUG=chrome-os-partner:48835
BRANCH=glados
TEST=Manual on chell. Run "hibernate" on EC console, verify that 3.3V EC DSW
rail goes to 0V, and the EC powers up on zinger insert, lid open or power
button press.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I7bf0c494ea240183240f5a6abc3d611df8efb45a
Reviewed-on: https://chromium-review.googlesource.com/324087
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good
idea:
- INPUT / PULL_UP is not necessarially the lowest-power state (for
example, if there is an onboard pull-down).
- Most GPIOs should already be in lowest-power state when we're in S5.
- For the few GPIOs that need to be in a different state for hibernate,
we can use a board-level callback.
In addition, remove mec1322 code related to restoring from hibernate
state, since we always reset coming out of hibernate.
BUG=chrome-os-partner:49608
BRANCH=glados, strago
TEST=`hibernate` on chell console when in S5 and AC removed. Verify that
EC power is roughly equivalent to low-power idle power. Attach Zinger,
verify that device wakes and boots, and charges from charger.
Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322937
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Enable CONFIG_BOARD_HAS_RTC_RESET and add a board_rtc_reset() function
to assert RTCRST to the PCH that will be called if the board fails to
sequence out of the S5 state.
This does not do anything on EVT devices but will be present in DVT.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=manually tested on chell
Change-Id: If0be091349a7ef7e8e1335ade029570c5f97a30e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322725
Reviewed-by: Shawn N <shawnn@chromium.org>
The GPIOs were set incorrectly in EVT so invert them in the EC
so we can keep an incrementing board version.
BUG=chrome-os-partner:49357
BRANCH=glados
TEST=test that 'version' reports 1 for EVT board instead of 4
Change-Id: I520c3e09c7c3f0797b46807932f859aa490ac4c7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321929
Reviewed-by: Shawn N <shawnn@chromium.org>
Pull floating pins high, don't duplicate external pull ups, and make a
few other minor changes.
BUG=chrome-os-partner:48109
TEST=Verify chell continues to boot and S5 power is reduced to
~5.5 mW.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaee0cc926149dae1f4189e6b9e4f7e3a4da6ba1c
Reviewed-on: https://chromium-review.googlesource.com/319165
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If deep sleep S5 is supported RSMRST to the PCH should not be high
when the PCH is in S5 unless the board is sequencing out of deep sleep
and S5 state. Therefore, ensure RSMRST is low when the EC goes into
hibernate. This assumes deep sleep S5 is employed. A more appropriate
fix is to honor RMSRST state prior to going into hibernate state.
Without this change the behavior on certain platforms do not sequence
out of S5 when coming out of hibernate.
BUG=chrome-os-partner:48133
BRANCH=none
TEST=tested on a failing EVT chell board at the factory
Change-Id: Ia4a1cdb59c25a3fc704c64fbe6beb01ede90d777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/317070
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rather than having various PWM module groups initialized from various
HOOK_INIT functions, group them all into a single module and initialize
them all from a common function in pwm.c.
BUG=chromium:563708
TEST=Manual on samus / samus_pd (with CONFIG_ADC enabled). Verify that
samus fan + KB backlight control is functional and samus_pd correctly
sets PWM output.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I9f9b09bfa544cd9bc6b7a867e77757dff0505941
Reviewed-on: https://chromium-review.googlesource.com/314882
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
If pulled up the backlight will be at 100% brightness instead of off.
BUG=chrome-os-partner:48130
BRANCH=none
TEST=hibernate on chell, see keyboard backlight stay off
Change-Id: I30cd289b9492356407aa54e6a84b04add647bd9a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/314936
Reviewed-by: Shawn N <shawnn@chromium.org>
Send power change event to AP whenever input power is changed,
ensure that AP gets the latest power charging info.
BUG=chrome-os-partner:47677
BRANCH=none
TEST=tested on Oak by plug/unplug AC adapter to type-C ports and
verifying the UI battery icon shows the correct status instantly.
Change-Id: I7465afcd8bc9b1c56ecf70fc74446866a8ab1b9a
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/313926
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Apply the recommended USB EQ settings for Tx and Rx channel
loss compensation to the PS8740 USB mux chip. This is called
after the driver is initialized and sets up the chip for the
first time.
BUG=chrome-os-partner:47074
BRANCH=none
TEST=build and boot on chell, read back registers to verify
> i2cxfer r 1 0x34 0x32
0x60 [96]
> i2cxfer r 1 0x34 0x3b
0x60 [96]
> i2cxfer r 1 0x20 0x32
0x60 [96]
> i2cxfer r 1 0x20 0x3b
0x60 [96]
Change-Id: I95334be9eed2858864787500a7483fa043947148
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313748
Reviewed-by: Shawn N <shawnn@chromium.org>
- Disable SLP_S0 as interrupt source for proto boards
- Remove pull-up on PLATFORM_EC_PROCHOT for EVT boards
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell proto
Change-Id: I3196e9fe1c921d66fd841c6ca1c3d8df131db9eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313663
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
