coreboot will enable AP_OVERTEMP signal when AP
has surpassed a temperature threshold. These
changes has the EC do an apshutdown when it
detects this signal going high.
BUG=chrome-os-partner:51926
BRANCH=None
TEST=lower AP_OVERTEMP threshold and make sure
that AP shutdown occurs.
CQ-DEPEND=CL:342797
Change-Id: Ib9c9d03d2df0d670830c0b4eea3eea3ba5bae0b8
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343060
Reviewed-by: Shawn N <shawnn@chromium.org>
Add generic PWM host commands for setting + getting duty cycle. PWMs can
be controlled through index (board-specific meaning) or by type
(currently KB backlight and display backlight are supported, more can be
added as needed).
BUG=chrome-os-partner:52002
BRANCH=None
TEST=Manual on chell.
`ectool pwmsetduty kb 100` - Verify KB backlight goes to 100%
`ectool pwmgetduty kb` - Prints 100
`ectool pwmgetduty 0` - Prints 100
`ectool pwmsetduty 0 0` - Verify KB backlight goes to 0%
`ectool pwmgetduty kb` - Prints 0
`ectool pwmgetduty disp` - Error res 3 (unsupported PWM type)
`ectool pwmsetduty 1` - Error res 3 (non-existent PWM index)
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I607c92a291e6c2e3af8238eaf22ad2bb81ffc805
Reviewed-on: https://chromium-review.googlesource.com/344012
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The tracing runs a higher priority task (SNIFFER) than the packet
injection (on CONSOLE task) and both RX and TX are using the same buffer,
so when we are sending a packet, we are getting immediately preempted by
the tracer and bad stuffs happen.
Now, we can manually inject packets and get the text trace of the
response.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=with the SOP' experimental patch, plug a full-featured cable into
Samus with Twinkie as an interposer, then do the following sequence:
Pretend there is a device
> tw resistor rd 0
Enable the text tracing
> tw trace on
Send discover identity to the cable (and get the descriptors)
> tw sendprime 1 0x104f ff008001
Sent CC1 104f + 1 = 381
165.939687 SRC/0 [0141]GOODCRC
165.942520 SRC/0 [514f]VDM Vff00:DISCID,ACK:ff008041 1c00050d 00000000 030a0000 11082032
Change-Id: Ie0ad57341c6476e983229b532716986dffefa8a1
Reviewed-on: https://chromium-review.googlesource.com/342512
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Kevin is code space constrained, so use RAM normally used for data
instead for code.
BUG=chrome-os-partner:52876
BRANCH=None
TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data
RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes
to add sensor task). Also, verify kevin continues to boot + power sequence.
Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/343191
Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Two permission registers are already lowered. This adds the
remaining two.
BUG=chrome-os-partner:52994
BRANCH=none
TEST=make buildall; run on Cr50
USB works, SPI works, sleep and deep sleep work, tpmtest.py works.
Change-Id: Ifb27d5be81f10537114f4702addb58c6d7e1630c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342455
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using
HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a
higher-than-default relative priority for peripheral initialization
outside of board.
BUG=None
TEST=Verify PWM and ADC are functional on kevin.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb
Reviewed-on: https://chromium-review.googlesource.com/342171
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Use input signals to verify power state and determine power state after
sysjump.
BUG=chrome-os-partner:52878
BRANCH=None
TEST=Manual on kevin.
- Verify AP powers up on 'powerbtn'.
- AP shuts down on 'apshutdown'.
- AP re-powers / resets on 'powerbtn' + 'apreset'.
- AP doesn't shutdown on 'sysjump rw' while in S0.
Change-Id: Id24feb0f8490aa7cb73c46178085ff2e46f8d0a6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341704
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
BUG=chrome-os-partner:52576
BRANCH=none
TEST=make buildall; try on Cr50
I manually tested both highsec and highperf variants, as well as
forcing the bootrom init to run. All the bank registers were
loaded with meaningful values, and none of the SPI or USB
functionality showed any problems.
Change-Id: Ia91ba98ef4c667aec74195c4a7bbf72a5d1c8b2d
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/342030
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Remove buffer size checks in _cpri__GenerateKeyRSA().
The TPM stack passes in TPM2B buffers that
may have the size field uninitialized.
Callees are expected to assume that the
buffer size is sufficient for the requested
operation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=TCG test CPCTPM_TC2_2_20_03_02 reliably passes
Change-Id: I3d9bc2475b82dfaa9ed1d2617b1c333ff4df409d
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340883
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
When system on
.always blue
When system is off
.discharging : off
.charging : red
.full-charged : green
Error : red - green switching
BUG=None
TEST=See LED behavier on kevin
Change-Id: I93f0dbb503c68999825c455c8dc81b6bdaf397b4
Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/341113
Reviewed-by: Shawn N <shawnn@chromium.org>
_cpri__EccPointMultiply should check whether the provided
point is on the curve prior to doing a multiply.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=TCG test CPCTPM_TC2_4_13_01_01 passes
Change-Id: Ia92494070c62f7e03b395975138c0c8446a7284d
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/341112
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This change modifies the behavior of RBOX by blocking the key0 and key1
output, when the power button is pressed. It also adds support for
printing debug statements when various RBOX interrupts are triggered.
BUG=none
BRANCH=none
TEST=On cr50 test board verify key0 and key1 out are not asserted unless
the power button is pressed.
Change-Id: I67a3c1b8009279015bdc87bcf0995cffa9ab6f03
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341470
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Setitng SYS_RST_L as an output contends with the EC setting it as an
output. We will only drive the pin when necessary.
BUG=none
BRANCH=none
TEST=power on kevin and make sure the AP is able to boot.
Change-Id: Ie40cc4932ff92d20b021765c3aa356d8902f20e1
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341326
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This patch adds HSE and PLL as a system clock oscillator for STM32L4.
This allows us to drive the chip at a higher frequency (up to 80 MHz),
which is necessary to big-bang GPIO ports accurately.
BUG=none
BRANCH=tot
TEST=make buildall. Verified console works on STM32L476G-Eval using HSE,
PLL-HSE, PLL-HSI, PLL-MSI as an oscillator. Verified console runs soundly
with different frequencies from 20 Mhz to 80 Mhz. Verified frequencies
using oscilloscope on MCO (Microcontroller Clock Output) port up to 50 MHz.
Change-Id: I493cdb6c323eb4e6a1560f6d030935c1950b1a2a
Reviewed-on: https://chromium-review.googlesource.com/341275
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
CR50 does not depend on the rsa implementation
in common This change removes the corresponding
config option.
Also remove a duplicate CONFIG_SHA256 option, and add a
comment regarding CONFIG_SPS_TEST.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=compilation succeeds
Change-Id: Ie01439899042c5fa981f884a01b83eb0b3eb6e32
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/340539
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a
channel active during low-power idle / deep sleep. Currently it's
supported by npcx and mec1322.
BUG=chrome-os-partner:52783
BRANCH=glados
TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify
KB backlight does not flicker during idle.
Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341002
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
GPIO console commands currently only show input voltage level,
and can only set level on predefined outputs.
This change allows GPIOs to be cycled between output, input,
and alternate function, as well as displaying the mode and
asserted level (if any) in gpioget.
This change creates CONFIG_CMD_GPIO_EXTENDED
as the internal gpio interface needs to be changed to support
this, and I can't test the other architectures. It may be
worthwhile to add this for all, or not.
This change is also necessary also for servo micro JTAG and PD
UART support, as several pins are tied together on the flex
and stm32 outputs need to be variously active or in high-z
depending on mode.
BUG=chromium:571477
TEST=gpioget <0|1|IN|A|ALT>; gpioget;
BRANCH=None
Change-Id: Iba32992db6244ee1e654db840d1c9c11dd2a0993
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338885
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
The cr50 SPI master can control the external AP and EC SPI ROM. This
change adds support for doing spi_transactions, but does not use the SPI
transactions for anything except console commands. This support will be
used for flashing the AP and EC through CCD. For now AP and EC flash
select must be done manually using the spi_flash_select console command.
Flash select should be disabled after use, because it will prevent the
system from booting.
BUG=chrome-os-partner:50701
BRANCH=none
TEST=Enable spi_flash commands. Select AP ROM and verify spi_flashinfo,
read, erase, and write commands work properly. Select EC ROM and verify
the same commands.
Change-Id: I16c55015794f8513effe0fa5712488a84bed2627
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339844
Reviewed-by: Shawn N <shawnn@chromium.org>
This patch adds support for console on LPUART (low power UART).
It is wired to the USB type B port on the board, which is also one of the
power sources. So, using LPUART simplifies the set up.
BUG=none
BRANCH=tot
TEST=Verified console works on stm32l476g-eval. make buildall
Change-Id: Iccf697cfabdcb7e1362d8453708eb79610d2e0cb
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340101
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch adds initial set of files to bring up STM32L476G-Eval board.
BUG=none
BRANCH=tot
TEST=Tested console. make buildall && make tests
Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/340100
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This add modifications for EVT, including:
- Use SPI for KX022 motion sensor on the daughterboard
- remove TMP432
- Use PF2 to control the external power of ANX7688
BRANCH=none
BUG=chrome-os-partner:52245
TEST=make BOARD=elm -j
Change-Id: I7d4021746bc8a2be0028076a5c3aeefd8736c1b0
Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/337338
Reviewed-by: Rong Chang <rongchang@chromium.org>
This change adds files to support nucleo-f072rb. This board can be used as
a DUT to test STM32F072.
BUG=none
BRANCH=tot
TEST=Verified EC console works. Flashed the board by 'make flash'. User LED
brinks periodically and when user button is pressed.
make buildall && make tests
Change-Id: I628f229b62c4b06d19d8245121f79a13e17bc2e9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/338461
Prime generation uses a sieve to amortize division
with small primes. Otherwise this a standard
Miller-Rabin implementation.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests under test/tpm2 pass
Change-Id: I9f84d1f9c911f6146e4bd80296f75157a191552d
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/335222
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
points_mul (variable time) is only necessary for
ECDSA verification, and is not required as part of
the public dcrypto API. Replaced wih (constant time)
point_mul, and add corresponding parameter checks to
the tpm2 interface call _cpri__EccPointMultiply.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I4ec885c147755e8a645c51b9a461b81c3a3b310f
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/338851
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Implement _cpri__TestKeyRSA, which computes
the modulus and private exponent given a
pair of primes, or computes the second prime
and private exponent given the modulus and
one prime.
The _cpri__TestKeyRSA call is used to determine
whether the components of an RSA key match each other.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I2c68d844f4bab207588cbda5c962b09078519a1a
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/330466
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
AES CTR will be necessary to implement hybrid encryption
and hence needs to be a part of the dcrypto library.
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
TEST=tests in test/tpm/tpmtest.py pass
Change-Id: I5dffe5d3a15748614db36aebdbcd50bde31bfdb2
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/339561
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
