This change adds support for signing SHA-384 & 512 hashes
when using PKCS#1 padding (CR50 does not support
SHA-384 & 512 at the moment, the actual hashing is to be
done on the host).
BRANCH=none
BUG=chrome-os-partner:59754
TEST=TCG tests pass
Change-Id: I78e774639a7968cbb50e58cdd0bf479e64123630
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/415218
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
On the bd9995*, back boosting may occur when actual battery voltage
drops below VBAT register setting. Maintain the VBAT register at the
battery-requested charge voltage even when not charging to ensure the
bd9995* doesn't become a back boosted animal.
BUG=chrome-os-partner:56139,chrome-os-partner:54248
BRANCH=gru
TEST=Manual on kevin, unplug AC, run 'charger', verify that 'V_batt' is
maintained at 8688 mV. Attach charger, verify 'V_batt' stays at 8688 mV
and device charges.
Change-Id: Ia0cc7f9279cb460e20a8faf332ad432067dc5482
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400087
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Enabling and disabling sleep in the rdd interrupt is redundant because
USB already takes care of that. When USB is initialized it will disable
sleep. If it is released or suspended then it will re-enable sleep. This
change removes the sleep enable and disable from the rdd interrupt. With
this change now sleep can be enabled while suzyq is still plugged in
using the command 'ccd disable'.
BUG=none
BRANCH=none
TEST=manual
The consoles still work
Updating the EC, AP and Cr50 still works
After running 'reboot ap-off' in the EC console and 'ccd
disable' in the Cr50 console Cr50 will go to sleep.
Change-Id: Ie8e6201e9fd611c514e93bc70d298d3b0d228611
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413606
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This patch introduces version 6 of the cr50 USB update protocol. This
version allows to multiplex TPM vendor and extension commands over the
same USB endpoint which is used for firmware updates.
When channeling TPM vendor commands the USB update frame looks as follows:
4 bytes 4 bytes 4 bytes 2 bytes variable size
+-----------+--------------+---------------+-----------+------~~~-------+
+ total size| block digest | EXT_CMD | Vend. sub.| data |
+-----------+--------------+---------------+-----------+------~~~-------+
Where 'Vend. sub' is the vendor subcommand, and data field is
subcommand dependent. The target tells between update PDUs and
encapsulated vendor subcommands by looking at the EXT_CMD value - it
is set to 0xbaccd00a and as such is guaranteed not to be a valid
update PDU destination address.
In the previous protocol versions target reset was requested by the
host sending a 4 byte PDU after the target receives the UPGRADE_DONE
message and moves the state machine to the 'awaiting_reset' state.
With the ability to transfer vendor commands, there is no need for the
target to have a special state for reset. The host can send the posted
or immediate reboot request using the appropriate vendor command.
As a result the 'awaiting_reset' state has been removed, the target
accepts vendor commands only when state machine is in the rx_idle
state.
Vendor command response size is not fixed, it is subcommand dependent.
In the current implementation the total size of the vendor command PDU
can not exceed 64 bytes, as there is no reassembly on the target side.
For backwards compatibility in case the target is running protocol
version earlier than 6, the 4 byte PDU is still sent to the target
after UPGRADE_DONE is sent.
BRANCH=none
BUG=chrome-os-partner:60013
TEST=tested updates on Reef and Gru, observed that it is possible to
update earlier versions of firmware, and that it is possible to
request immediate and posted reset (depending on the presence of
the -u flag in the usb_updater invocation).
Change-Id: I6ea9e9f742c96b8ab0670e9cec87a83cd47bb20e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414948
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When usb update errors happen it helps a lot to be able to see the
actual error code returned by the target and where the error was
generated.
This patch adds a few printouts to help with debugging.
BRANCH=none
BUG=none
TEST=observed proper error messages generated while debugging
introduction of extension/vendor commands transfer over USB.
Change-Id: I06c77e7467f7f9547704c88c4b673866fb2e6032
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414947
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Until extension commands using incompatible TPM command code are
phased out, the function sending vendor/extension commands to the TPM
needs to be aware of the subcommand code and use the matching TPM
command code.
BRANCH=none
BUG=chrome-os-partner:60013
TEST=with the rest of the patches applied both posted and immediate
reset commands operate on Gru as expected.
Change-Id: I8977df22e4c2fadfd3427c0b4f70035f7f532e00
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414946
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Let's make sure that both embedded and host side use the same command
definitions. To avoid host compilation problems move the definitions
into a separate file.
BRANCH=none
BUG=none
TEST=compilation still works.
Change-Id: Id0d85a51aebabed0637965b3b19d7ed42c46e75e
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414945
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Cr50 updates in development environment should allow resetting the
device immediately after update (without the need for SYS_RST_L to be
toggled).
This patch adds a vendor command to do just that.
BRANCH=none
BUG=chrome-os-partner:60013. chrome-os-partner:60321
TEST=none yet, with the rest of the patches applied the target gets
rebooted immediately after a cr50 code update. Also, observed
that flashing the console does not quite work, opend
crosbug.com/p/60321 to address this.
Change-Id: Ia6f99ad6d22004347ad02aac2cbf4dd6c5594928
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414442
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Some upcoming changes will introduce transfer of vendor and extension
commands over the usb updater endpoint.
This patch exposes a function which allows to verify integrity of
received USB PDUs.
BRANCH=none
BUG=chrome-os-partner:60013
TEST=no functional changes, usb_updater still works fine.
Change-Id: I8d9e6746ef0dfbb17bba618410514ca047a59a45
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414441
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Just for consistency sake, make all normal messages generated by the
utility in the course of firmware update start with lower case letters
and all error messages start with upper case letters.
BRANCH=none
BUG=none
TEST=make buildall -j still succeeds
Change-Id: Ifb0bd8dec4c2bb5cbbb2c93b1918fc699c2f33dd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414944
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This is just a clean up patch, unifying all cases where endian
conversions are used in the usb updater source code.
BRANCH=none
BUG=none
TEST=usb update of cr50 is still possible on gru (which uses the code
being changed).
Change-Id: I362e9762493854b4fdbb9ec15c2cb363003f258a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414443
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
When the battery is fully charged or not charging, upon removal of
the AC, discharge takes long time. To overcome this issue suspend
the DC-DC converter when discharging on AC.
BUG=chrome-os-partner:58969
BRANCH=none
TEST=Manually tested on reef. Discharge is in the permissible range.
'chgstate' console command prints correct values.
Change-Id: I64afa992e50b6e18daf43edf237fde8cf658a8a2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/413153
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This reverts commit c459c8278e
as the fix is not straightforwad, some host command codes in
private repos are expressed using C preprecessor which
breaks the assumption of this patch that all host commands
are expressed as four digit hex numbers.
Change-Id: I922de9ae8dbab6eef048463c5c09b1f338152083
Reviewed-on: https://chromium-review.googlesource.com/414492
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Because the virtual dev-mode switch is stored in the TPM, when we erase
the TPM memory prior to unlocking the Cr50 console on reboot the system
reinitializes itself in normal mode. This is by design (Chromebooks
should fail into a more-secure state when possible), but it can be
unexpected.
This adds some extra caution to the unlock warning message, so that
owners who are fiddling with it for the first time aren't unpleasantly
surprised by losing all their work.
BUG=chrome-os-partner:57407
BRANCH=none
TEST=make buildall; test on Reef
From the Cr50 console, run
lock on
lock off
Observe the new, scarier warning.
Change-Id: I6fd1248a5a4c131fa107a902a4539fa73f2308f6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/414387
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Use binary search in host command lookup dispatcher
BUG=chrome-os-partner:570895
TEST=manual testing on kevin
- Kevin boots
- ectool hello
make buildall -j
Verify *.smap hcmds section is sorted:
100bca94 R __hcmds
100bca94 R __host_cmd_0x0000
100bcaa0 R __host_cmd_0x0001
100bcaac R __host_cmd_0x0002
100bcab8 R __host_cmd_0x0003
100bcac4 R __host_cmd_0x0004
100bcad0 R __host_cmd_0x0005
100bcadc R __host_cmd_0x0006
100bcae8 R __host_cmd_0x0007
100bcaf4 R __host_cmd_0x0008
100bcb00 R __host_cmd_0x0009
100bcb0c R __host_cmd_0x000a
100bcb18 R __host_cmd_0x000b
100bcb24 R __host_cmd_0x000d
100bcb30 R __host_cmd_0x0010
100bcb3c R __host_cmd_0x0011
100bcb48 R __host_cmd_0x0012
100bcb54 R __host_cmd_0x0013
100bcb60 R __host_cmd_0x0015
100bcb6c R __host_cmd_0x0016
100bcb78 R __host_cmd_0x0017
100bcb84 R __host_cmd_0x0025
100bcb90 R __host_cmd_0x0026
100bcb9c R __host_cmd_0x0029
100bcba8 R __host_cmd_0x002a
100bcbb4 R __host_cmd_0x002b
100bcbc0 R __host_cmd_0x002c
100bcbcc R __host_cmd_0x0044
100bcbd8 R __host_cmd_0x0045
100bcbe4 R __host_cmd_0x0046
100bcbf0 R __host_cmd_0x0047
100bcbfc R __host_cmd_0x0061
100bcc08 R __host_cmd_0x0062
100bcc14 R __host_cmd_0x0064
100bcc20 R __host_cmd_0x0065
100bcc2c R __host_cmd_0x0067
100bcc38 R __host_cmd_0x0087
100bcc44 R __host_cmd_0x008c
100bcc50 R __host_cmd_0x008d
100bcc5c R __host_cmd_0x008f
100bcc68 R __host_cmd_0x0092
100bcc74 R __host_cmd_0x0093
100bcc80 R __host_cmd_0x0096
100bcc8c R __host_cmd_0x0097
100bcc98 R __host_cmd_0x0098
100bcca4 R __host_cmd_0x0099
100bccb0 R __host_cmd_0x009e
100bccbc R __host_cmd_0x00a0
100bccc8 R __host_cmd_0x00a1
100bccd4 R __host_cmd_0x00a8
100bcce0 R __host_cmd_0x00a9
100bccec R __host_cmd_0x00b6
100bccf8 R __host_cmd_0x00b7
100bcd04 R __host_cmd_0x00d2
100bcd10 R __host_cmd_0x00d3
100bcd1c R __host_cmd_0x00db
100bcd28 R __host_cmd_0x0101
100bcd34 R __host_cmd_0x0102
100bcd40 R __host_cmd_0x0103
100bcd4c R __host_cmd_0x0104
100bcd58 R __host_cmd_0x0110
100bcd64 R __host_cmd_0x0111
100bcd70 R __host_cmd_0x0112
100bcd7c R __host_cmd_0x0113
100bcd88 R __host_cmd_0x0114
100bcd94 R __host_cmd_0x0115
100bcda0 R __host_cmd_0x0116
100bcdac R __host_cmd_0x0117
100bcdb8 R __host_cmd_0x0118
100bcdc4 R __host_cmd_0x011a
100bcdd0 R __evt_src_EC_MKBP_EVENT_KEY_MATRIX
100bcdd0 R __hcmds_end
BRANCH=none
Change-Id: Ideb9951b318763f71915e2c4e5052f4b4bfab173
Reviewed-on: https://chromium-review.googlesource.com/405528
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch enables an interrupt handler for BMI160. This will improve
response time of the motion sense task.
BUG=None
BRANCH=none
TEST=Install and run AIDA64 from Playstore. Wiggle Reef DVT. Verify
'CrosEC Gyroscope' readings change.
Change-Id: Ie8dacb51795fa194840817d833cc6356beb01c8f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413079
This describes a 5-finger touchpad. The physical/logical dimensions
of the trackpad are hardcoded for the time being.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
Change-Id: I04a0833a28c013395974104ebdd6fcb29e5d6680
Reviewed-on: https://chromium-review.googlesource.com/407742
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
For example, when a HID descriptor is longer than 64 bytes, we need
to split it in multiple packets.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make buildall -j
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
Change-Id: I25a05eabaf9413e332fe3cd70695a0d53639713d
Reviewed-on: https://chromium-review.googlesource.com/409316
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Mark host command structures as aligned for elm board.
Without marking as aligned, llvm was correctly complaining about
taking address of packed member.
util/ectool.c:1158 error: taking address of packed member 'size' of
class or structure 'ec_params_usb_pd_fw_update' may result in an
unaligned pointer value [-Werror,-Waddress-of-packed-member]
BRANCH=none
BUG=chromium:665240
TEST=Builds now
Change-Id: Ic4a2e81f6af8ef2a906d6ac7aca87ea6d00fe318
Reviewed-on: https://chromium-review.googlesource.com/413108
Commit-Ready: Manoj Gupta <manojgupta@chromium.org>
Tested-by: Manoj Gupta <manojgupta@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Enabling/Dislabling keyboard and touchpad is required to prevent EC
from waking up the system from S3 in tablet mode.
This change disables the keyboard and the trackpad when the lid goes
beyond 180 degree.
Keyboard and touchpad are also enabled/disabled by the tablet switch.
When the lid reaches 360 position, keyboard and touchpad are disabled.
And they stay disabled as long as the lid stays at 360 position.
This prevents keyboard and touchpad from turning on by the (faulty) lid
angle calculation.
BUG=chrome-os-partner:58792
BRANCH=none
TEST=Keyboard and trackpad are disabled when the lid goes beyond 180
and re-enabled when it's smaller than 180. Keyboard and trackpad are
disabled when the lid goes to 360 degree and the system doesn't wake
up by a keypress.
Change-Id: I48c04bd576f457a899dfdf9b4718d73b59419cbe
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/411395
This first cleans up the code:
- Define report as a structure.
- Fix USB interval from 40 ms to 32 ms (Linux kernel complains
otherwise).
Then, this removes the old set_keyboard_report interface, and
replaces it by the interface used by the keyboard scanner
(i.e. keyboard_state_changed and keyboard_clear_buffer).
This also means we need a keycode table to translate from
row/column to USB HID keycode.
BRANCH=none
BUG=chrome-os-partner:59083
TEST=make buildall -j
TEST=make BOARD=hammer -j && util/flash_ec --board=hammer
With evtest and "hid 0-7" in console, check that key are
reported correctly.
Change-Id: I5d526db1568c29c7f28fc5e962e213e44303cc16
Reviewed-on: https://chromium-review.googlesource.com/411571
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When cr50 rollback happens, the newer header's magic field is set to
zero to prevent it from ever running again.
Take this into consideration when displaying versions of the inactive
RW image.
BRANCH=none
BUG=none
TEST=loaded two versions of the new code on a cr50 and then modified
the fallback counter to force it to boot the older version and
reboot a Reef. Once Reef fully boots to chrome os examine CR50
version report:
Before:
> vers
...
RW_A: 0.0.9/DEV/cr50_v1.1.5654-2228b76+
RW_B: * 0.0.11/DEV/cr50_v1.1.5654-2228b76+
...
After:
> vers
...
RW_A: * 0.0.9/DEV/cr50_v1.1.5654-2228b76+
RW_B: Error
Change-Id: I2a9ee13117a0bc91710226cd733c5c484c6d0595
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413089
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Electro & Reef use the same board files but have different batteries
hence configure the respective battery parameters for these boards.
BUG=chrome-os-partner:59876
BRANCH=none
TEST=Manually tested on Reef. Boot with/without/battery works.
cut-off and boot from cut-off works.
Change-Id: I0e4684987133d6bcd9cabab5c5a1ce5b6c5684d2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/411353
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The mux for selecting source clock of ITIM will introduce a delay
and have a chance to make ITIM's source clock and core clock are
asynchronous. We need consecutive reading for ITCNT32 no matter source
clock is APB2 or 32k.
Modified sources:
1. hwtimer.c: Add consecutive reading for ITCNT32
BRANCH=none
BUG=chrome-os-partner:34346,chrome-os-partner:59240
TEST=No time stamp symptoms occur on wheatley for 30 hours.
Change-Id: I8b54e93b320e3ea74fc3d6ea13f0d178f9c449cd
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/412505
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When "make buildall" has board which uses core/minute-ia,
CROSS_COMPILE?=i686-pc-linux-gnu- doesn't get set unless
CROSS_COMPILE is not defined; however, it's defined before
this line, and wrong toolchain is used.
Remove "?" to set correct CROSS_COMPILE.
BUG=none
BRANCH=none
TEST='make buildall -j' passed
Change-Id: Ied4a9f93a4d44714c012d3a3e50e4a34f41a7c1f
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/410402
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rereading the specification, remove delays when not needed:
- When we move the sensor out of suspend, we need to wait before
using it (BMI160 spec: 2.11.38 Register (0x7E) CMD)
When we do a softreset, we need just need to wait 300us for the
sensor to go in suspend, we will wait only when we change the rate
and enable the sensor.
- The timeout at fifo flush is not needed, it was added for debugging.
- Remove unnecessary printf when initializing the magnetometer.
BUG=chrome-os-partner:59188
BRANCH=glados, reef, strago
TEST=On reef, check the EC boot faster: time spend initializing the
sensors
decreased from 240ms to 133ms
Change-Id: Ia80232da42aa705df819a4988da483a344ffcbb4
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/411964
Commit-Ready: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The button closer to the hinge is assigned to volume down and
the one closer to the user is assigned to volume up. This change
swaps the GPIO assignments to fix the UX.
BUG=chrome-os-partner:60057
BRANCH=none
TEST=Verified the one closer to the hinge increases the volume and
the one closer to the user descreases the volume.
Change-Id: I3e716da288839c3f5be608fb2d63f277bbde1bc7
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412981
The pulldown on diob5 is used to detect when servo is detached. It is
unnecessary during deep sleep and when the EC console is active because
servo detection is disabled. Having the pull-down enabled during these
times can increase power consumption.
This change disables the pulldown when the EC console and deep sleep are
enabled. It also disables the diob5 input during deep sleep.
BUG=chrome-os-partner:60020
BRANCH=none
TEST=manual
Disconnect servo
Use the suzyq consoles to turn off the AP.
Enable deep sleep.
Measure the power consumed by vddiob and make sure it is around
0.3mW when the EC is in hibernate and when it is not.
Change-Id: I8a653c28800cfbeeb1b4b8598d166846124c6b53
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412940
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This returns the system information that is needed to determine the
correct signing keys for firmware updates.
BUG=chrome-os-partner:59747
BUG=chrome-os-partner:59705
BRANCH=none
TEST=make buildall; test on Reef
Run the "sysinfo" command on the Cr50 console:
> sysinfo
Reset flags: 0x00000800 (hard)
Chip: g cr50 B2
RO keyid: 0x3716ee6b(dev)
RW keyid: 0xb93d6539(dev)
DEV_ID: 0x017950ab 0x04656742
>
Send the raw command bytes from the Reef AP, observe the result:
# /tmp/trunks_send --raw 80 01 00 00 00 0C 20 00 00 00 00 12
80010000001C0000000000123716EE6BB93D6539017950AB04656742
#
The result contains the same information from the console command:
8001 TPM_ST_NO_SESSIONS
0000001C responseSize (28 bytes)
00000000 RC_SUCCESS
0012 vendor-specific subcommand
3716EE6B RO keyid
B93D6539 RW keyid
017950AB DEV_ID0
04656742 DEV_ID1
Change-Id: I82de3ebfb3e9be3b707583bc825d2efbcf851c5c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/413106
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Cr50 has an internal pull down. This change changes the PULL_UP on KSO2
to a PULL_DOWN to match Cr50.
BUG=chrome-os-partner:60020
BRANCH=none
TEST=poweroff the AP, put the EC in hibernate, and verify when cr50
enters deep sleep it consumes around 0.6mW on vddiom.
Change-Id: I017094c185f616e018f121ac3ffb0521892aafa1
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412947
Reviewed-by: Shawn N <shawnn@chromium.org>
When the console is unlocked, the function nvmem_wipe_or_reboot()
is called. This holds the EC in reset, clears nvmem, resets the
TPM task, then releases the EC. Nothing about that should cause
the Cr50 to reboot, but it was happening anyway.
This CL addresses several subtle problems.
First, holding the EC in reset invoked the sys_rst_asserted()
interrupt handler, triggering extra (and early) calls to
tpm_reset(). That should wait until after nvmem is cleared, and
only be called once.
Second, the intentional call to tpm_reset() caused the current
(HOOKS) task to wait for the operation to finish, but it didn't
wait long enough (recreating the endorsement certs can take over
a second). When the task_wake_event() returned, a timeout was
indicated in addition to the completion event.
Third, because we checked for the timeout first, we reported an
error even though tpm_reset() completed successfully, just slower
than we expected. We didn't get the timeout event before it
completed because the TPM task runs at a higher priority.
This CL addresses all of these cases, and makes wiping nvmem the
responsibility of the TPM task as well, so that it can do it when it's
ready.
Note that the EC (and thus AP too) will be held in reset while nvmem is
erased.
BUG=chrome-os-partner:59902
BRANCH=none
TEST=make buildall, manual tests
From the Cr50 console, run the "lock on" and "lock off" commands.
Try it both with and without the battery present. Observe that
the Cr50 no longer reboots just because the console unlocks.
Change-Id: I65a342502718acc5b9bda8c6f28dcd27e8f027f7
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/411379
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Charger BGATE is off on POR hence the voltage to the battery pack is
not applied immediately from the VBUS. To overcome this issue, BGATE
is turned on (CHG_EN) at charger initialization. If the voltage across
VBATT is high but I2C is still failing, battery is booting from ship
mode hence overwrite the battery as not present till I2C on battery
is success and INIT bit is set.
BUG=chrome-os-partner:59308
BRANCH=none
TEST=Reef can boot to OS from shipmode battery.
Change-Id: If1b212612e27fd65a822675a9609f0a8c03d8add
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/411360
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the battery charging is not allowed and charging at high load
audible noise is observed from the BD9995X charger. To prevent this
issue enable the battery-learn mode when battery charging is not
allowed.
This audible noise is related to the fact that in light load (<450mA
being withdrawn from VSYS) the DCDC of the charger operates
intermittently i.e. DCDC switches continuously and then stops to
regulate the output voltage and current, and sometimes to prevent
reverse current from flowing to the input. This causes a slight
voltage ripple on VSYS that falls in the audible noise frequency
(single digit kHz range). This small ripple generates audible noise
in the output ceramic capacitors (caps on VSYS and any input of DCDC
under VSYS).
BUG=chrome-os-partner:56695
BRANCH=none
TEST=When battery charging not allowed, battery is put in battery
learn-mode & audible noise is not observed.
Change-Id: Ia22779fe4cf70dd9dd4f799a9698264e44c4c7d2
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/412382
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the host requests the uploader to post a reboot request, the
uploader should exit right away once the request is posted.
BRANCH=none
BUG=chrome-os-partner:59911
TEST=verified that cr50 gets successfully updated from this image to a
newer one on both reef and gru: the reboot happens under upstart
control, not by cr50 rebooting on its own.
Change-Id: I9e4a2da686fe512b633daa05c675871e5946926f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412348
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
The 'cycles' register will be clobbered by our macro, so it must be
specified as an output operand that may also be used as input.
BUG=chrome-os-partner:60000
BRANCH=gru,strago,glados
TEST=Build + burn wheatley, verify alignment exception is not
encountered on boot. Also verify produced assembly is still correct:
100a89a6: 2303 movs r3, #3
100a89a8: 3b01 subs r3, #1
100a89aa: d1fd bne.n 100a89a8
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I1be03a006967aed6970dbac5d98a19a31e0b7d49
Reviewed-on: https://chromium-review.googlesource.com/412441
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
File-scoped variables in common/tpm_registers.c must be handled
specially to avoid unexpected behavior when calling tpm_reset().
Enhance the comments and add a couple of macros to help explain
it better.
BUG=none
BRANCH=none
TEST=make buildall; Run on Reef
This is just commenting and code cleanup. No changes in behavior
are expected; none are observed.
Change-Id: If70e56d00642a11df7b5ceb5d5d32c485236f7a8
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/412407
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This patch changes the entry/exit model for S0ix from a PCH
SLP_S0 signal based model to a hybrid host event/direct interrupt
model. The kernel will send host events on kernel freeze/thaw exit;
EC will initiate the S0ix entry based on host command and exit via
another host command from kernel.
The assertion of SLP_S0 comes later than HC(suspend) and deasserion
of SLP_S0 comes earlier than HC(resume).
________ ________
SLP_S0 |______________________|
_____ ________
HC |___________________________|
BRANCH=none
BUG=chrome-os-partner:58740
TEST=Build/flash EC and check 'echo freeze > /sys/power/state'
command in OS shell. Verify idle state transitions during display off
and periodic wakes from S0ix do not lead to state transitions in EC.
Change-Id: Ie18c6c2ac8998f59141641567d1d740cd72c2d2e
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Archana Patni <archana.patni@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/401072
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
