It is useful for the updater to be able to determine which region
is active without having to use the update interface.
BRANCH=none
BUG=b:35587171
TEST=lsusb -d 18d1:5022 -v -v | grep hammer shows either:
RO:hammer_v1.1.6441-e58472daf+ or
RW:hammer_v1.1.6441-e58472daf+
depending on the image used
Change-Id: I8e1acfbc546330e10ba650b743e3a4c9986b0c30
Reviewed-on: https://chromium-review.googlesource.com/515242
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
As part of the pairing process, AP needs to be able to inject
some entropy into the base.
Let's also define PAIR_CHALLENGE, which will be implemented in
a later CL.
BRANCH=none
BUG=b:38487027
TEST=Flash hammer. On host, reboot hammer to RO:
usb_updater2 -r; sleep 0.5; usb_updater2 -s
usb_updater2 -e (adds entropy)
EC console: check that rollbackinfo shows secret is updated
Change-Id: I964bb578c6bfbb1ab5105a70b43682d51df4ed47
Reviewed-on: https://chromium-review.googlesource.com/513807
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Newer Eve boards will lose VBAT on power cycle and therefore cannot
successfully save the reset flag state.
Implement the workaround that will allow these boards to continue to
work for FAFT testing by indicating to the skylake chipset power code
that it should skip the PMIC reset when doing 'reboot ap-off'.
BUG=b:35585876
BRANCH=none
TEST=manual testing on Eve: execute 'reboot ap-off' and ensure that the
AP does not power on. Also ensure that 'dut-control power_state:rec' works
as expected and does not power off at the recovery screen due to a power
button press.
Change-Id: Ida1563593d802c00280a55a0d24a504c25fab532
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514504
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Some hardware has an issue where the reset flags are lost on power cycle
because the EC backup ram loses power. This causes the flag to not power
on the AP (ap-off) to be lost.
In order to pass FAFT it is required that boards support this flag, so
this commit adds a workaround where the skylake chipset code will call into
the board to ask if it has working reset flags and if not it will skip the
PMIC reset if the "ap-off" flag has been set.
The "ap-off" flag is purely for testing, it is not possible for users to
do this without having access to the EC console. (which is currently not
possible at all with CCD unless you can also build a debug cr50 image)
BUG=b:38187362,b:35585876
BRANCH=none
TEST=manual testing on Eve: execute 'reboot ap-off' and ensure that the
AP does not power on. Also ensure that 'dut-control power_state:rec' works
as expected and does not power off at the recovery screen due to a power
button press.
Change-Id: If11e17179e9173509b9a6ae1ef0d94a50ba181d0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514503
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
With the updated scancode matrix the keymask needs to be adjusted to
not mask off these particular keys.
BUG=b:36735408
BRANCH=none
TEST=build and boot on Eve
TEST=kbpress 0 3 1; kbpress 0 3 0 reports KEY_LEFTMETA as expected
TEST=kbpress 0 5 1; kbpress 0 5 0 reports MSC_SCAN but no key yet
(as expected because the kernel does not handle it yet)
Change-Id: Iba78741b8a0cd1248a799cf5219cee59ea6630ec
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/514502
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The trimmed value of CC parameter setting registers
(port0: ff3760h ~ ff3763h, port1: ff3860h ~ ff3863h)
will be reset to default after a soft reset (system_reset()).
BRANCH=none
BUG=none
TEST=Console command 'reboot' and checking if the value of
cc parameter setting registers are correct (trimmed).
Change-Id: Ibf9c72e8aeef36701d72bcb64529735295295cdf
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/513744
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously, result codes were being stored as `enum ec_status` values.
The compiler was forcing this value to only be one byte large, since
that's all that was necessary to represent all the values of that
enum.
This change fixes this bug by switching result code variable types from
`enum ec_status` to `uint16_t`.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Iacdca51dc6c1de677d2fbb59ad6dd2572d21ea7f
Reviewed-on: https://chromium-review.googlesource.com/513609
Commit-Ready: Jeff Andersen <jeffandersen@google.com>
Tested-by: Jeff Andersen <jeffandersen@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
For pairing purpose, we want to store some secret random number in
the base. The most convenient location for this is the rollback
region.
Since the rollback region can now be updated without incrementing
rollback_min_version (when we add entropy to the secret), we need
to add an increasing id to tell the code which rollback region is
the latest.
We also add console commands to manually add entropy.
BRANCH=none
BUG=b:38486828
TEST=Flash hammer (with or without CONFIG_ROLLBACK_ENTROPY_SIZE set)
rollbackinfo => 1 version 0 block, 1 empty block, RW verifies
correctly.
rollbackupdate 0; rollbackinfo => No change
rollbackupdate 1; reboot => RO refuses to jump to RW
only when CONFIG_ROLLBACK_ENTROPY_SIZE is set:
rollbackinfo => Secret is [00..00] on both blocks (so the data
was copied correctly)
rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate
between the 2 blocks.
rollbackupdate 2 => Refuses to downgrade version
TEST=From blank secret [00..00], 'rollbackaddent Hello' updates it
to [ba..fa], which matches the output of:
(dd if=/dev/zero bs=1 count=32; echo -n Hello) | sha256sum
Change-Id: I79c3e790e56e21958cc1b4ba05bd4e5f359d3090
Reviewed-on: https://chromium-review.googlesource.com/511985
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
utils test is a little too large for hammer's small RO, so we split
it in 2 test: utils and utils_str. Instead of one test that requires
about 8kb extra flash, we have 2 tests that take respectively
3.4kb (utils_str) and 4.6kb (utils) of extra flash.
BRANCH=none
BUG=chromium:726113
TEST=make BOARD=hammer tests -j
util/flash_ec --board=hammer --image=build/hammer/test-utils.bin
runtest => pass
Repeat with test-utils_str.bin
TEST=Before this change:
make runtests -j
./util/run_host_test utils | grep Running | sort > old
Apply this change:
make runtests -j
(./util/run_host_test utils; ./util/run_host_test utils_str) \
| grep Running | sort > new
diff old new => No difference (except timing)
Change-Id: I917d572e671d6ce0a8799508761f55de7bd83133
Reviewed-on: https://chromium-review.googlesource.com/514604
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Add console and usb_spi commands to enable or disable IOs
to the socket, so that it will not be powered if a chip is inserted,
and control reset and boot_cfg.
BUG=b:36910757
BRANCH=None
TEST=Check no voltage when socket is disabled. Full spiflash compatibility.
Change-Id: Ie4ce0613a868030833abfdccd827acce2753dc6f
Reviewed-on: https://chromium-review.googlesource.com/509072
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This patch sets GPIO_LAN_PWR_EN to output/high to power on
the ethernet port at start.
BUG=b:37646105
BRANCH=none
TEST=Measured V3P3A_LAN is 3.3V.
Change-Id: I9629a72d1ffefd1ca2aeb8d2d1f5d74a953d7e58
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/514622
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Fizz needs to set available power on type-c/pd before PD task starts.
PD task tries to reset available power at start-up. This patch prevents
those reset attempts from disabling already initialized power sources.
BUG=b:37316498
BRANCH=none
TEST=Boot Fizz on barrel jack and type-c adapters
Change-Id: I807f9d5ae4b4530fa80479b4e1a669569be841c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513582
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
ANX has specific sequencing requirements for PWR_EN and RESETN when
entering active and standby modes. The order in which the two GPIOs
were set did not match the spec. Update board_set_tcpc_power_mode to
ensure correct ordering for both the modes.
BUG=b:62043928
BRANCH=None
TEST=make -j buildall
Change-Id: Ifc2991da87c7b7facd3384f752792371efb9fe1e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513477
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This change sets the initial power button state to init-on
if the power button is pressed.
BUG=b:37274183
BRANCH=none
TEST=Enter recovery mode by power+recovery button press.
Change-Id: I6ed849bc303e7cdbcb975ae2a6ff278093c86088
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486946
Reviewed-by: Duncan Laurie <dlaurie@google.com>
We need to process the stop condition after slaver receiver is executed,
or else we will lost the last byte of the transmission.
BRANCH=none
BUG=b:38510075
TEST=`make BOARD=rose -j`, AP suspend/resume should complete within 3 secs
Change-Id: I6390a908b6c05b875b8bb2c0a124292785110b20
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/512463
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Allow to configure the sensor to detect autonomously finger touch event
similar to what is done in the suspend() routine of the kernel fpc1020
driver.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35648259
TEST=make BOARD=eve_fp
Change-Id: I8b78bd6bdeecd8658850383417c950d9025fdf40
Reviewed-on: https://chromium-review.googlesource.com/491072
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Move the existing fingerprint host command in the driver and
add more of them to prepare the new fingerprint architecture.
The commands are mostly stubbed for now.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
CQ-DEPEND=*364728
BRANCH=none
BUG=b:35648259
TEST=make BOARD=eve_fp (with and without a private repository)
do a fingerprint image capture with 'fptest'.
Change-Id: Ie17a5fde2d6470c6272e8059bddc845cea07aff2
Reviewed-on: https://chromium-review.googlesource.com/491071
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Typically, we do not need RW section to be able to update rollback
information (rollback block should be protected when RW is running),
so we can save some flash space by undefining this option.
BRANCH=none
BUG=b:35586219
TEST=make newsizes saves ~420 bytes on hammer and staff.
Change-Id: Ic457673e56ace083f2ebb1ca0f37f54bf125bfa4
Reviewed-on: https://chromium-review.googlesource.com/511983
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We want to always be able to update cr50 image to a newer version,
even if the AP is not cooperating.
BRANCH=cr50
BUG=b:35580805
TEST=verified that update of a prod image is possible
Change-Id: I3bbe2c4aca8bf0c3129f4495db0e76405a2ed189
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/511285
Reviewed-by: Nick Sanders <nsanders@chromium.org>
This is copied chip/g version as of commit 0e5497db6, plus the following
uncommited usb_update patch (CL:458469):
a0176a1cc usb_updater: Flush all data from endpoint before trying to update
On top of that, a good number of common-code specific modifications are
added: new extra commands, new first_response_pdu format, use of FMAP.
BRANCH=none
BUG=b:35587170
TEST=usb_updater binary identical before and after this change.
TEST=make BOARD=hammer -j && \
( cd extra/usb_updater && make && \
time sudo ./usb_updater2 ../../build/hammer/ec.bin )
TEST=cd extra/usb_updater; make
# Jump to RW
sudo ./usb_updater2 -j
sleep 0.5
# Update RO, then reboot
sudo ./usb_updater2 ../../build/hammer/ec.bin
sleep 0.5
# Update RW (first tell RO to not jump to RW)
sudo ./usb_updater2 -s
sudo ./usb_updater2 ../../build/hammer/ec.bin
TEST=cd extra/usb_updater; make
# Tell RW to jump back to RO
sudo ./usb_updater2 -w
sleep 0.5
# Update RW, then reboot
sudo ./usb_updater2 -s
sudo ./usb_updater2 ../../build/hammer/ec.bin
TEST=usb_updater2 can update hammer, and read its version, rollback
version and key version.
Change-Id: I09da894d83e2b4d6c2e46cab301522c27fa0160c
Reviewed-on: https://chromium-review.googlesource.com/458468
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
In old system driver, ec clears "Predefined Time Occurred" (PTO) flag
before setting a new alarm (PT field in WTC). If PT field is the same
as the first 25 TTC bits at this moment, we might receive unexpected
rtc interrupt again. This CL sets new alarm first then clears PTO flag
to make sure rtc interrupt is issued from new alarm.
BRANCH=none
BUG=b:38310685
TEST=Duplicated the same symptom by the script in issue 38310685 on
gru. No symptoms occurred with the same script for 3 hours by applying
this CL.
Change-Id: Ia6410d6aa4ef8e2acb7bfadf9192d619045bfa58
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/508572
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Make the dcrypto ecdsa verify code check that r,s are in range, and
not depend on the caller C code to have done so.
For instance, s equal to 0 would result in infinite loop during
computation of its modular inverse.
BRANCH=none
BUG=b:35587381
TEST=TCG tests pass
Change-Id: I13f7811be030aed9feaa11c45dc68d4bfd08fb76
Reviewed-on: https://chromium-review.googlesource.com/508819
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Adds min_frequency and max_frequency to struct motion_sensor_t.
New attributes min_frequency and max_frequency are now returned in
ectool's MOTIONSENSE_CMD_INFO response.
Incremented ectool's MOTIONSENSE_CMD_INFO version to version 3.
Add constants for MIN_FREQUENCY and MAX_FREQUENCY to each sensor's
header file.
BRANCH=none
BUG=chromium:615059
TEST=build/boot and verify MOTIONSENSE_CMD_INFO response on kevin,
make buildall -j passes.
Change-Id: I66db9715c122ef6bb4665ad5d086a9ecc9c7c93a
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/482703
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Gru ran out of room with upcoming change, disabled CONFIG_CMD_ALS
to free up the needed space and keep build from breaking.
BRANCH=none
BUG=chromium:615059
TEST=verified gru target build doesn't run out of flash space using
"make buildall -j"
Change-Id: Ifb76ad0fe4693dfa4415370354c6d5af2bd4cc11
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/490846
Reviewed-by: Scott Collyer <scollyer@chromium.org>
The first two versions of servo_v4 (red and blue) have the TPD2E001
ESD between VBUS and CC1/CC2. This part has a breakdown min voltage of
11V. Therefore for these versions of servo_v4, need to limit VBUS to
less than the default 20V value.
This CL adds support to read two board ID gpios attached to the gpio
expansion part. The max VBUS voltage is limited to 9V for red/blue and
allowed to be 20V for black.
BUG=b:38351574
BRANCH=servo_v4
TEST=Manual
Modified a servo_v4 to add the 2 new pullup resistors. Tested with
this unit and with a unit that does not have the pullups. Verified
that without the pullups the version ID reads a 0 and the max VBUS
voltage that will be requested by the CHG port is 9V. Wih the modified
servo_v4, verified that the version reads 3 and the CHG port will
request up to 20V.
Change-Id: Ic41fcbe3a5c000282552c7322b5ab18ebb203cd2
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/507027
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
This change adds CONFIG_POWER_BUTTON_INIT_IDLE. When it's set,
the system starts with the power button state idle. It means
when the board boots from power-off, it stays at G3.
BUG=b:37536389
BRANCH=none
TEST=Power on Fizz. Verify it stays at G3. Verify it boots
by pressing power button.
Change-Id: I09a62a69d9f201b2dc261838cc9b4425fe3a8dc1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486945
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Instead of using EC hibernate shut down the PMIC over I2C.
This will turn off the DSW rail and the EC completely. The existing
wake sources are still able to wake the system.
BUG=b:35647896
BRANCH=none
TEST=manual testing on Eve board to ensure that wake sources that
are expected to wake from G3 are still functional. (AC, power, lid)
Change-Id: I91b14ec360190176dba0a8e7c458b2b0ab5b6dcd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506719
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Enable the mutable scancode sets for EVT boards and reassign the
existing F13 scancode to instead send the new 0[e0 58] 1[e0 07]
scancode instead.
BUG=b:36735408
BRANCH=none
TEST=manual testing on Eve EVT to ensure that the key that used
to send F13 now sends the new scancode. Also test on P1 to ensure
that the key still sends F13.
Change-Id: Ia134db7b069d5bf10c931ee7ce66dd1ea85d3544
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506718
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add an option to allow the scancode sets to be mutable. The only
reason to use this is to allow a scancode to be changed at runtime,
for instance to support different keyboards in one image.
The side effect of this is the scancode sets are moved out of the
shared RO section.
BUG=b:36735408
BRANCH=none
TEST=make -j buildall
Change-Id: Iefb97691d1f295411d7b5db603d9214d41af49fd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506717
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
First, libpayload expects the keyboard interface index to be 0.
Then, hid_iface_request needs to reply to USB_HID_DT_HID request
with the content of struct usb_hid_descriptor. With current code,
the variable name is generated (and therefore hard to guess), so
we create a new set of macros so that we can use a specific
variable name.
Also, add support for HID Get_Protocol and Set_Protocol, as they
are compulsory for devices supporting boot protocol, even though
those are mostly no-op for now.
Finally, add a note regarding USB HID keyboard boot protocol, to
make sure that we do not accidentally change the report format.
BRANCH=none
BUG=b:36538963
TEST=Keyboard works in FW screen, both trackpad and keyboard
still work when AP has booted.
TEST=hammer/staff can still be updated (both RO from RW, and RW
from RO)
Change-Id: Ibea4888385909c9ce3b430464e5805c039d4b9ed
Reviewed-on: https://chromium-review.googlesource.com/505796
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This applies the simple rule: Charging port led is on, other
is off. When charging, LED is amber, otherwise it's white.
Open questions:
- Do we want blinking on low battery? On which side(s)? In
which AP states?
- No blinking in S3? That's ok?
- Need to add led blinking support for special debug mode
- Recovery mode blinking does not work as LED is powered from
a rail that is not on when AP is in S5.
BRANCH=none
BUG=b:37970194
TEST=Charge from one side, led is first amber, then white when
battery is full. Switch side, led behaves the same way.
Change-Id: I0531d72cd621148c0d0cce57a32b7310792d9936
Reviewed-on: https://chromium-review.googlesource.com/497372
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add the evaluation board driver of npcx7 series ec for testing. If you
received the evb which ec is 128-pins package, please notice it has
the following limitations.
a. No GPIOD7/E0 pins.
b. No I2C4_0, I2C4_1, I2C5_1 and I2C6_1 ports.
c. No ADC7, ADC8 and ADC9 channels.
d. No JTAG port 1.
e. Do not enable CONFIG_HIBERNATE_PSL since no PSL circuit on evb.
This CL also includes:
1. Modified reset config from srst to sysresetreq in openocd/npcx.cfg.
Make sure openocd driver can reset ec by using NVIC_SYSRESETREQ.
2. Add flash utilities for npcx7 ec in openocd/npcx_cmds.tcl.
3. Add npcx7_evb support in flash_ec.
BRANCH=none
BUG=none
TEST=Passed all npcx7 drivers verification on the evb no matter which
ec's package is 128 or 144 pins package.
Change-Id: I8224d97cd66ce483d70816f47b2e124308f1b69c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505832
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Some chip supports two owned slave address. The second slave address is
used for other purpose such as board specific i2c commands. This option
can be set if user of the second slave address requires larger host
packet er size.
BRANCH=none
BUG=b:37187312
TEST=`make BOARD=rose -j`
Change-Id: I8d0b04bf4dded55e3957c7b25d849663299593e5
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472288
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
This patch clones I2C slave and hostcmd driver from stm32f0.
This patch contains contribution from Wei-Ning Huang <wnhuang@chromium.org>
for fixing i2c slave transmitter (CL:471726).
BUG=chromium:688979
TEST=build and load on dev board, run i2cget/set on host and check
return value.
BRANCH=none
Change-Id: I3d159d5bdd4bda6c229cf6d275ab4982836628dc
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/461037
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
dabc580d7e "poppy: Add ARC++ sensor support." accidentally moved pin
from gpio 36 to 30. When updating gpio.inc for rev1, I accidentally
thought the pinout had been changed. Let's fix this.
BRANCH=none
BUG=none
TEST=Boot on poppy and soraka
Change-Id: I6f44acdcfa7bc8f21144b26887eda503a350a6b0
Reviewed-on: https://chromium-review.googlesource.com/497232
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
When AP boots and FW screen is shown (e.g. in developer mode),
AP FW is querying MKBP status in a loop, leading to a lot of "+"
being printed in the EC console.
To avoid this issue, let's print "(++)" after a command is received
5 times in a row.
BRANCH=none
BUG=b:37925684
TEST=Set GBB flags to 0x4a38, reasonable number of "+" is printed
on EC console on boot, which firmware screen is being shown.
Change-Id: I8368c558b97e7a2513b979322bd4bba442626b27
Reviewed-on: https://chromium-review.googlesource.com/505948
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
At init time, read resolution/dpi from trackpad, and check that
logical/physical dimensions match the expected values, provided
at build-time.
BRANCH=none
BUG=b:38277869
TEST=Flash staff, no error message at boot time. Flash hammer image
onto staff, a warning is shown at boot time.
Change-Id: I5ef7d25b6e6525c2bd6fc023f58f3a242134d962
Reviewed-on: https://chromium-review.googlesource.com/505857
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In principle, trackpad dimensions (logical and physical), can be
probed from the trackpad at runtime, but this would slow down setup
time, as we need to wait for the trackpad to be initialized to read
those. Also, we do not have a framework to generate HID report
at runtime, and a new base with new trackpad would probably require
a new overlay anyway.
Also, set appropriate (temporary) values for both hammer and staff.
BRANCH=none
BUG=b:38277869
TEST=Connect hammer/staff to host, correct logical dimensions are
shown in evtest, and resolution is always 32.
Change-Id: I39b84274d71ca2f4e285f3324c0841331aae9bc1
Reviewed-on: https://chromium-review.googlesource.com/505856
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fizz has two power sources: barrel jack and type-c port. It
selects a power source at boot and does not dynamicall switch
to the other ports after that.
Fizz initializes all power suppliers of all ports to zero then
initialize the source supplier (barrel jack or type-c port).
When both sources are provided, it prefers a barrel jack. This
detection is done by reading the voltage on PPVAR_PWR_IN.
If barrel jack is detected as a sink, type-c port works as a
source only. If type-c port is detected as a sink, type-c
port works as a sink only.
Fizz does not have a battery. So, battery module is removed.
BUG=b:37573548,b:37316498
BRANCH=none
TEST=Boot on both type-c & barrel jack.
Change-Id: If4f5ff0c6019d06ac9dacb5dd365f5aa96bffef3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/499547
