To accomodate our growing code, image RW.B is removed so that RO and
RW.A can both have 60K space. This is just a temporary solution. Add
RW.B back when we have enough space for all three images.
Also add license header to firmware_image.lds.S so that repo does not
complain about it.
BUG=chrome-os-partner:8079
TEST=build image and run on proto-0.
Change-Id: I85b723f3e645c12fd89b189263ca44d58c4621eb
Signed-off-by: Vic Yang <victoryang@chromium.org>
Compared to Daisy, it has the EC console on USART2 (pins PA2 and PA3)
and regulator enable GPIOS EN_PP1350 and EN_PP5000 are on PA9/PA10.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv && make BOARD=daisy && make BOARD=discovery
Change-Id: I545f7c9b05480e58db913ea562c77a1a1cd2b11c
Avoid duplicating in each board file, the stub functions replacing not
implemented drivers on the STM32L platform.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=discovery
Change-Id: I25cd949c31e53a90c39f623617c7d52517a3d205
Allow to set easily the SoC pins to one of their native functions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, check the muxing of the USART pins is still
working and we get traces.
Change-Id: I6e83d2eea8986d814720ad4b2fef588908b99079
This CL attempts to abstract underlying bus from i8042 code. Nearly
all i8042 logic is isolated already. This patch is intended to allow
us to use i8042 logic for processing keys and commands on boards which
do not necessarily use LPC as the host <--> KBC bus interface.
This CL does the following:
- Define KBC bus <--> host (kbc_host_bus) on a per-board basis in
board.c.
- Add generic wrappers in place of lpc_keyboard_* in i8042 code.
- Define the behavior of generic wrappers in EC-specific keyboard
sources. If board.c specifies LPC, then send via LPC.
TODO: This needs to be tested on real hardware...
Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=None
TEST=Locally compiled for Link, BDS and Discovery.
Change-Id: I9cabd514bd44fd6b508c26994eccc3011eedbc0f
Allow to setup edge triggered interrupts on the GPIOs.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=add a adhoc handler for the USER button and check its trace.
Change-Id: I11a280c412c1d333bab4a74f869221edf59fcf8e
This will allow more efficient access to EC-provided data (temperature,
fan, battery) by the main processor.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7857
TEST='ectool hello' from link main processor should still work
Change-Id: I2dc683f3441b34de9fb4debf772e386b9fdcfa82
Implement enable_fpu() and disable_fpu().
enable_fpu() disables interrupt and then enables FPU.
disable_fpu() disables FPU and enables interrupt.
Also added a CONFIG_FPU flag.
BUG=chrome-os-partner:7920
TEST=none
Change-Id: I2d71f396d9c7d7ac4a6a2d525f3d86f8aae87521
Signed-off-by: Vic Yang <victoryang@chromium.org>
This also significantly refactors the module in other ways. Instead
of polling for changes every second, the power button task sleeps
until its next state transition or input.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7508
TEST=manual
1. Reboot EC with lid open. System should NOT power on.
2. Close lid. System should power on.
3. Open lid. System should power on.
4. Press power button. System should power off.
For now, EC debug messages should also indicate [PB task wait] only
when transitions are taking place; the task function should be
sleeping at other times.
Change-Id: I86ac420506cebcdf9ca62bdca342e86857d9e242
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7451
TEST=hold down no keys; KB init state should be blank
hold down reload (F3); KB init should indicate recovery key pressed
hold down F3 + ESC; same
hold down F3 + F2 + ESC; KB init should NOT indicate recovery key pressed
Change-Id: I0fbf15407b20669396f667e6499ee5a9d545a4d5
BUG=chrome-os-partner:7839
TEST=none, work in progress
Change-Id: I20acde8db7f250227adcd4b9dc59328362e68720
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
These provide 8-bit accesses to registers within an I2C device.
BUG=chrome-os-partner:7839
TEST=none
Testing will come when I start using them.
Change-Id: Ib53d3347253bccee93cb9c5da12db92970155d92
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Remove id field from temp_sensor_t struct, since it's only used by the
console command (which already knows the id, because it's looping over
it).
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=none
TEST='temps'
Change-Id: I0970850073d644509cd5501d7ac4421c7373143b
We have to wait until the controller is no longer busy before we announce
that we're done. Just waiting for the first interrupt isn't enough, because
that's often just an error indicator and the controller still has to stop.
BUG=none
TEST=none
Change-Id: I065c049111d7de276bf8f7cd0eed39c3f5cff5f4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7493
TEST='powerbtn' to boot main processor, then 'temps' and 'pecitemp'
Change-Id: Id57526ebb37c8aecb05ecebccc2824f462b9de1a
The Daisy board will have the EC UART on the debug connector wired to
USART1 (PA9/PA10 pins)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=Run Discovery board with mini-servo attached to PA9/PA10 and see
the traces.
Change-Id: I97c59ba388fddb150ff6c76ec3317deedb567546
Supports turning system on and off via power button.
Also added 'powerbtn' command, which sends a power button press of the
specified duration, and deprecated the 'x86power s0' command, since
pressing the power button is a more correct way of powering on/off the
system.
Note that current coreboot doesn't seem to boot reliably; when it
fails, the x86 asks for S5 and then S0 a second later. It boots about
every 3rd try. No indication this is due to the EC; the EC just was
ignoring these requests until this CL.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7851
TEST=reboot, 'powerbtn', system should power on
'powerbtn', system should power off
'powerbtn 5000', system should power off regardless of previous state
press power button, system should power on
press power button again, system should power off
hold power button 8 sec, system should power off regardless of previous state
Change-Id: I89f419553289b20c78a57bc8cb1699932b095aa1
Battery charging state machine contains many file changes.
This is the 1st part of the break down. Refactor original
test code into board dummy driver. Normalize charger API.
And import link's charger IC driver.
Signed-off-by: Rong Chang <rongchang@google.com>
BUG=chrome-os-partner:7855
TEST=build without warning and error
BOARD=bds make
BOARD=link make
BOARD=discovery make
Change-Id: I34b6e9862a45331378916bc77653d4adb22ca548
Record commands used previously and use up/down arrow key to navigate in
the command history.
Also removed the command '.' of repeating last command as we can use up
arrow key now.
Also changed the behaviour of uart_write_char() to be blocking on
transmit FIFO full, so that we do not lose echoed character and do not
need to flush.
BUG=chrome-os-partner:7815
TEST=Type 'help' and enter. Then type 'aaaa' and up arrow key, should
show 'help', and pressing enter prints help.
Type 'hellp' and enter. Then type 'aaaaaa' and up arrow key, should show
'hellp'. Should be able to use left/right arrow key and backspace to
correct it to 'help', and pressing enter prints help.
Type 'help' and enter. Then type 'aaa', up arrow key, and down arrow
key. Should show 'aaa'.
Change-Id: I65c615d61bf63acb31bea329aa91a3202d4db0ad
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7488
TEST=type things into the x86 console UART; should appear on the u-boot prompt
Change-Id: I75fd225842c03d11d79280fb7453ad37695279e3
Refactor board/chip-specific code into corresponding directories.
Add support of the four I2C temp sensor in Link.
Use table lookup to handle different types of temperature sensors.
BUG=chrome-os-partner:7527
TEST=Correctly read EC internal temperature on bds.
Compile for link succeeded.
Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
Original code tests SND bit, but it is not reliable to indicate the
SERIRQ frame has been sent out because the EC always clears it
immediately. Unfortunately the SIRQRIS is always asserted in
continuous mode so that we cannot rely on it.
So, the udelay(4us) method is the best way we can use now.
Note: the quiet mode? Forget it. My EC never sends out further frames
after the first has been sent.
BUG=none
TEST=on bds board.
Change-Id: Ica79b463f3dbe7435fe75f3db4cef00ad7ad5ec0
The GPIO console commands are common to all platform, let's push them in
the common code.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=bds && make BOARD=discovery
on BDS console, try gpioget command.
Change-Id: I26e6d26b8d661e78b80d5d5f665e81f4daef0c11
No interrupt support yet.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery EC console, using "gpioget" and "gpioset" commands
check we can switch the LED and read the button state.
Change-Id: I01294643d3df070a535dab5a6be02c296487fca5
Add a final wait to ensure the clock is ready before returning.
Setup the Flash according to the manual recommendations.
The low-speed oscillator and RTC are now done in the system module with
other RTC inits.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run the EC firmware on the Discovery and manually exercise various
path through the console.
Change-Id: I4e6149b6fd55c8fc72dbdf6bfc4a10665e0246bd
Allow to get proper reset reason.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=On the discovery board, try the reset button, the "reboot" command
and a blocking wait, and see the proper reset reason displayed.
Initialize the scratchpad register with "setscratchpad" command and
check we can read it back after reboot.
Change-Id: I1fe1eec4987f7c9816454de4fd3b4addda4ad05a
Use the Independant WatchDog.
The Window WatchDog would provide a nice early warning interrupt before
actually rebooting but the max period (128 ms) is probably too short for
our purpose.
The full GPIO support and the reboot cause detection will be implemented
in later steps.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=on Discovery board, do blocking waits of 500ms and 1500ms, and
check the latter reboots the platform and the former does not.
Change-Id: I26e4d8b26b733269b7811cc3b3a09daf98ea364a
The problem comes from the different assumption of interrupt mode in EC and
the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge.
However, the auto-IRQ functino of EC is level-triggered and uses low-active to
assert an IRQ. This makes the deadlock so that the kernel never gets an
interrupt until a byte is manually pulled from host.
So, the solution is manually firing an IRQ_1 to host after EC puts a byte to
port 0x60. Note that the auto IRQ needs to be disabled in order to avoid
the interference with manual IRQ generation.
This CL also moves chip specific code to lm4/lpc.c and handle some minor
keyboard commands.
BUG=none
TEST=on hacked baord.
Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
The ADC input pin was always configured as BDS. Modified it to configure
the correct pin.
BUG=none
TEST=On Link, "rw 0x4002451C" show 0xff instead of 0xf7.
Change-Id: I1efd5cd59ad65f55cd673529afa6153add63ecac
Refactor ADC code and move board/chip-specific part to corresponding
directories.
Implement function and console command to read Link charger current.
BUG=chrome-os-partner:7527
TEST=Read EC temperature and POT input on BDS.
Change-Id: I7fafd310ea49d9b2781f10c3453f5488da29a08a
As the STM32L doesn't have any 32-bit timer, we use 2 chained 16-bit
counters to emulate a 32-bit one :
* TIM2 is the MSB half-word (Slave timer)
* TIM3 is the LSB half-word (Master time)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run timer_calib and timer_dos on the Discovery board, and check
waitms and gettime console functions against wall clock.
Change-Id: I8917207384d967fd87321797856e3d58b237f837
Force starting the transmission immediatly when ordered by the UART
buffering layer.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC console on Discovery and measure the timestamp of each
characters on the serial port.
Change-Id: I036a3fa0a60baa27de4ba0ceb386841a429535ac
The TX empty interrupt needs an actual write to DR to be cleared.
So, we de-activate it before filling the TX buffer to ensure the
interrupt won't fire after the last write.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run EC console along with a lower priority task on Discovery board,
and check the task is scheduled as expected.
Change-Id: I56c33c6dd7ccfd238fd9d5910780d12945467010
simple UART driver to get the serial console on the USART3.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on Discovery board and check we get the first message on the
UART and the console is echoing the characters.
Change-Id: Id85999a5ddbd75804e9317a1b8c2fd4afb89eb38
Run from internal clock at 16Mhz, but enable PLL to get a better
precision.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=run on discovery board and check software is still alive after
clock initialization.
Change-Id: I8425482825015adf96c30e67a9320d0df2f4f2b7
Define IRQs and register addresses for basic peripherals to do STM32L
bringup.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=mostly untested, there should be typos over there...
Change-Id: Ib6d90436e25be74f724112619cdae7acccfaf085
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7718
TEST=manual
// enable fan
gpioset enable_vs 1
// set fan speed to 7000
fanset 7000
faninfo
// should report duty cycle about 65%, fan speed about 7000 rpm, status = 2
fanset 4000
faninfo
// should report duty cycle about 25%, fan speed about 4000 rpm, status = 2
fanset -1
// should report duty cycle 100%, fan speed about 8800 rpm, status = 3
Change-Id: Ib7d7df14ad240811e6e79bc1fc4ecf0e6841c334
