When a sysjump host command is received, there is a (usually) small
period of time when the EC has sent a reply packet back to the host, but
interrupts are still enabled. If the host sends a new host command,
STATUS_PROCESSING will be set by the EC ISR, but the host command will
never be handled due to pending sysjump. In this case, STATUS_PROCESSING
will still be set, so we need to clear it on LPC post-sysjump re-init.
BUG=chrome-os-partner:49318
TEST=Add 200ms msleep before call to interrupt_disable() in
jump_to_image(), boot to software sync, and verify host commands are
handled successfully post-sysjump and system continues to boot.
BRANCH=glados, cyan
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id0878df738541f7d5d158821a68988a8e6dc6759
Reviewed-on: https://chromium-review.googlesource.com/322431
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
As proposed by e.lam@cirro.nl, update the number of USB interface in the
descriptor when we are in 'sink mode' : the vendor interface for the
sniffer endpoint is not exported in this mode, so we have only one
interface.
This should the Windows USB driver used by libusb/Zadig.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chromium:570287
TEST=./board/twinkie/build_rw_variant
Change-Id: I5948643d552030481a52adb8c0937a42e7ae8ae1
Reviewed-on: https://chromium-review.googlesource.com/322371
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
the third_party tpm library.
Some files in the third_party TPM2 source are
omitted from compilation (e.g. CpriHash.c) as they
contain platform dependent code. Subsequently all
the functions necessary for compilation were moved
to stubs.c. However, some of these functions are
platform independent, and should remain in the
third_party implementation.
The corresponding change CL:321375 adds such functions
to third_party/tpm.
TEST=compilation succeeds
BRANCH=none
BUG=chrome-os-partner:43025,chrome-os-partner:47524
CQ-DEPEND=CL:321375
Signed-off-by: nagendra modadugu <ngm@google.com>
Change-Id: I6a41085332c94dcbe7ecfdeceea0a7015e4ac693
Reviewed-on: https://chromium-review.googlesource.com/321930
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Previously the flash test used the GPIO string name to identify the
write protect GPIO. Change to use the GPIO signal enum. This is faster
and removes a use of gpio_list.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I4203c33cfa6d2b25d73d886b5248857a0c271565
Reviewed-on: https://chromium-review.googlesource.com/321913
Commit-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The GPIOs were set incorrectly in EVT so invert them in the EC
so we can keep an incrementing board version.
BUG=chrome-os-partner:49357
BRANCH=glados
TEST=test that 'version' reports 1 for EVT board instead of 4
Change-Id: I520c3e09c7c3f0797b46807932f859aa490ac4c7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/321929
Reviewed-by: Shawn N <shawnn@chromium.org>
Use a static buffer rather than 256 bytes of stack when scanning for the
end of an image.
BUG=chrome-os-partner:49396
TEST=Verify "ectool echash abort; ectool echash start 0xfffffffe 100"
doesn't panic on glados.
BRANCH=glados
Change-Id: Ia864fe77134533bce079dab3b253142b14410ded
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/322283
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
If no charger connected, battery LED blinks when battery is
low/critical; and it should stop blinking once system is in
S5/G3.
BUG=chrome-os-partner:48718
BRANCH=none
TEST=Verified on Kunimitsu when OS shutdown system due to
critical battery and enter S5/G3, battery LED stops blinking.
Change-Id: I9349a9938a548ce675999579f749bd5dae3c399f
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/321794
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Modified hibernate funcs to support hibernate_wake_pins on weatley, npcx_evb
and npcx_evb_arm.
For better power consumption, we disable ADC, tri-state spi pins, all inputs
of wake-ups to prevent leakage current caused by input floating and set
necessary GPIOs' states in hibernate function.
Modified drivers:
1. npcx_evb/board.c: Add hibernate_wake_pins array for hibernate.
2. npcx_evb_arm/board.c: : Add hibernate_wake_pins array for hibernate.
3. wheatley/board.c: Add hibernate_wake_pins array for hibernate.
4. wheatley/board.c: Add board_set_gpio_state_hibernate func for adjusting
GPIOs' status related to board for better power consumption.
5. hwtimer.c: Remove unnecessary interrupt_enable/disable funcs. Interrupt
will disable before it is called.
6. register.h: Add WKINEN definition and declarations used for hibernate.
7. system.c: Add system_set_gpios_and_wakeup_inputs_hibernate to set GPIOs'
state and wake-up inputs before entering hibernate.
8. system_chip.h: Remove unused BBRM_DATA_INDEX_PBUTTON field.
9. gpio.c: Enable WKINEN in gpio_set_flags_by_mask func.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Ic85814065464095fdcb7a75964c2c528d8f8e62f
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/321466
Reviewed-by: Randall Spangler <rspangler@chromium.org>
flash_ec is used for both ec chips accessed over servo, and
standalone stm32 devices. It's not necessary to have a servo
conencted to update the standalone devices over usb.
This is useful for servo v4 and servo micro.
BUG=chromium:571477
TEST=Verify servo micro/discovery can be flashed without servo v2.
BRANCH=none
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: I9deee1616d93feeac4d6675bc3a4f573d4906f7b
Reviewed-on: https://chromium-review.googlesource.com/321925
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@google.com>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
There is no indication that PMIC is ready for communication
EC should check i2c response from PMIC first before initializing
rest of registers.
BUG=None
BRANCH=master
TEST=check if there is message, "PMIC init failed", in EC log.
Change-Id: Ic790edf3639acfb2b5357e2638c88dc8d59bebf0
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/319631
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Updated the permissions of ec_uart_pty to match the permissions of the
other PTYs.
BUG=None
BRANCH=None
TEST=cros_workon hdctools ec-devutils, run servod, ls -l on ec_uart_pty
from dut-control, verify that permissions are 666.
Change-Id: I71c72645c5a435fea562084185b80ff6d31652b4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321371
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Includes support for encrypt / decrypt,
and sign / verify; padding schemes OAEP /
PKCS1; supporting bignum library.
RSA key sizes must be a multiple of 32-bits
(with the top bit set). Keying material,
input and output buffers are required to be
word-aligned.
BRANCH=none
TEST=added encrypt/decrypt sign/verify tests, compatibility with openssl tested
BUG=chrome-os-partner:43025,chrome-os-partner:47524
Change-Id: I6bc324c651e3178bb45bb75ab5935d9bc07efbce
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/316942
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
This commit adds support for the EC-3PO interpreter to disconnect and
reconnect to the EC UART. This is handy so that other tools that need
to use the raw UART directly can do so without interference from
EC-3PO.
BUG=chromium:571170
BRANCH=None
TEST=For both enhanced and non-enhanced EC images, issue disconnect
command and verify that no debug prints were emitted and no commands
were sent to the EC. Then issue reconnect and verify that the console
works as normal and that no commands were buffered.
TEST=./util/ec3po/run_tests.sh
Change-Id: Ic572e25d24d5e45fbe2eeb84a534235c4ec98d38
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321084
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
If a user had already run util/ec3po/run_tests.sh, and then never
modified any ec3po files, the presubmit check would list every file in
the EC repo that was newer since the the last run. This included
files such as build artifacts.
BUG=chromium:575032
BRANCH=None
TEST=Run ./util/ec3po/run_tests.sh once. Run make -j buildall, try to
upload and verify that no nag message to run ec3po tests is presented.
TEST=Touch an ec3po file, try to upload, verify that nag message about
running ec3po unit tests is presented.
Change-Id: I4f09bb76dcd85b570b57030197f4887bed85f1a7
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/321134
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Replace Makefile with real link file in order to build sources in board folder.
Modified drivers:
1. Makefile: change file type to link file
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Iba80166369869d661c8f6da989e3bc1c586047e7
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320901
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
if CONFIG_USB_PD_TCPM_VBUS is enabled, a race condition may happen:
In function pd_set_input_current_limit() and typec_set_input_current_limit(),
EC may notify AP power change event before PD send the up-to-date
POWER_STATUS TCPC alert to EC. It will cause the AP get the stale power
status. Move the power change event notification to board_set_charge_limit(),
it will be called after EC receives POWER_STATUS TCPC alert, and sending
power change event notification only if the "charge limit" or "charge port"
or supplier is changed.
BUG=chrome-os-partner:48801
BRANCH=none
TEST=make buildall -j; Tested on Oak by plug/unplug AC adapter to
type-C ports and verify the UI battery icon shows the correct status
instantly.
Change-Id: I52f0e268fdebc45e609d843847540ae48cd0a9eb
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/320066
Reviewed-by: Rong Chang <rongchang@chromium.org>
For TCPMs with an off chip TCPC, PD MCU host event status can be handled
in a common way. When a status flag is updated (ex. from
charge_manager), notify the AP through the host event, and save the
status flag for later retrieval.
BUG=chrome-os-partner:49124
BRANCH=None
TEST=Verify `cat /sys/class/power_supply/CROS_USB_PD_CHARGER1/online` on
chell reflects the actual online status of the charger. Also verify UI
charge icon tracks the online status correctly.
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I63bc70205627474590e38ffd282faedaea3bcc66
Reviewed-on: https://chromium-review.googlesource.com/320796
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The presubmit check would nag at the user to run the EC-3PO unit
tests, even if they hadn't modified any EC-3PO files. This was not my
intention. This commit fixes the presubmit check to only check for
unit test success if a EC-3PO file is modified.
BUG=chromium:575032
BRANCH=None
TEST=Remove util/ec3po/.tests-passed; Modify a non-ec3po file, commit,
and try to upload. Verify that no nag message is presented.
TEST=Remove util/ec3po/.tests-passed; Modify a ec3po file, commit, and
try to upload. Verify that a nag message to run unit tests is
presented.
Change-Id: I86e9f325329b7ad1a4c7c5971b7851e9024e7750
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/320831
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
During pressing VolUp + VolDn + Pwr buttons, Silego polls down both EC_RST_L
and ROP_LDO_EN on wheatley. Beside VCC1_RST occurs, power-on reset also occurs
simultaneously since EC's power rail is turned off by PMIC for a while.
VCC1_RST_STS bit is cleared by power-on reset and it will influence recovery
mode detection.
The workaround treats no matter power-on or VCC1_RST reset as reset-pin reset.
Use BOARD_WHEATLEY to distinguish them.
Modified drivers:
1. system.c: Proposed workaround for RESET_FLAG_RESET_PIN issue.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I96198ffb6901f0539755046ca303e94381ae7541
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320641
Reviewed-by: Randall Spangler <rspangler@chromium.org>
In order to support rpm mode, we use a TICK function (fan_tick_func) to
monitor tacho value and adjust PWM duty. In this version, fan driver always
enables clock source of MFT to make sure it can present real-time tacho value.
For better performance, the feedback value to adjust PWM duty is various.
We also change fan & pwm settings for SUNUN 4-pins pwm-type fan.
Modified drivers:
1. npcx_evb/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
2. npcx_evb_arm/board.h: Modified fan_t & pwm_t structures for SUNON fan spec.
3. fan_chip.h: Remove unnecessary default_count field of mft_t structure
4. fan.c: Add support for rpm mode
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: I25e7bd2f3f726b40fd4e0d9a1049a4d82bbd830d
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320510
Reviewed-by: Randall Spangler <rspangler@chromium.org>
x86 systems will auto-power-on when power is applied to the EC. When
the battery level is critically low, power-on is prevented, except when
the system is unlocked. So, when unlocked, some systems will
auto-power-on regardless of battery level, overcurrent the charger /
battery, and then repeat forever.
Prevent this reboot loop by ignoring auto-power-up when the battery is
critically low, regardless of system unlocked status.
BUG=chrome-os-partner:48339
TEST=Verify power-up is prevented on no-battery chell w/ donette. Then,
run 'powerbtn' on EC console and verify system powers on (and
overcurrents).
BRANCH=None
Change-Id: Ia631b5a8c45b42ec805e4a0c3f827929a0efd236
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/319187
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
[task]
1. Copy task_wait_event_mask() function of cortex-m0.
[system]
2. Include host_command.h for host_command_pd_request_hibernate().
[i2c]
3. Update i2c handler to use task_wait_event_mask.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=chromium:435611,chromium:435612
TEST=1. console commands: i2cscan, i2cxfer, and battery.
Change-Id: If5bb4407460d28c0b021ab133ca4b635ff7bc3c9
Reviewed-on: https://chromium-review.googlesource.com/320440
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the RO region being added to software sync, up to two hashes will
be requested during boot. Currently if vboot_hash has a valid hash when
the EC gets an EC_VBOOT_HASH_GET host command then it will return that
hash. When the EC gets a request for the RO hash after it has calculated
the RW hash it returns the RW hash in the response.
This change will add a check that the EC not only has a valid hash, but
that it is for the correct region.
BRANCH=none
BUG=none
TEST=Try to get the RO and RW hashes from depthcharge and make sure they
match the values gotten using ectool
Change-Id: I2449c8d79b4a74f4865dd1234fb253bcdac66a31
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/318861
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Some devices have multiple ECs (main EC and PD MCU) and therefore there
are multiple consoles and interpreters running concurrently. This
commit prepends each log message with the served PTY to identify which
of the console or interpreter instances the log message comes from.
BUG=None
BRANCH=None
TEST=Ran ec3po in servo for samus. Noticed each debug print with the
different PTYs for the main EC as well as the PD MCU.
TEST=util/ec3po/run_tests.sh
Change-Id: Icc69d2257172f4fedc217572ad0b6d15dac40387
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/320597
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Wai-Hong Tam <waihong@chromium.org>
In testing, it was found that certain ECs couldn't respond to the EC_SYN
in less than 0.1s. Therefore, this commit changes the interrogation
timeouts. For non-enhanced EC images, the timeout has been increased to
0.3 seconds. This is small enough that there's not too much of a delay,
but long enough that enhanced EC images can respond in time. With an
enhanced EC image on veyron_jerry, EC_ACKs were arriving after ~0.2s.
BUG=None
BRANCH=None
TEST=Flash enhanced EC image on veyron_jerry, start console/interpreter
pair and verify that the console is functional.
TEST=util/ec3po/run_tests.sh
Change-Id: I4931aaee908653ae302a8e57941444e5f0b6ce2b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/320594
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We should consider the interval between the calling __hw_clock_event_set and
entering deep idle. In order to get more accurate value of deep idle time, FW
should record the time-stamp before entering deep idle and calculate the deep
idle time based on it.
Modified drivers:
1. hwtimer_chip.h: Add new function declarations for deep idle time caculation.
2. hwtimer.c: Add new functionsfor deep idle time caculation.
3. clock.c: Modified for calculating more accurate deep idle time.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Id037c4dc3564659e4ad493f2fc3ffc5d06c18b06
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/320071
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Added presubmit check to make sure that when any ec3po files are
modified, the unit tests should be run as well.
BUG=None
BRANCH=None
TEST=Touched a unit test file, tried repo upload and received an error
about running unit tests. Ran run_tests.sh and all tests passed. Tried
to repo upload again and this time it succeeded.
TEST=Created a failure in one unit test, ran run_tests.sh and verified
that the failure was caught and the CL wouldn't pass the presubmit
check.
Change-Id: I4df4a0fd1107292f693749188491f6286360f557
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/319211
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
After commit 98ab7484d331 ("keyboard: prevent races enabling/disabling
kb scanning") kbpress was totally broken, which wasn't so good for
FAFT. Fix it by making sure we go into polling mode for simulated
keyboard presses.
BUG=chrome-os-partner:48849
TEST=kbpress works
Change-Id: Icd663c2ee7a184e6af4438368595087b35724a4f
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/319586
Reviewed-by: Randall Spangler <rspangler@chromium.org>
ecst is used at build / link time, so it should be compiled for the
build machine architecture, not the architecture of the host board.
BUG=chromium:567232
TEST=Verify 'cros_sdk ... cros_run_unit_tests --board=oak' passes with
CL:319256.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ic7f6aa989d0760eda1fe64221e41d3230c9ab9b9
Reviewed-on: https://chromium-review.googlesource.com/319633
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Pull floating pins high, don't duplicate external pull ups, and make a
few other minor changes.
BUG=chrome-os-partner:48109
TEST=Verify chell continues to boot and S5 power is reduced to
~5.5 mW.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaee0cc926149dae1f4189e6b9e4f7e3a4da6ba1c
Reviewed-on: https://chromium-review.googlesource.com/319165
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Use custom charging profile to enable charging at a faster rate.
BUG=chrome-os-partner:48662
BRANCH=none
TEST=load on lucid and charge at room temp. Use "chgstate" command to
verify that battery current matches the expected fast charging current
for the given temp range and voltage.
Change-Id: Ie508d29db091593ff2cfda9d135c73f6a3de5a9a
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/319493
Commit-Ready: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Support lower core CLK frequency and configure the baudrate parameter of console
UART for current core CLK.
Modified drivers:
1. clock.c: Support lower core CLK frequency.
2. uart.c: Add baudrate setting for differenct core CLK.
3. clock_chip.h: Set default core CLK to 16MHz.
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none
Change-Id: Id83ecf92c19bec508ec84e2d271d7e1fa278774f
Signed-off-by: CHLin <chlin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/319030
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Add support for continuously writing ADC samples to a circular buffer.
CONFIG_ADC_PROFILE_FAST_CONTINUOUS should be defined and an
appropriate sized buffer must be passed to adc_read_all_channels().
BUG=chromium:569994
TEST=Manual on snoball. Verify 'adc' continues to function (single
mode). With pending commit, verify that continuous conversion interrupt
is called at appropriate frequency and values look consistent.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I025825d72a698f8f1f4f95a89477df791bd5e67e
Reviewed-on: https://chromium-review.googlesource.com/318505
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
