This fixes a bug in which after a sysjump, the sleep_mask is
reset, and the EC is allowed to go into a low power mode even
though the AP is still running. This causes numerous problems,
must notable of which is that a flashrom write fails with an
EC protocol mismatch error.
BUG=chrome-os-partner:23645
BRANCH=none
TEST=Execute a flashrom write and make sure the system does not
use the low power code immediately after.
Change-Id: I4d50282da0c5ba5b6488ed14a267a4d8cafe09a7
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174943
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
These were being driven push-pull, causing leakage.
BUG=chrome-os-partner:23639
BRANCH=none
TEST=rambi still boots main processor out of reset
Change-Id: I39a18e48307b66fc767ce2c8256d828d4e6962e0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174897
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
QEMU tests served us well, but it has been more and more difficult to
maintain as we now have more chips and use more functionality from each
EC chip. With emulator tests in place to test common code and hardware
test to test per-chip/per-board drivers, it's time to remove QEMU tests
to simplify our code base.
QEMU tests that are covered by other emulator tests are removed
completely; tests that are not covered are left alone for now to
preserve the test logic.
BUG=chrome-os-partner:18343
TEST=util/make_all.sh
BRANCH=None
Change-Id: I5a4dd2f5ac42f7f66f86fdce0b62dbd2c65bf66a
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174669
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To conform to our mutating naming conventions, let's rename the
chip-specific PWM header file to have the string "_chip" in it.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: I6584be8e54fd24c8638559817e150c707bc0edb5
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174884
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Needed for shipping systems. Puts battery into shutdown mode until AC
reapplied.
BUG=chrome-os-partner:23634
BRANCH=none
TEST=With system on battery power, 'battcutoff'. System will shut off
after a few seconds. Power button will not turn it on. Plugging
AC power in will turn system back on.
Change-Id: I10a28c3c21623508dc8e4dee1cc5dc8d6fb9a6af
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174888
Reviewed-by: Dave Parker <dparker@chromium.org>
Update the comments in several board.c files to accurately describe which
pwm control circuit is being used for what purpose.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=none
No code changes, comments only.
Change-Id: I29cef5a2bfee4d7d44bedd092783d9f1d2ea5ef3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174901
Picked some reasonable values. Subject to later tweaking.
BUG=chrome-os-partner:23634
BRANCH=none
TEST=On AC power, charging = yellow
On AC power, done charging = green
No battery = blinking red
On battery, AP on = dim green
On battery, AP off = off
Change-Id: I2eb901ea4de98fec8cd83e403d6ed8a06a2a9ca9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174778
Reviewed-by: Dave Parker <dparker@chromium.org>
Using best-guess numbers for input current limit. Battery voltage and
temperature limits are set from actual battery spec.
BUG=chrome-os-partner:23597
BRANCH=none
TEST=battery and charger commands print reasonable info
battery charges when system plugged in
Change-Id: I812276cbe46c8463a855c7ba3e0bfec4852e6f97
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174766
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reset the DMA status after the end of the conversions,
else we will exit too early at the next call of the function and the
values before they are actually transfered.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run "adc" command several times and always see proper value for
each ADC.
Change-Id: I7ad335fffa2da34a4b715e9f0c9927bf06baef8f
Reviewed-on: https://chromium-review.googlesource.com/174397
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This is tidier than every board defining its own module_id enum, and
encourages standard naming of modules.
A subsequent CL will do more cleanup (standardizing on MODULE_LED
instead of MODULE_POWER_LED and MODULE_LED_KIRBY), but it's easier to
do that as a separate CL than part of this one.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: If0fcef284fb3aa2fa145bc9ff3d1f3f2d25a2e47
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174382
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Originally, the ARM boards printed the keyboard scan matrix whenever
it changed. This generated a lot of output, so we filtered that at
the console channel level. When we refactored the keyboard scan
module, that changed so that the scan matrix was not printed by
default, and the 'ksstate' debug command was used to enable printing
it. But on ARM boards, 'ksstate on' wouldn't do anything without ALSO
using 'chan -1' to turn the keyboard console channel back on. And
without the scan matrix printing by default, there's no reason to keep
the keyboard channel off by default.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards
bang on keyboard on pit and don't see much debug output
ksstate on
now bang on keyboard and see matrix changes
Change-Id: I554b42e7582d507530cdecad7b35df71ca0e634f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174373
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
No code changes, just tidying some comments and moving a TODO to a bug.
BUG=chrome-os-partner:23557
BRANCH=none
TEST=compile any project; hey, this is just a change in comments.
Change-Id: Ib1e3190ac9abdc90fb04c785e1f20b9cc66b1bc3
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174447
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Changed ADC clock gating to disable the ADC module to conserve power,
and only enable it when needed. This saves about 15% of the power
consumed by the EC when the AP is running.
BUG=none
BRANCH=none
TEST=Run the ADC stress test. This runs 2000 consecutive ADC
reads of all the channels and verifies that the ADC module
successfully records the samples. Note that when running this
test make sure all other calls to read an ADC channel are
disabled because the ADC read function does not protect
against different tasks accesses.
Change-Id: I9ca3671d8cf68e09d21c9c2594856f9c08476398
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174580
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously, it was really confusing whether I2C_PORT_HOST meant the
port where the EC was the master, or the port used to talk to the AP.
No functional changes, just a global find/replace and some tidying of
unused comments.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: Ia591ba4577d3399729556e0234ba0db3a0e3c5ea
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174546
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Rather than hackily sending a host response before sending the battery
cutoff command, just put the cutoff command in a deferred function
call and respond normally to the host command.
BUG=chrome-os-partner:23568
BRANCH=none
TEST=On battery power, 'ectool batterycutoff' prints success, then the
system loses power due to battery cutoff.
Change-Id: Ic42d08ef94a10f89d093290cda63da01fca985a5
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174573
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
When we cleaned up the alternate function GPIO initialization, we left a
declaration for configure_fan_gpios() in fan.h. That function doesn't exist
anywhere, so there's no point in declaring it.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=manual
Build everything. Nothing fails.
Change-Id: I3d1fe1ff62e523aa7c87d57c5e838b01a0c6e899
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174334
Reviewed-by: Randall Spangler <rspangler@chromium.org>
It doesn't need to be compiled if there would be nothing for it to talk to.
BUG=chrome-os-partner:20739
BRANCH=none
TEST=build all platforms, pass unit tests
comment out chipset task in Rambi ec.tasklist; code still compiles
Change-Id: I004364b8c1fdf02c420162b5ad2843068a26b452
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174302
Device-specific headers belong in driver/ or chip/. The include/
directory should be for common interfaces.
Code should not normally need to include driver-specific headers. If
it does, it should use the full relative path from the EC project root
(for example, drivers/charger/bq24715.h).
Change-Id: Id23db37a431e2d802a74ec601db6f69b613352ba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173746
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The common/ subdir was getting cluttered. Move drivers for external
components to a new driver/ tree, and move what used to be called
chipset_*.c to a new power/ directory.
This does not move/rename header files or CONFIG options. That will
be done in subsequent steps, since moving and modifying .c files in
the same CL is harder to review.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I67a3003dc8564783a320335cf0e9620a21982d5e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173601
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This improves WiFi stability after resume since powering down may
erase or otherwise stymy the firmware.
Signed-off-by: Paul Stewart <pstew@chromium.org>
BUG=chrome-os-partner:22175
BRANCH=none
TEST=Suspend and resume bolt, make sure WiFi is still operable
Change-Id: Ia9e39464955b373e6f03a36ca5af5c475e957208
Reviewed-on: https://chromium-review.googlesource.com/174257
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Paul Stewart <pstew@chromium.org>
Commit-Queue: Paul Stewart <pstew@chromium.org>
CG_CTRL0 is already set to 2 by pmu_init_registers(), and the battery
charge rate hack was temporary.
BUG=chrome-os-partner:23425
BRANCH=none
TEST=build daisy
Change-Id: I863c8d6d5d5f30375dce14b7d2a30e9e710ef969
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173915
Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org>
The EC LPC implementation guarantees that the status byte will have at
least one zero bit, so there's no need to scan the parameter space as
well. Removing this unneeded check will slightly speed up ectool.
BUG=chrome-os-partner:10963
BRANCH=none
TEST=on an x86 chromebook (e.g. link), ectool hello still works
iotools io_read8 0x200 && iotools io_read8 0x204 -> not both 0xff
Change-Id: Ic02ca0ee686ab10e50093807717ec638aaa468c6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174059
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This dev board hasn't seen much love. Add bug links for the unloved
bits and remove an empty interrupt handler.
BUG=chrome-os-partner:23494
BRANCH=none
TEST=build mccroskey
Change-Id: Ic521c6cba4ca438bf54f9ce77eb0cba99be57602
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174082
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Some of the comments no longer apply. Others needed more info.
No code changes; just comment changes.
BUG=none
BRANCH=none
TEST=build all platforms
Change-Id: I1d52aa9a98427a78c9d9a8cf44934fb04c3c00c8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174084
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The pin has a 100k series resistor, which is overwhelmed by the
internal pullup.
BUG=chrome-os-partner:23489
BRANCH=none
TEST=gpioget wp_l, with screw present and removed. With screw present,
signal should read 0; with it removed it should read 1.
Change-Id: I35ee867111d0d7e8626dd3ac8010e9a10f46ccf7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is an analog temperature line on the Samus battery connector. We don't
yet know what it means, but there's a pull-up on it, so if it's reading
close to ADC_READ_MAX, we can probably assume there's no battery.
This change says that any reading within 90% of ADC_READ_MAX means the
battery pack is not present, so we can go ahead and boot without trying to
wake it up first.
BUG=chrome-os-partner:23449
BRANCH=none
TEST=manual
Connect the battery, boot. It should happen quickly.
Disconnect the battery, boot. It should STILL happen quickly.
Running "adc" on the EC console should show an entry for "BatteryTemp". If
no battery is connected, it should read somewhere close to 4095.
Change-Id: I1e41bccb2a988d34de09192ebb0a68b91b1b0b24
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174046
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
A 16-element FIFO consumes 208 bytes of RAM, which isn't too horrible.
No code changes, just expanding on a comment.
BUG=none
BRANCH=none
TEST=build spring
Change-Id: Ibb51970b6fc72623435d21bd0b368c3e60da24da
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173922
Reviewed-by: Vic Yang <victoryang@chromium.org>
The fixme was just a feature request. I've moved it to a new bug.
Comment change only; no code changes.
BUG=chrome-os-partner:23457
BRANCH=none
TEST=build rambi
Change-Id: Ie3fc0482b6697c12040b868ba837073929cf5b82
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173921
Reviewed-by: Vic Yang <victoryang@chromium.org>
This code is pretty much the same across all x86 chipsets. In the
long run, maybe it should be moved to x86_common.c, but for now,
simply implement on bolt what we did on samus and all the other
haswell systems.
BUG=chrome-os-partner:20372
BRANCH=none
TEST=build bolt; don't have a bolt to test on
Change-Id: I01c2795192fcbd3980ed464c1e3e1dfb64fdb228
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173798
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
No code changes, just replacing a FIXME from the comments with a more
thorough explanation.
BUG=chrome-os-partner:20805
BRANCH=none
TEST=build falco
Change-Id: Ibd98322c2b9fd6e0447771ce5fe43e0283743c60
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173930
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Falco has shipped, so those numbers are evidently good enough.
Slippy is not being developed and won't be fixed. Simply note that
numbers are estimates.
Comment changes only; no code changes.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build falco and slippy.
Change-Id: I064896235626af8a5b7214b410908bba91434f7f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173911
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Note that adapter current limits are specific to the given battery
charger chip used in falco. Since the file is named extpower_falco.c,
no additional fixing needed.
Comment change only; code is the same.
BUG=none
BRANCH=none
TEST=compile falco
Change-Id: I28d8b6c9335ec188c30f7c47fb2f8ecdda276bae
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173914
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Changed the low power idle task to use the low speed clock in deep
sleep. The low power idle task is currently only enabled for Peppy,
Slippy, and Falco. This change decreases power consumption when
the AP is not running.
Note that the low speed clock is slow enough that the JTAG cannot be
used and the EC console UART cannot be used. To work around that,
this commit detects when the JTAG is in use and when the EC console
is in use, and will not use the low speed clock if either is in use.
The JTAG in use never clears after being set and the console in use
clears after a fixed timeout period.
BUG=None
BRANCH=None
TEST=Passes all unit tests.
Tested that the EC console works when in deep sleep.
Tested that it is possible to run flash_ec when in deep sleep and
using the low speed clock.
Change-Id: Ia65997eb8e607a5df9b2c7d68e4826bfb1e0194c
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173326
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rambi shares several of the control signals (CTL1, ILIM_SEL) between
both ports, and hard-wires some of the others (CTL2, CTL3). It still
has separate enable lines for each port.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=boot system; gpioget shows (in part)
1 USB_CTL1
0 USB_ILIM_SEL
1 USB1_ENABLE
1 USB2_ENABLE
Then do 'apshutdown' and gpioget shows
1 USB_CTL1
0 USB_ILIM_SEL
0 USB1_ENABLE
0 USB2_ENABLE
Change-Id: Ib3d321ca2b0aa7dce08ddd6633810a75641bc9a8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Every chipset had its own header file just to declare a GPIO interrupt
handler. Since this seems to be a common feature of the power
interface, make a standard power_interrupt() API provided by
chipset.h. This lets us get rid of 4 include files, and makes it
easier to add more chipsets in the future.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I1fc5612d42625ea46e0a8e16a83085b66d476664
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173745
On many of the Haswell boards, RCIN# was attached to PL6, which is not
an open-drain capable GPIO. As a workaround, we toggle it to an input
to get it into a high-Z state. Now that we understand the problem,
document it and remove the FIXME tag from the comments.
Baytrail systems map RCIN# to a different pin, so don't need this
workaround at all.
BUG=chrome-os-partner:20173
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I545a90a523e2967fad40bd47cb47a51983a37bdb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173796
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This pin should not be driven, it is the source of massive leakage
from PP3300_EC rail into PP3300_PCH.
BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-ec, verifed with scope
Change-Id: I8b4ba7e2e842505244b2c7c55cd661ae9363dbad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173839
Reviewed-by: Randall Spangler <rspangler@chromium.org>
These are changes ported from other haswell systems that are
useful in development. Pause in S5 can be used for power cycle
testing and the CPU throttle is important for runin since there
is no other active throttle methods.
BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-ec
Change-Id: I8774a466141f2cdc671a5e14705ae29433f94981
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173838
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This console command is useful during bringup to interrogate
devices on the EC I2C interfaces.
Ported from STM32 into the common file. This command now
takes an additional argument for the port to be used.
BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-ec, tested on samus
Change-Id: I8308fbc2f34e369a20051dca9c5d43872f239777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173837
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The backlight controller EEPROM is not enabling PWM mode and
it is reloaded every time the backlight state is changed.
Since we no longer have signals indicating when the PCH is
enabling or disabling backlight this hack will read the
controller every second at runtime to determine if it needs
to enable PWM mode.
This should be removed with the next build when the EEPROM is
changed to enable PWM mode by default.
BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-ec
Change-Id: I5c4acb1115acb7a4a5b04d09c1317778eeb2998d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173836
Reviewed-by: Randall Spangler <rspangler@chromium.org>
