Also removes unused recovery request, since AP handles that internally now.
BUG=chrome-os-partner:10685
TEST=manual. From root shell,
ectool reboot_ec RO -> EC reboots to RO, AP stays up
ectool reboot_ec A -> EC reboots to A, AP stays up
ectool reboot_ec cold -> EC reboots, AP shuts down
ectool reboot_ec cold at-shutdown -> (EC stores request, but doesn't reboot)
shutdown -P now -> EC reboots when AP shuts down
ectool reboot_ec cold at-shutdown -> (EC stores request, but doesn't reboot)
ectool reboot_ec cancel -> (EC stores cancel-request)
shutdown -P now -> AP shuts down, but EC doesn't reboot
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I51bbf997f6b7f94fe61f06a8a1804c3cc5c319b8
Reviewed-on: https://gerrit.chromium.org/gerrit/25791
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add this option to make panics easier to decode.
Also put panics in a new stack for snow.
BUG=chrome-os-partner:10146
TEST=manual:
build for all boards
On snow, cause a panic and see that it is reported correctly.
Change-Id: If0b90ec0cec4ccb10041bd12bc21b342581e7f62
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24506
This change is picked from daisy change:
I70f66581d0e921c83bc2051b2a521b332e18aa50
It should be reverted after rework all dev boards to new I2C config.
Issue filed against this hack: http://crosbug.com/p/10622
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:10622
TEST=manual
Console commands:
'i2c r 0x90 4' - single byte pmu read
'battery' - double bytes battery read
Change-Id: I3185d872dc5ef6673fcd7efddf8394fe73f11813
Reviewed-on: https://gerrit.chromium.org/gerrit/25743
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
This change adds battery and PMU driver to snow board configuration.
Charging is enabled in init function. EC I2C host is set to I2C2.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:10608
TEST=manual
Run uart console command 'i2c r 0x90 4'.
Change-Id: Ie09749c33c6093a46ba0ea44d42910417a67f37a
Reviewed-on: https://gerrit.chromium.org/gerrit/25501
Tested-by: Rong Chang <rongchang@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Lack of this command could make u-boot pc_keyb.c failed to init (see
lines around line 143 of u-boot/files/drivers/input/pc_keyb.c).
static char * kbd_initialize(void)
{
...
kbd_write_command_w(KBD_CCMD_KBD_TEST);
if (kbd_wait_for_input() != 0x00)
return "Kbd: interface failed self test";
Change-Id: I0a906e0ee4419be74a79ce983c025ce42f02cb81
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:10358
TEST=tested on link.
Reviewed-on: https://gerrit.chromium.org/gerrit/25619
Reviewed-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
The fault status registers sometimes have useful information, so provide
an option to display these.
This adds about 1KB to the code size.
BUG=chrome-os-partner:10146
TEST=manual:
build for all boards
On snow, cause a panic and see that it is reported correctly.
=== EXCEPTION: 03 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :00000047 r2 :60000000 r3 :200013dd
r4 :00000000 r5 :080053f4 r6 :200013d0 r7 :00000002
r8 :00000000 r9 :200013de r10:00000000 r11:00000000
r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a
Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000
mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008
Change-Id: I1a18c85ee63760502c92b300f5a87e57468469a5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24505
Reviewed-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:10662
TEST=manual
1) Boot system with power+esc+refresh. gpioget ENTERING_RW --> 0
2) reboot, then gpioget ENTERING_RW --> 1
3) Check EC_IN_RW signal on AP, if possible
Change-Id: I9de43eecf71654bf337d7a0e8b21f0cbcf386cc7
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25624
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This change is a temperary hack. And it should be reverted after
finalize daisy board design.
The host port on daisy can be configured as I2C1 or I2C2. PMU is
connected directly to the host port, hence the host port can be
detected. This change unifies ec firmware image for different I2C
configurations.
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:10612
TEST=manual
Build daisy ec firmware. Flash it to daisy boards with different
I2C port config. Check uart console commands:
'i2c r 0x90 4' - single byte pmu read
'battery' - double bytes battery read
Change-Id: I70f66581d0e921c83bc2051b2a521b332e18aa50
Reviewed-on: https://gerrit.chromium.org/gerrit/25502
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Mark Hayter <mdhayter@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
The script ensures that the servo parameters are correct,
and restores original servo parameters afterwards.
Daisy EC flashing works from the build tree :
./util/flash_ec --board=daisy --ro
The Link flashing is using the new openOCD 0.5.0 in the chroot.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=./util/flash_ec --board=snow --ro
./util/flash_ec --board=link
Change-Id: Ifc87a8d21a5dac6ad8c4a0fb38694aa5f5bbf992
Reviewed-on: https://gerrit.chromium.org/gerrit/21664
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
1) Smaller start delay for commands
2) Reads can use the entire 128 byte parameter space
This improves read speed from 350ms/64kb to 210ms/64kb.
BUG=none
TEST=ectool flashread 81920 81920 then compare with ec.A.bin
Change-Id: I53d460bace5f21db845a3f8ec681507fca0f7b0e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25562
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The flash commands syntax has slightly evolved
and the watchdog needs to be switched off even though we are doing a
reset halt.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:7420
TEST=flash Link EC using OpenOCD inside the chroot:
sudo USE="ftdi" emerge openocd
sudo openocd -f chip/lm4/servo_v2.cfg
flash_link
Change-Id: Ieef5df682a945646525267a7b702e953796f3f00
Reviewed-on: https://gerrit.chromium.org/gerrit/25561
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chromium-os:31902
TEST=manual
1. reboot ec
2. port80; nothing there
3. powerbtn
4. retype port80 repeatedly during boot and see it fill and then scroll
Change-Id: Id227d5debbdd635332ed2f42bc0f163833031b5c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25442
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
For particularly nasty errors the stack or stack pointer may be corrupt,
or in a place that we do not want overwritten. Provide and option to
place the stack in a fresh place, assuming you can reach exception_panic().
Note that exception_panic() does not write anything to stack itself.
BUG=chrome-os-partner:10146
TEST=manual:
build for all boards
On snow, cause a panic and see that it is reported correctly.
Change-Id: I21d8b9bb12455758309d54ef20de66640d8a2df6
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24504
Rather than just reset with no information when we hit a watchdog, try
to anticipate the problem and display a trace message as on lm4.
This solution is not ideal since we must constantly reset the WWDG to make
it work. It may be better to look at dedicating a timer to this purpose
instead, since we are really just shadowing the IWDG and don't actually
need the reset functionality.
One problem is that we now have a fairly short time limit on many
operations, since if we can't service an interrupt within about 30ms then
the WWDG will reset the system.
It also affects JTAG since it seems that the watchdog goes off the first
time JTAG is invoked to program the flash. The solution here is to retry.
For these reasons it is implemented as an option, CONFIG_WATCHDOG_HELP.
BUG=chrome-os-partner:10145
TEST=manual:
build for all boards
On snow:
> waitms 500
See that there is no message
> waitms 1300
Time: 0x0000000000733ba3 us
Deadline: 0x00000000006b6db2 -> -0.511473 s from now
Active timers:
Task Ready Name Events Time (s)
0 R << idle >> 00000000 0.000000
1 R WATCHDOG 80000000 0.000000
2 KEYSCAN 00000000 0.000000
3 GAIAPOWER 00000000 0.000000
4 R CONSOLE 00000000 0.000000
5 HOSTCMD 00000000 0.000000
--- UART initialized after reboot ---
[Reset cause: watchdog]
[Image: RO, snow_v1.1.32-8c00326-dirty 2012-06-03 07:54:29 sjg@sglass.mtv.corp.google.com]
done
Change-Id: I042fcc9ecd9c21210ea3826ca69c943aab949d1f
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24398
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
We want this function to be available for all chips, so move it into a
generic place.
The task_disable_irq() from the LM4 version can be left in
watchdog_check(), to keep the watchdog_trace() function generic.
BUG=chrome-os-partner:10145
TEST=build for all boards
Change-Id: I98c60ce5958f1498b84a233ef04290a68a7838c5
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24397
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(And maybe other keyboard status in the future...)
BUG=chrome-os-partner:10358
TEST=manual
reboot
kbd -> should show disabled
power on system, wait for it to boot
ctrl+alt+F2 -> should be able to type at console
kbd -> should show enabled
kbd disable -> should no longer be able to type at console
kbd enable -> should again be able to type at console
Change-Id: Icdb38b09f318a47b0413609294b44cd810e8f389
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25353
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Tested-by: Bill Richardson <wfrichar@chromium.org>
The SCB registers are defined in the ARMv7-M architecture, so they are
common to all chips.
We will need System Control Register (SCR aka SYSCTRL) to implement
power management on stm32.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=snow
Change-Id: I35c283731306541b3d21398c96fdca89954fe20a
Reviewed-on: https://gerrit.chromium.org/gerrit/25392
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
When we need to mock modules in a unit test, we need a way to mock
the actual modules. This CL enables mock of given source files.
For example, if we need to mock watchdog for test 'foo', we can add to
test/build.mk: "core-mock-foo-watchdog.o=fake_watchdog.o", and then
implement its own watchdog in fake_watchdog.c.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10356
TEST=Set a mock fake_watchdog.c and check the test is compiled with
fake_watchdog.c instead of watchdog.c.
Change-Id: I4a0afb589a49dad7c4d6faf8926438085cdc46cf
Reviewed-on: https://gerrit.chromium.org/gerrit/24942
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
The current delay is set to 0 second, which causes unexpected shut down
whenever we get an erroneous value. Since 2 seconds is short enough for
EC to respond to CPU overheating event, let's lengthen it to 2 seconds to
prevent this.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10382
TEST=none
Change-Id: I7f971108943d74310b69b97c5f082fb2478f273b
Reviewed-on: https://gerrit.chromium.org/gerrit/25186
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
No code changes, just rearranging source in preparation for an
experiment to see how much the binary shrinks if we disable the
interactive console.
BUG=none
TEST=none
Change-Id: Ie21f1b3dcd04272e80fd40b2ed54d1eaf7fb1cdf
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25232
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Note that util/comm-lpc.c already does this for the host side of the
commnunication.
BUG=chrome-os-partner:10444
TEST=none; all EC responses are currently well-formed
(but do try 'ectool hello' from host and make sure it still works)
Change-Id: I731ed326e281be6a7435edfa03c783225e105b72
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25124
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Previously, the host could write to this space and corrupt the memmap data.
BUG=chrome-os-partner:10210
TEST=manual
From a root shell:
localhost ~ # io_read32 0x960
0x574e5553
localhost ~ # io_write32 0x960 0x1234
localhost ~ # io_read32 0x960
0x574e5553
That verifies that the EC is rejecting host writes on the memmap range
localhost ~ # ectool hello
EC says hello!
That verifies the host is still able to write to the user param range
Change-Id: I8c29571f439a14f308ed73f4c641264e17f944e9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/25115
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This bug unexpectedly comes from 2 related features:
1. Issue chrome-os-partner:7486: stop driving keyboard columns ASAP when
power button is pressed. This is to avoid the keys on ESC column to
reset the system if the power button is also pressed. This is done by
keyboard_enable_scanning(0) in power_button_interrupt().
2. During the booting, the power button state is set to BOOT_RECOVERY and
will ignore the power button release (to avoid confusing the host).
However, before the state is set back to IDLE, the
power_button_interrupt() can be triggered ever so that the matrix scan
is disabled.
Therefore, we have to enable the matrix scan in the BOOT_RECOVERY (and
the derived EAT_RELEASE) because they ignore power button release.
Note that in the regular states, the power_button_released() is called
after debounce time. They are fine.
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:10358
TEST=Press ESC+Refresh+Power for many many times with vatious hold time.
The tab key works to disable the recovery reason.
Change-Id: Ic05fc6e22caadb4a3892a4b201dd5bfc7e9c3f44
Reviewed-on: https://gerrit.chromium.org/gerrit/24991
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com>
Move the implementation of panic into C code. Only a very small part
needs to be in assembler, and the reset is easier to maintain as C.
As part of this, define panic_putc() and panic_puts() which directly
wite to the UART.
To make things more convenience for the future, add a simple printf()
implementation in the panic path. This is not reliant on the uart
buffering system being in a happy state. However, we do call the
emergency flush so that our panic message will appear after previous
output rather that surpressing it (which would be extremely confusing).
Code/data size for panic.o grows by about 200 bytes, but this is mostly
due to the increased flexibility.
text data bss dec hex filename
292 272 0 564 234 old panic.S
692 3 48 743 2e7 new panic.c
BUG=chrome-os-partner:10146
TEST=manual:
build and boot on snow:
> rw 0x06000000
=== EXCEPTION: 03 ====== xPSR: 01000000 ===========
r0 :0000000b r1 :00000047 r2 :06000000 r3 :200013dd
r4 :00000000 r5 :080052cc r6 :200013d0 r7 :00000002
r8 :00000000 r9 :200013de r10:00000000 r11:00000000
r12:00000000 sp :200009a0 lr :08002a5d pc :08003962
Rebooting...
Change-Id: If3e3f572e0f32af780b6ebda235b1b3cde4de5e4
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24503
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add the minimal amount of stubs (namely MOSCCTL, UARTCC and FLASH_FMPPEx
registers) to the emulation to be able to boot link EC firmware and
pass OS tests.
the QEMU binary is generated from the chromeos-ec-0.15.1 sandbox of the
chromium.org qemu.git repository at hash 1a48940.
I will add next better GPIO control and default states to ensure we are
booting the proper mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10240
TEST=make qemu-tests BOARD=link
./util/run_qemu_test -b link
Change-Id: I3d7b9247628133289e0ef04bb7d85c7438b6ed81
Reviewed-on: https://gerrit.chromium.org/gerrit/24880
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Perviously we have a 10-second delay for all temperature sensor. This is
not suitable for CPU temperature. Let's change that to have an option to
set the delay length for each temperature sensor. And also shorten the
delay of TMP006 sensor to 7 seconds, that of EC internal temperature to
4 seconds, and that of PECI CPU temperature to 0 second.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:10233
TEST=Check EC issued warning as soon as CPU temperature reached the
threshold.
(cherry picked from commit cf24df7f3ee24eaa5dbeae3b304d11ddada9a914)
Change-Id: Id2cc4a437bde15697afe4020b6153e5d13466759
Reviewed-on: https://gerrit.chromium.org/gerrit/24694
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Vic Yang <victoryang@chromium.org>
Commit-Ready: Vic Yang <victoryang@chromium.org>
- update strings which were modified by the message text "compression"
- updated QEMU which supports a couple of additional registers for LM4F
(getting internal oscillator calibration status and writing timer
counter through TAV)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:10008
TEST=make qemu-tests
Change-Id: Idf0ee13f354b4e14405e949861d426f3e4c3022b
Reviewed-on: https://gerrit.chromium.org/gerrit/24827
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
When recovery is required, it will be because there's either a hardware pin
pulled somewhere, or because the recovery_reason is set in NVRAM. Coreboot
and U-Boot can see both of those, so the EC shouldn't make up a new reason.
If it does, it changes the original cause.
BUG=chrome-os-partner:9706
TEST=manual
Reset the EC using ESC+Power (Refresh+Power on EVT). At a root shell, run
crossystem recovery_request=11
reboot
When you see the Recovery screen, press TAB. It should say
recovery_reason: 0x0b We have no idea what this means
Prior to this fix, you'd see recovery_reason 2 instead, which is wrong.
Change-Id: Ie54185471927e7e829962d30bba9d142d593088f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24152
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Off-by-one is not my friend.
BUG=chrome-os-partner:10206
TEST=manual
1. rw 0x20000000
2. ww back the same number printed
3. rw 0x20000000. should match
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I61e0d26cf4cb274a88326d4e7d24ff1c82d6e515
Reviewed-on: https://gerrit.chromium.org/gerrit/24756
Reviewed-by: Simon Glass <sjg@chromium.org>
When kb_fifo_start is 0, the index calculation yields -1 because C got
the mod (%) operation arguably wrong. By adding KB_FIFO_DEPTH to the
index before computing the mod with respect to KB_FIFO_DEPTH, we avoid
the negative case and (obviously) produce the same result in all other
cases.
BUG=chrome-os-partner:10247
TEST=saw incorrect state from kernel log before fix: could not repro after.
Signed-off-by: Luigi Semenzato <semenzato@chromium.org>
Change-Id: I3a30c229dc9f762dd45203e842128811a24cf53f
Reviewed-on: https://gerrit.chromium.org/gerrit/24730
Tested-by: Luigi Semenzato <semenzato@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Ready: Luigi Semenzato <semenzato@google.com>
Some terminals do not generate backspace correctly, so accept delete
as a substitute.
BUG=chrome-os-partner:10147
TEST=manual:
ssh into workstation, then telnet to serial port (with ser2net running)
See that the backspace key now works correctly, instead of injecting
strange characters into the terminal.
Change-Id: Ief6f2bcab9b8e82cb5720d18c596326b49ffc336
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24715
Reviewed-by: Randall Spangler <rspangler@chromium.org>
We were going straight to S5. When the PCH first goes into S5 after
power-loss, it decides to boot for some reason. So, stay in G3.
Still exit G3 if waking from hibernate or if the power button is
pressed when the EC boots on a power-on reset.
BUG=chrome-os-partner:10239
TEST=manual
1) Unplug battery and AC power. Plug in AC power. System does not boot.
2) Press power button. System boots now.
3) From console, 'hibernate 10'. Close and open lid. System boots.
4) From console, 'hibernate 10'. Press power button. System boots.
5) Hold power+esc+refresh. System boots into recovery.
6) Hold power+esc. EC reboots. Release esc. System stays off.
7) Unplug battery and AC power. Plug in AC power while holding power button.
System boots.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Change-Id: I7612a40ab5ebe41d356ac3a6b89cedf1174125f4
Reviewed-on: https://gerrit.chromium.org/gerrit/24729
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
EVT uses power+refresh as the Silego combination not power+esc, so
holding down power+esc+D wouldn't turn on the fake dev switch, and
holding down power+refresh+D wouldn't either because on a short enough
tap the EC would measure refresh as still held down.
BUG=chrome-os-partner:10210
TEST=manual
1) hold down reset combo + D -> turns on fake dev mode
2) hold down reset combo + F -> turns off fake dev mode
Change-Id: I85b51d3684500ae821513e71a2cd01aa4fcf5e8f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24646
Should be no functional changes; this is just rearranging code.
BUG=none
TEST=boot system and type on console; should still work
Change-Id: I1c0d44db2d32048b1aaf458728b887b4a008c8cd
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24644
Also add snprintf(), and %X format code.
BUG=chrome-os-partner:10206
TEST=timerinfo; should print correctly. 'ectool battery' on host side should print same serial as 'battery' on EC console.
Change-Id: I5c9f69d1a20ee5d0a59440c122655adbf62c9aea
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24635
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Some things about watchdogs are common across Cortex-M3, so create a
common watchdog file to hold these. Put the watchdog task in there as
the first customer.
BUG=chrome-os-partner:10145
TEST=build for all boards
Change-Id: Id55f71a807ee12bae3758afc213c30c731eadc07
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/24395
Reviewed-by: Randall Spangler <rspangler@chromium.org>
