This adds explicit "int fan" args to the exported functions from
common/fan.c: fan_set_percent_needed() and fan_percent_to_rpm(). Within that
file, multiple fans are handled independently.
This is not complete, though. Host commands and sysjump support still only
handle a single fan, so at the moment multiple fans are treated identically
in those cases.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
All boards build, "make runtests" passes.
On a multi-fan system, the EC command "faninfo" displays multiple results:
> faninfo
Fan 0 Actual: 0 rpm
Fan 0 Target: 0 rpm
Fan 0 Duty: 0%
Fan 0 Status: 0 (not spinning)
Fan 0 Mode: rpm
Fan 0 Auto: yes
Fan 0 Enable: yes
Fan 1 Actual: 0 rpm
Fan 1 Target: 0 rpm
Fan 1 Duty: 0%
Fan 1 Status: 0 (not spinning)
Fan 1 Mode: rpm
Fan 1 Auto: no
Fan 1 Enable: no
>
and the "fanduty", "fanset", and "fanauto" all require the fan number as the
first arg:
> fanduty 0 30
Setting fan 0 duty cycle to 30%
> fanset 1 2000
Setting fan 1 rpm target to 2000
> fanauto 0
> fanauto 1
On single-fan systems, there is no visible change.
Change-Id: Idb8b818122e157960d56779b2a86e5ba433bee1b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175368
Reviewed-by: Randall Spangler <rspangler@chromium.org>
All the current data buffers *are* aligned, but we should check anyway
just to avoid unpleasant surprises in the future. This matches what
we do on STM32L. On STM32F, we copy a byte at a time so alignment of
the source data doesn't matter.
BUG=chrome-os-partner:9526
BRANCH=none
TEST=manual
flasherase 0x20000 0x1000
flashwrite 0x20000 0x200 -> succeeds
flashwrite 0x20201 0x200 -> fails
Change-Id: Id1a0fd8f6871e1fcdc3f55ec25eea40f33b5214c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175532
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Fixed bug in which two different tasks reading two different ADC
channels could interfere and cause the ADC clock to get disabled
when a read is still in progress, thus causing a reboot.
Added a runtime assert to verify that developers don't sample the
same ADC channel from multiple different tasks, which could cause
hard to trace reboots.
BRANCH=none
BUG=chromium:313872
TEST=1) Added console command to continuously read an ADC channel not
read anywhere else. Verified that when running this console command
I could reproduce the bug every few minutes.
2) Wrote code in adc.c to protect the ADC clock resource.
3) Ran console command from step 1 for ~2 hours with no reboots.
Change-Id: Ic1905dde12871a4b93957702f7f31a25a2762bb4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175404
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update comments with more info, or remove if no longer applicable.
No code changes.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: I5b56eeb500bc0f00e84e91ef99684f4b1b310972
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175418
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add bug links, reword, or remove as applicable.
No code changes, just comments.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: Id55dd530c10091d7ab9d0f942f750168fca793b4
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175326
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Add bug references. Remove one assert that can no longer be triggered.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I3f4d2e4f2f3343a8d0531cb0715d151eaa4d0b50
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175293
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Remove comments if no longer applicable, or assign bug numbers if they
still are. Tidy some debug output. No code changes other than the
debug output.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms, pass unit tests
Change-Id: I2277e73fbf8cc93f3b1b35ee115e0f2f52eb8cf9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175215
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Instead of just configuring fan support as yes/no, we'll use it to specify
the number of fans on the board. Undefined (not zero!) means no fan support
at all.
Syntax change only. No new functionality.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
make runtests, build all platforms, build and test on Link.
Change-Id: Iff65efa69e05f3e1a54fdc2a8da9001b4e8487ca
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175150
This looks like a lot, but it's really just moving the non-board-specific
stuff from chip/lm4/fan.c into common/fan.c, updating the appropriate
headers, and renaming functions to better match the new location.
This is entirely code refactoring and renaming. No new functionality.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
make runtests, build all platforms, build and test on Link.
Change-Id: I7dc03d6732bad83cf838a86600b42a7cff5aa7aa
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175012
All hibernate register writes must wait for the WC bit. When we're
enabling the RTC alarm, it's important to wait for the WC bit
afterwards, too, or else we could go into deep sleep before the write
to HIBIM is committed.
Also make sure that the normal hibernate() path enables the RTC alarm
if it has a timeout. This bug wasn't noticed until the low-power idle
code called system_reset_rtc_alarm(), since before then HIBIM was
initialized to 1 and just stayed there.
BUG=chrome-os-partner:23678
BRANCH=anywhere we use low power idle (wolf/leon, too)
TEST=with hacked firmware, note that HIBIM=1 just before the wfi
instruction in chip/lm4/clock.c
Change-Id: Ie01b106ac6a6c5894811f9a333715b22ef896f82
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175013
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This chip returns ver/family/partno = 0x10de, as indicated by the
datasheet. Also switch the identification code to use a switch
statement rather than re-reading the DID1 register in if-then-else.
BUG=chrome-os-partner:23679
BRANCH=none (maybe haswell branches, but it's largely cosmetic)
TEST=version command on rambi identifies the chip as ti tm4e1g31h6zrb B1
Change-Id: I4a3748413de65d3116feb7c444f5a2af5953eecd
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175008
Reviewed-by: Vic Yang <victoryang@chromium.org>
On the LM4, all pwm functions are implemented through hardware "fan"
modules. This change abstracts the hardware fan stuff from the higher level
pwm and fan control logic. Those are still chip-specific at the moment, but
may be moved into common with a future CL.
BUG=chrome-os-partner:23530
BRANCH=none
TEST=manual
Code refactoring only, no new behavior. All tests build and pass, and I
tested on Link with some manual pwm and fan commands on the EC console.
> fanduty 30
> faninfo
Should report ~4500 RPM
> fanset 7000
> faninfo
Should report ~48% duty cycle.
> fanauto
Back to automatic control.
> kblight 0
> kblight 10
> kblight 50
> kblight 100
Keyboard backlight should glow appropriately.
Change-Id: I7558f36b2626e555fc8dabdd12660fa484a93b7f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174991
Reviewed-by: Randall Spangler <rspangler@chromium.org>
QEMU tests served us well, but it has been more and more difficult to
maintain as we now have more chips and use more functionality from each
EC chip. With emulator tests in place to test common code and hardware
test to test per-chip/per-board drivers, it's time to remove QEMU tests
to simplify our code base.
QEMU tests that are covered by other emulator tests are removed
completely; tests that are not covered are left alone for now to
preserve the test logic.
BUG=chrome-os-partner:18343
TEST=util/make_all.sh
BRANCH=None
Change-Id: I5a4dd2f5ac42f7f66f86fdce0b62dbd2c65bf66a
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174669
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
To conform to our mutating naming conventions, let's rename the
chip-specific PWM header file to have the string "_chip" in it.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: I6584be8e54fd24c8638559817e150c707bc0edb5
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174884
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reset the DMA status after the end of the conversions,
else we will exit too early at the next call of the function and the
values before they are actually transfered.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run "adc" command several times and always see proper value for
each ADC.
Change-Id: I7ad335fffa2da34a4b715e9f0c9927bf06baef8f
Reviewed-on: https://chromium-review.googlesource.com/174397
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Changed ADC clock gating to disable the ADC module to conserve power,
and only enable it when needed. This saves about 15% of the power
consumed by the EC when the AP is running.
BUG=none
BRANCH=none
TEST=Run the ADC stress test. This runs 2000 consecutive ADC
reads of all the channels and verifies that the ADC module
successfully records the samples. Note that when running this
test make sure all other calls to read an ADC channel are
disabled because the ADC read function does not protect
against different tasks accesses.
Change-Id: I9ca3671d8cf68e09d21c9c2594856f9c08476398
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174580
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previously, it was really confusing whether I2C_PORT_HOST meant the
port where the EC was the master, or the port used to talk to the AP.
No functional changes, just a global find/replace and some tidying of
unused comments.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: Ia591ba4577d3399729556e0234ba0db3a0e3c5ea
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174546
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Device-specific headers belong in driver/ or chip/. The include/
directory should be for common interfaces.
Code should not normally need to include driver-specific headers. If
it does, it should use the full relative path from the EC project root
(for example, drivers/charger/bq24715.h).
Change-Id: Id23db37a431e2d802a74ec601db6f69b613352ba
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173746
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
The EC LPC implementation guarantees that the status byte will have at
least one zero bit, so there's no need to scan the parameter space as
well. Removing this unneeded check will slightly speed up ectool.
BUG=chrome-os-partner:10963
BRANCH=none
TEST=on an x86 chromebook (e.g. link), ectool hello still works
iotools io_read8 0x200 && iotools io_read8 0x204 -> not both 0xff
Change-Id: Ic02ca0ee686ab10e50093807717ec638aaa468c6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174059
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Some of the comments no longer apply. Others needed more info.
No code changes; just comment changes.
BUG=none
BRANCH=none
TEST=build all platforms
Change-Id: I1d52aa9a98427a78c9d9a8cf44934fb04c3c00c8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174084
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Changed the low power idle task to use the low speed clock in deep
sleep. The low power idle task is currently only enabled for Peppy,
Slippy, and Falco. This change decreases power consumption when
the AP is not running.
Note that the low speed clock is slow enough that the JTAG cannot be
used and the EC console UART cannot be used. To work around that,
this commit detects when the JTAG is in use and when the EC console
is in use, and will not use the low speed clock if either is in use.
The JTAG in use never clears after being set and the console in use
clears after a fixed timeout period.
BUG=None
BRANCH=None
TEST=Passes all unit tests.
Tested that the EC console works when in deep sleep.
Tested that it is possible to run flash_ec when in deep sleep and
using the low speed clock.
Change-Id: Ia65997eb8e607a5df9b2c7d68e4826bfb1e0194c
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173326
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This console command is useful during bringup to interrogate
devices on the EC I2C interfaces.
Ported from STM32 into the common file. This command now
takes an additional argument for the port to be used.
BUG=chrome-os-partner:23449
BRANCH=samus
TEST=emerge-samus chromeos-ec, tested on samus
Change-Id: I8308fbc2f34e369a20051dca9c5d43872f239777
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173837
Reviewed-by: Randall Spangler <rspangler@chromium.org>
stm32l100 is mostly identical to stm32l151,
excepted that the RAM is smaller (10kB instead of 16kB for the RB SKU),
the EEPROM is smaller, there is no touch capability (but we are not
using those 2 features).
So, in the new stm32l100 variant configuration, we adjust the memory
size to 10kB and keep the regular UART RX buffer size (512 B) rather
than putting a 2kB buffer to fit in the new constraints.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=run on discovery board reworked with stm32l100rct6 and Nyan
reworked with stm32l100rbt6.
Change-Id: Ifd78f59a102b3079f0f794af8058211dc724153d
Reviewed-on: https://chromium-review.googlesource.com/173632
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
Add some missing descriptions in config.h and rename a few defines to
be more consistent.
No functional changes, just comments and symbol renaming.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all platforms; pass unit tests
Change-Id: I05a9a2ed6fd7bc8b14a18a0dc57d7d22430de21a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173111
Reviewed-by: Vic Yang <victoryang@chromium.org>
Rather than scan the entire GPIO table, stop as soon as all interrupt
bits have been handled. We hand-order the table so GPIOs with
interrupts are first, so this should reduce interrupt overhead.
BUG=chrome-os-partner:23296
BRANCH=none
TEST=boot rambi
x86indebug -1
apshutdown
powerbtn
...That should print lots of 'x86 in' debug messages as pins
change state, showing that the interrupt handlers are still responding.
Change-Id: I7942cd51870ad51de068d90d68cf6634ff2fb1a0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173031
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
First implementation of a low power idle task for the LM4 chip. The
low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a
board.h file. This commit turns it on for Peppy, Slippy, and Falco
only because those are the only boards tested.
When using the low power idle task, the chip goes in to deep sleep
when it can. Deep sleep disables clocks to most peripherals and puts
the onboard flash and RAM into a low power mode. The chip is woken
out of deep sleep using the RTC in the hibernate module. Increased
the idle task stack size to handle more involved idle task.
In board.c, the array of GPIO info can be used to select which GPIO
points can wake up the EC from deep sleep. Currenlty selected are
the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5.
Additionally the port with the KB scan row GPIO point is also
enabled to wake up the EC from deep sleep.
Signed-off-by: Alec Berg <alecaberg@chromium.org>
BUG=None
BRANCH=none
TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no
noticeable side affects. Verified that the power consumed by the EC
is lower when in S3, S5 and G3 by scoping the sense resistor
powering the chip.
Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726
Reviewed-on: https://chromium-review.googlesource.com/172183
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
When the EC CPU is running at a decreased clock frequency, frequent
keyboard scans can starve other EC tasks of CPU and lead to dropped
data or watchdog timeouts.
Enforce a minimum number of EC clocks between keyboard scans to
prevent this from happening. The default chosen (16000 clocks) is
equal to the shortest post-scan delay (1 ms) of any current board when
the AP is in S0, so this should have no effect when the AP is in S0.
When the AP is in S3 or S5, we don't need to scan the keyboard as
frequently anyway. This can be overridden on a per-board basis for
future boards if needed.
BUG=chrome-os-partner:23247
BRANCH=pit
TEST=apshutdown, then hold down a key for 10 seconds. Should not see a
watchdog reset.
Change-Id: I228f53a32ad4769f6a137a9ab06903111bea115d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172895
Reviewed-by: Vic Yang <victoryang@chromium.org>
Rambi's Silego chip inverts the pull as well as the signal. So it has
a pulldown for the signal instead of a pullup. The EC must drive the
signal push-pull, since open-drain only works for signals with pullups.
BUG=chrome-os-partner:23198
BRANCH=none
TEST=type on keyboard; C/D/E/3/F1-F4 should all work
Change-Id: Iaea4f540c523824571a568b70cca3e0fb467f79c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Silego chip used on Rambi inverts column 2. So the EC should pull the signal low when NOT scanning column 2, and release it at all other times.
BUG=chrome-os-partner:23198
BRANCH=none
TEST=not yet; need to probe on scope
Change-Id: If6a784493533f11ae54d18f27591697e69aa2282
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172674
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Created a new function to enable or disable clocks to various
peripherals. This new function makes it easy to specify if you
want the clock enabled in run mode, sleep mode, and/or deep
sleep mode.
Added infrastructure to specify which GPIOs should interrupt the
EC from deep sleep.
BUG=none
BRANCH=none
TEST=Passes all unit tests. Ran on a peppy and verified that
the clock gate control registers in run mode (LM4_RCGC regs)
were the same before and after this change.
Change-Id: Ia5009ac8c837f61dca52fe86ebdeede2e1a7fe4d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172454
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Rambi has a pair of LEDs which are attached to the PWM fan controller.
Add support for them. Also add a generic 'pwmduty' command which can
be used to get/set the duty cycle for any PWM channel.
Also fix rounding errors in pwm module, so that set/get duty doesn't
keep rounding down.
BUG=chrome-os-partner:22895
BRANCH=none
TEST=Boot rambi. LEDs are off.
pwmduty -> both are 0%
pwmduty 0 10 -> green LED on dimly
pwmduty 1 10 -> red LED on dimly
pwmduty 0 99 -> green LED on brightly
pwmduty 1 100 -> red LED on brightly
pwmduty 1 0 -> red LED off
pwmduty 1 -1 -> red LED turns back on because fan controller is disabled
pwmduty -> channel 0 at 99%, channel 1 disabled
Build all platforms. Pass all unit tests.
Change-Id: Ib0a6289a757554e696a9a0153a85bdc34e2ee2ae
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172094
We only used I2C_PORTS_USED to iterate through the list of hardware ports
actually in use, but we defined it in board.h at the same place where we
matched particular I2C devices to the (possibly shared) buses they're on.
This CL makes I2C_PORTS_USED into a global constant, so it can be set
automatically where we initialize the ports, and doesn't have to be
related to the list of attached devices.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=manual
Build everything, run all tests, should still work.
Change-Id: I65f22f5cadfc4b3afe51af48faa5fb369bc3aa09
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171884
include/config.h should have the canonical list of all CONFIG_* macros used
everywhere else. This fixes some that weren't included, and some that had
been changed in one place but not in others.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=manual
Build everything. It should still work.
cd src/plaform/ec
make runtests
for i in bds bolt daisy discovery falco kirby link mccroskey peppy pit puppy rambi samus slippy snow spring; do make BOARD=$i || touch died.$i; done
There shouldn't be any died.* files.
Change-Id: I0a1ec2d57668509c514dc5a521e547836a3e9894
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171690
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Every board other than link does the same thing - filter out the power
button event, then set the WAKE_L gpio level based on the remaining
events. This code doesn't need to be duplicated 7 times, so make it common.
Link didn't filter out the power button wake signal, but works fine
with the common implementation. Like the other boards it gets a power
button wake event via the dedicated PCH PWRBTN# signal.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=suspend link, then wake using power button press
compile all platforms; pass unit tests
Change-Id: Ib3a6d310d0f5e337374b3c331ab2872fe377bdf6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171405
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We don't use the EEPROM block on the LM4 chip, but if we ever do we'll
want this off-by-one error fixed.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=Build bds, since that's the only board which even compiles this code.
Pass unit tests.
Change-Id: I598f043cf00ebc1eca75fa6e6b7815d85a61e353
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171141
For all GPIOs, the current values are recorded. A test can then change
the value of a GPIO input by gpio_set_level(). The changed value is
recorded and also interrupt is fired if the change fits the interrupt
flags defined in board/host/board.c.
BUG=chrome-os-partner:19235
TEST=Pass all tests
BRANCH=None
Change-Id: If8e547e5adf4a20dcb118f5fe2187293005d4ca3
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170907
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This just does a copy/rename from Bolt. Tweaking for Samus' peculiarities
will come next.
BUG=chrome-os-partner:22870
BRANCH=none
TEST=manual
The only thing we can check is that it compiles:
cd src/platform/ec
make BOARD=samus
Change-Id: Ied95ebdd1137548b21334b4a65a298c68482c517
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171081
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This provides an interface to detach and re-attach fake I2C devices,
which can be used to test I2C connection failure.
BUG=chrome-os-partner:19235
TEST=Pass sbs_charging test along with the next CL
BRANCH=None
Change-Id: Ibfee79b13d45e62377d894aa28547e77bef2189e
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170752
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the PWM interface refactoring, only the CPU fan uses the fan.h
interface. All other PWM channels (keyboard backlight, etc.) use the
pwm.h interface. Remove the unused constants, and rename FAN_CH_CPU
to CONFIG_FAN_CH_CPU so it fits with the other fan config options.
No functional changes; just renaming things.
BUG=chrome-os-partner:18343
BRANCH=none
TEST=build all targets; pass unit tests
Change-Id: I391fbeaf54afcc29a11c2799a4520b7ad8784796
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170534
Reviewed-by: Vic Yang <victoryang@chromium.org>
This should have all the correct GPIO mappings.
Chipset and charger tasks are currently disabled, until we bring up
the voltage rails and I2C communication.
BUG=chrome-os-partner:22895
BRANCH=none
TEST=compiles; everything else needs to wait until we get hardware
Change-Id: Iea49fe7ab8bd17f61c8cc6c71f236a503418ee28
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170540
Reviewed-by: Vic Yang <victoryang@chromium.org>
This moves the mock function from common layer down to physical layer to
complete the test of common layer.
Also disable flash test for hardware tests, as this is only testing
common layer.
BUG=chrome-os-partner:19236
TEST=util/make_all.sh
BRANCH=None
Change-Id: Idd1c2c44591952894486f84d428872cfbf2cfdad
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170297
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Currently, it doesn't compile unless CONFIG_FAN is defined.
BUG=chrome-os-partner:22803
BRANCH=none
TEST=temporarily undefine CONFIG_FAN in board/link/board.h; code compiles
and all unit tests pass
Change-Id: I251d670ccd299f7a50b1455364a817e07fad4cb1
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170106
Currently, CONFIG_UART_HOST must be defined for all LM4-based
platforms. Future platforms may not need host UART support, so make
it optional.
BUG=chrome-os-partner:22802
BRANCH=none
TEST=Temporarily comment out CONFIG_UART_HOST in board/link/board.h;
code still compiles.
Change-Id: I8775d9daaf8f6e45f1f374c9be7f10316611447f
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170104
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
To test drivers, we need a way to fake I2C periphrals. With this CL, a
fake peripheral can be done by declaring its own I2C read/write
functions. The fake I2C peripherals may return EC_ERROR_INVAL to
indicate it's not responding. The emulator I2C read/write call scans
through all registered I2C peripherals and uses the first response.
BUG=chrome-os-partner:19235
TEST=Pass sbs_charging test with the next CL.
BRANCH=None
Change-Id: I9380dc40e147781b42e09eb6979c864bbd9f2ac4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169511
Reviewed-by: Randall Spangler <rspangler@chromium.org>
STM32 has a single-byte mailbox for UART I/O. When the core clock
runs at 16Mhz we can service interrupts fast enough to handle 115200
baud input, but when we drop to 1MHz we drop characters. Using DMA to
receive input solves this problem.
The STM32 DMA engine can only generate interrupts when the transfer is
half-done / all-done, so we need to poll the DMA receive-head-pointer
to see if individual characters have been received. Do this in the
tick task (every 250ms). When a character is received, poll more
quickly for a bit (5 times before the next tick) so the input console
is more responsive to typing.
BUG=chrome-os-partner:20485
BRANCH=none
TEST=Console is responsive to debug commands. For example, help -> prints help
apshutdown -> shuts down AP
arrow keys -> move cursor and scroll through command history
Ctrl+Q, help, wait a second, Ctrl+S -> help output printed after Ctrl+S
Then in chip/stm32/config_chip.h, comment out #define CONFIG_UART_RX_DMA
and rebuild/reflash the EC. When the AP is up, the console works normally
but after 'apshutdown', the EC drops to 1MHz core clock, and the arrow
keys don't work. (This step confirms that adding DMA support did not
change the behavior of systems where CONFIG_UART_RX_DMA is not defined.)
Change-Id: I199448354824bd747c7b290ea7fd5ccf354c11bb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169406
Reviewed-by: Simon Glass <sjg@chromium.org>
