Build the hardware version string from the register definitions,
so I no longer forget to update it.
Check it at runtime against the build version registers.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the console command line,
type "version" and see the following string:
"Chip: g cr50 A1 20141203_224409"
Change-Id: I6d902780d42f2dd18a57ccc08fd4ba4fee5ebc7c
Reviewed-on: https://chromium-review.googlesource.com/233582
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
- record and display reset cause
- add the hard reset option
- add the scratchpad to store values across reboots.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:33818
TEST=On the console command line, chech the "[Reset cause: xxx]" string
- for the initial reset cause
- use "waitms 4000" to trigger a watchdog reset
- use "reboot soft"
- use "reboot hard"
The "utils" test is now building and passing.
Change-Id: I68c7096e5b7bfd102be89fd8eef6fe20da37a6f8
Reviewed-on: https://chromium-review.googlesource.com/233581
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Implement a driver to trigger a watchdog reboot if we are stuck
somewhere. Also display a nice warning when we reach half of the
watchdog period.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On the console, type "waitms 500" and see nothing,
type "waitms 2000" and see the watchdog warning.
Type "waitms 4000" and see the warning, the platform rebooting.
Change-Id: Iac5d0100febd5eab1ae6cfac5a47ff728ebda3a6
Reviewed-on: https://chromium-review.googlesource.com/233430
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
We were losing timer events because usecs_to_ticks(deadline) was
clipping the value when deadline was larger than 0x08888888 (deadline is
a timestamp rather than a delay).
The computation of the timer deadline has been modified to avoid the
clipping issue.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:34347
TEST=run on Cr50 with the watchdog activated and no longer see watchdog
warnings.
Run the "timer_calib" test and see that the 1s sleep is 1000038 us :
make BOARD=cr50 tests
fhl ../build/cr50/timer_calib/timer_calib.RO.hex
Change-Id: Id2200a89eb1b72099e536291af321609b24b4777
Reviewed-on: https://chromium-review.googlesource.com/233531
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
CL to migrate the flashing VDMs from zinger's custom vdm to
common/usb_pd_flash.c such that other updateable type-C devices can
share.
Additionally adds gaskets to call standard runtime flashing facilities
for USB-PD devices using it.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,
Try following:
1. From samus_pd console w/ zinger in port 1
pd 1 flash version
pd 1 flash reboot
pd 1 flash info
2. From samus linux prompt w/ zinger in port 1
ectool --name cros_pd flashpd 1 1 <zinger RW payload>
Reading 16384 bytes from
/usr/local/zinger_v1.1.2528-d809e42.ec.RW.bin...
Erasing expected RW hash
Rebooting
Erasing RW flash
Writing RW flash
Rebooting PD into new RW
Complete
3. Repeat 1&2 above on hoho & dingdong.
Change-Id: I018055fa9de128f937c57debdc21dea026137bcf
Reviewed-on: https://chromium-review.googlesource.com/231835
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Todd Broch <tbroch@chromium.org>
Until we implement a proper reset of the microcontroller,
add a reset of the Cortex-M3 CPU core in system_reset() in order to
avoid getting stuck in a weird loop if we get a panic.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=trigger a data abort and verify we are not going into a panic loop.
Change-Id: Ie046379e6a9469bd683fa774cdc9abb10a14e8f1
Reviewed-on: https://chromium-review.googlesource.com/233109
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
A non-zero error code returned by the callback causes EP0 to STALL.
This is the common mechanism used in USB to indicate an error while
processing a control request. This simplifies the implementation
of interface callbacks.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I89ceb4892f9f810fcaf6e975e6982fc5b2ae447b
Reviewed-on: https://chromium-review.googlesource.com/232368
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When using gpio_set_flags_by_mask() to modify a GPIO pin setting, the
former code was not able to revert an open-drain GPIO into push-pull
mode (the other way round was working). Fix it to be able to transition
in each direction.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=all
BUG=none
TEST=on Twinkie, run "tw res none RP3A0" then "adc" and see the RP3A0
GPIO set to 1 and pulling the CC to 3.3V.
Change-Id: Ic2d8ed95ea21b21d261a12ba298931d8bd5e6919
Reviewed-on: https://chromium-review.googlesource.com/231150
Reviewed-by: Vic Yang <victoryang@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The latest gcc picked up a couple out-of-bounds issues, so
"make buildall" was failing. This fixes them.
BUG=none
BRANCH=ToT
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Idcd6a3358ecbb0e0d2a610e1cd28c2f138ce520b
Reviewed-on: https://chromium-review.googlesource.com/231156
Reviewed-by: Randall Spangler <rspangler@chromium.org>
For USB console, we wait for USB host to grab the data before writing
the next chunk of characters. However, if the USB peripheral is
disabled, the current implementation is confused as to whether the host
has grabbed the previous chunk of data.
Fix this by explicitly checking for USB peripheral enabled.
BRANCH=ryu
BUG=None
TEST=Boot on Ryu and check console isn't slow.
Signed-off-by: Vic Yang <victoryang@chromium.org>
Change-Id: I438c95835e56707b7ca1796734f2e47062799f44
Reviewed-on: https://chromium-review.googlesource.com/231115
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This is fairly large change set to accomodate a new hardware
release. There are enough differences to require refactoring the
registers.h file. Autogenerated constants are now in gc_regdefs.h
and all constant names begin with GC_, while register names are
defined in registers.h and begin with GR_.
Yes, I know the new header files are wider than 80 chars, but we
agreed that was okay in some cases if it makes them more readable
(see commit 3500c28).
BUG=chrome-os-partner:33423
BRANCH=none
TEST=make buildall -j
Build and run on the development board.
Change-Id: I21bd88c490f4f359ad17b5af9d17d8caca8dc9e4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/230513
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Add commands to send PD packets and to tweak individual parameters (TX
clock frequency, RX detection threshold, resistors on CCx).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:28337
TEST=verify that the PD sniffing is still working by dumping traffic
between Zinger and Samus.
Connect Twinkie to Zinger, set Rd by using "tw res NONE RD" and see VBUS
going to 5V (reading it using "ina 0").
Send a BIST mode 2 request using the following command :
tw send 2 0x1043 50000000
and see the other end starting sending BIST.
Change-Id: I3c8ddf858435ac1c17a43f59351bbaa69603a209
Reviewed-on: https://chromium-review.googlesource.com/227778
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Extend the Zinger runtime to take into account the disable_sleep()
issued by the USB protocol stack and avoid going into deep-sleep while
connected.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=connect Zinger to a PD power sink (Twinkie) and monitor the stop
mode entry/exit on a GPIO.
Change-Id: I04e35fdd65f3be3da7a4304dc1a92e6268930888
Reviewed-on: https://chromium-review.googlesource.com/230340
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Allow to use larger RSA keys by setting CONFIG_RSA_KEY_SIZE to 4096 or
8192 rather than using the default 2048-bit size.
It's mainly for benchmarking purpose right now as we don't have the RAM
to store the 3x key size buffer and the flash space for the public key
structure.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=samus
BUG=none
TEST=build Zinger with CONFIG_RSA_KEY_SIZE equals to 4096 and run it.
Change-Id: I9839121bf158d0a30dde1e48d875f345191bfec2
Reviewed-on: https://chromium-review.googlesource.com/228925
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
It's really annoying to have to type two different commands. If I
want to read a location and then write it and then read it back
(which often happens when poking at hardware), then this:
rw 0x40570008
rw 0x40570008 14
rw 0x40570008
is much easier to enter than this:
rw 0x40570008
ww 0x40570008 14
rw 0x40570008
The "ww" command is still there, if you're really attached to it.
BUG=none
BRANCH=none
TEST=manual
Tried the example above. It worked.
Change-Id: I2302ed60df3dd3ec2224afa7c32d997bd2468ec1
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229660
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Implement the API expected by common/timer.c
BUG=chrome-os-partner:33699
BRANCH=none
TEST=manual
Run the "gettime" and "timerinfo" and "taskinfo" and "waitms"
commands. Compare the elapsed time with the real world. They seem
to match.
Change-Id: Ie5acae76780ee09e7dfb6cc0282de25f8063e96f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/229642
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This enables forwarding of the local PD/EC console
over debug USB. It gates the console functionality
based on the CCD mode that is set.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable partial CCD mode on ryu and verify that it is
enumerated by the host correctly, but doesn't respond
to console input, and doesn't generate output.
Enable full CCD mode on ryu and verify that it is
enumerated and that the console works as expected.
Verify that the console still works by default on the
discovery-stm32f072 board.
Change-Id: I0325ce9689486c41387d6075330be1d7d42f1d42
Reviewed-on: https://chromium-review.googlesource.com/229342
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Previously enabling USB would automatically (using an
init hook) initialize the USB peripheral. This would
take over the GPIO lines assigned to the USB module.
This is not OK on Ryu for Case Closed Debug because it
interferes with the AP's access to the USB 2.0 lines
even when not in Case Close Debug mode.
This change adds a configuration option to inhibit this
default initialization of the USB peripheral. It also
renames the existing CONFIG_USB_INHIBIT to
CONFIG_USB_INHIBIT_CONNECT now that there are two
possible inhibitions.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable console on ryu_p2 and discovery-stm32f072 board
Verify that it works on both
Change-Id: I6734357131b4356e3d4164349d6c74deac196ce5
Reviewed-on: https://chromium-review.googlesource.com/229138
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Previously the usb driver used #ifs to select a mechanism to
enable and disable the DP pullup. This doesn't scale well,
especially when the knowledge of how to do this is not known
to the chip specific code, but instead is board specific (as
it is with the STM32F373).
This change uses the build systems ability to build chip family
specific files per build to select the appropriate behavior.
And on the STM32F3 family of parts it just calls out to a board
specific pair of connect/disconnect functions.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable console on ryu_p2 and discovery-stm32f072 board
Verify that it works on both
Change-Id: I976e02fbc7acbb0f85817d7295b26ee9ecab0711
Reviewed-on: https://chromium-review.googlesource.com/229040
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Previously the USB RAM size was off by a factor of two
for chips that required 32-bit alignment of accesses,
even though the underlying memory was 16-bits in size.
This change adds an additional configuration for the
access size (it still assumes that the underlying memory
is 16-bits in size) and uses that to adjust the USB_RAM
memory section in the linker scripts.
This change also removes the default values for the USB
RAM from stm32/config_chip.h because they mask issues
when new chips are added. It is better for a new chip
to fail to compile until these values are provided.
Finally, this change introduces a common USB API header
so that common code doesn't need to include the STM32
specific header.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable console on ryu_p2 and discovery-stm32f072 board
Verify that it works on both
Change-Id: Id118627f53e9e8ff1bd09fb51f1f9634ff495d19
Reviewed-on: https://chromium-review.googlesource.com/228833
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
The console code never worked with the old style STM32 USB
peripherals because no chips with that version of the peripheral
were being used. The STM32F373 uses the older USB peripheral.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable console on ryu_p2 and discovery-stm32f072 board
Verify that it works on both
Change-Id: I77d36c33712521d7840b4e3ca02ebbea5de3d5df
Reviewed-on: https://chromium-review.googlesource.com/227741
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Modules that are enabled are listed below:
- Power Sequencing
- Keyboard Scan and Protocol
- LPC to support Keyboard
- Power Button Task
ec.spi.bin has to be generated manualy using
pack_ec.py
BUG=None
BRANCH=None
TEST=Tested on Stargo-Proto board
Change-Id: Ic5d504c3d6e9c7c5f3482fb7e9e37800b6274824
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/226303
Reviewed-by: Vic Yang <victoryang@chromium.org>
The fans on samus have a recommended minimum duty cycle of 20%
while running, but 30% in order to start. We've been using the
EC's built-in fan controller for the start requirement, but it
has a minimum fast-start duty cycle of 50%. It turns out that
that speed is noticeably noisy.
This change handles the startup with logic in the EC instead, so
that the fan only tries to spin at 30% initially (or if it drops
too much below the minimum turning speed).
BUG=chrome-os-partner:33429
BRANCH=ToT,samus
TEST=make buildall -j
Boot the system, let it idle with the browser windows closed, the
browse a bit, then idle. Listen for changes to the fans.
Before, I could hear the fans kick in and out as the AP load
changed. Now it's much quieter.
Change-Id: Id35215520c064eb6843686ec8bb5f3618dac6cf6
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/227658
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Previously the version string was special cased in the USB stack
because the build system prevented the inclusion of ec_version.h in
any file other than common/version.c. This lead to common/version.c
being the only place that the USB version string could be computed
and thus the special case of filling in the version string descriptor
at run time. This made the USB stack more complex, and lead to the
common/version.c file including usb.h, which is actually STM32
specific.
Now, the portion of ec_version.h that is deterministic is only
updated when something in the tree actually changes (by way of a
conditional in the makefile), and ec_version.h no longer has to
depend on all object files (other than the special version.o).
This allows anyone to include ec_version.h as needed. In particular,
each board that wants to define a USB version string can directly
include ec_version.h and do so.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
touch files and verify rebuilds happen correctly
Change-Id: Ic84d0b9da90f82ebb4630fb550ec841071e25a49
Reviewed-on: https://chromium-review.googlesource.com/227211
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
The serial console works. Nothing else is implemented yet.
BUG=none
BRANCH=ToT
TEST=make buildall -j
To build,
make BOARD=cr50 hex
Testing the result requires a development board. I have one. It
works with HW revision m3.dist_20140918_094011
Change-Id: I718d93572d315d13e96ef6f296c3c2796e928e66
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226268
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Per table 6-24 of USB PD spec an alternate mode adapter (AMA) should
include both product & AMA VDOs.
BRANCH=samus
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,
Connect hoho/dingdong to fpie/samus and see product VDO proceed the
AMA VDO in DFP_U console output:
Product VDO -----------------------------v
|------|
SVDM/5 [1] ff008041 340018d1 00000000 50100001 1100000b
Note, hoho's PID == 0x5010
And dingdong (0x5011)
SVDM/5 [1] ff008041 340018d1 00000000 50110001 1100000b
Also see bcdDevice field in descriptor match above data.
$ lsusb -v -d 18d1: | egrep -i "idproduct|bcddev"
idProduct 0x5011
bcdDevice 0.01
Change-Id: I4d898816a45c68c7ff75a54fd348fc11be408ae0
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226125
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
USB Billboard class can be used to advertise an alternate mode capable
device that hasn't entered a mode. Additionally it can remain after
mode entry providing its Billboard capabilities descriptor is
updated.
This CL postpones enumeration which previously occurred after boot
until tAMETimeout has passed and alternate mode has NOT been entered.
Future CL could choose to also (re)enumerate with mode capabilities
although this is not required by the USB PD specification.
BRANCH=none
BUG=chrome-os-partner:31192,chrome-os-partner:31193
TEST=manual,
With DFP_U which does not enter mode see Billboard class enumerate
else it does not.
Change-Id: I59a0815cd0ea551ba9a878907c0184df4ba9480c
Signed-off-by: Todd Broch <tbroch@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224663
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Now that the problem with UART in STOP mode is fixed, let's enable low
power idle for Ryu P2 boards.
BRANCH=None
BUG=chrome-os-partner:33219
TEST=Shut down the AP and unplug AC power. Check the EC goes into
deep-sleep by 'idlestat'.
TEST=Power up the AP and check the EC stays awake.
Change-Id: Ib8ad3763407315ec0f95551fa0fdd258a060e113
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/226312
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
These names can be used to uniquely identify an interface
as being a console forwarded from the AP, or the EC's
console or some other console. This makes it possible to
connect to the correct console from servo without knowing
what board is attached. These strings could also be used
by udev rules to create appropriate symlinks.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I1abd36f952782a03606b09485917be8e154534ce
Reviewed-on: https://chromium-review.googlesource.com/225950
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
This uses the newly allocated simple serial SubClass
and Protocol identifiers to make enumeration of serial
consoles over USB easier. The simple usb serial kernel
driver can select based on vid/class/subclass/protocol,
making it trivial to attach to serial consoles.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable USB console on discovery-stm32f072 and verify
that a new ttyUSB? device is discovered.
Change-Id: I6d3e414a20753573c2ee90a48fb1d5dce2c3972d
Reviewed-on: https://chromium-review.googlesource.com/225869
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Previously the USB console code used two separate
bidirectional endpoints. Using the STM32 USB perihperals
endpoints in this manner means that there are only 8 total
endpoints available. But the STM32 USB peripheral allows
for a single endpoint number to be used for both IN and
OUT transactions, and while this (re-using an endpoint
number for both IN and OUT endpoints) appears to be not
compliant with the letter of the law with respect to the
USB spec, it is supported by USB stacks, and is used in a
number of USB devices.
So this change makes the USB console driver share a single
endpoint number between the IN and OUT bulk endpoints used
to implement the console.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable USB console on discovery board and manually test.
Change-Id: I511e56de2162a6c04ddba80d26b37b4f0cd993fd
Reviewed-on: https://chromium-review.googlesource.com/225868
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
When calling the ep_undefined function, the linker was not considering
it as a Thumb function and not setting the LSB in the address pointer.
This was causing an exception at runtime.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=all
BUG=none
TEST=inspect assembly
Change-Id: I8f4d1e351081032e138f593f0b61294031fc09b1
Reviewed-on: https://chromium-review.googlesource.com/226093
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=master
BUG=chrome-os-partner:29139
TEST=Buiid an EC FW image and run on Rambi to test if key loss is
improved and any side effect somes with this change. Need more test
units to confirm this.
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Change-Id: I2399e33d2ca3defe8cd9b1f94ab0af1db7f84635
Reviewed-on: https://chromium-review.googlesource.com/225557
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mohammed Habibulla <moch@chromium.org>
Previously the USB console code would wait for up to
30 ms for the USB packet buffer to become available
for transmission, even if it was called from an interrupt
context. This doesn't work because, even if we were OK
with waiting this long in interrupt contexts, which we are
not, we rightly assert that we are not in an interrupt
context in task_wait_event, which usleep calls.
This solution is a quick fix to only wait when not called
from within an interrupt context. The correct solution
is likely to decouple the printf code from directly calling
the console driver code, instead we should place a queue
between the driver and printf logic.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Enable USB console on discovery board and manually test.
Change-Id: I5b6f7bbb77f75132c75935f8fda01e652a236ae0
Reviewed-on: https://chromium-review.googlesource.com/225867
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
By default, UART wakes the chip up on RXNE interrupt. This means when
the chip wakes up, RDR is full and only the shift register is empty, and
this leaves us only the time of a single character to process the
character in RDR. On some system, this is not enough and the first (or
even the second) character is overrun, and thus any multi-character keys
(e.g. arrow keys) break.
To avoid this problem, let's change the wake source to wake on start bit
detection. This gives us the time for one more character to wake up and
process the console input.
BRANCH=None
BUG=chrome-os-partner:33219
TEST=Enable low power mode on Ryu P2. In STOP mode, hit up arrow key and
see the last command show up.
Change-Id: Idce4c0bdfcf3e04ad84152ba525f704a0909f115
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/225771
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@google.com>
Before entering STOP mode, we need to ensure UART Tx has completed.
Otherwise, we may lose some characters or some bits within a character.
For Tx DMA mode, this is already done as we wait until TC (Tx complete)
is set before disabling Tx. However, when not using DMA, we enable sleep
when TXE is set. At this moment, the last character is still in the
shift register and going into sleep causes loss of the whole or part of
the last character.
To avoid this, let's enable TC interrupt and enable sleep only if we
have no more characters to send and TC is set.
BRANCH=None
BUG=chrome-os-partner:33219
TEST=Enable low power mode on Ryu P2. Type when the EC is in STOP mode
and check there is no broken character.
Change-Id: Ife42671882b7f1d1d17734d7d20fb4ba7dffb371
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/225283
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This adds the option to use one 16-bit timer for watchdog helper when
using 32-bit hwtimer. With this, a debug message is dumped before
watchdog fires and we can easily see the task hogging the processor.
BRANCH=None
BUG=None
TEST=On Ryu P2, 'waitms 3000' and see debug message before the EC
reboots.
Change-Id: I498f63a105a0ba1ab7ec7d274dc8b1f16a44140f
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/225253
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This modifies the stray hard-coded DMA channel for UART Rx to the
correct config flag.
BRANCH=None
BUG=chrome-os-partner:32660
TEST=On Ryu, enable UART Rx DMA and check console is still responsive
Change-Id: Icec2de6ad4d34c6e0f8df2a1d51d9fefd982c9f4
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/225239
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On STM32F0, a single IRQ is used for all RTC events, including RTC_ALARM
and RTC_WAKEUP, and this IRQ is named RTC_WAKEUP. We use RTC_WAKEUP IRQ
in our code while we actually meant to capture RTC alarm event. On
STM32F3, RTC_WAKEUP and RTC_ALARM are separate IRQs and thus we're
having problem. Let's make it explicit which RTC IRQ we want to use and
fix our code to use RTC_ALARM.
BRANCH=None
BUG=chrome-os-partner:33219
TEST=Run 'rtc_alarm' on Ryu and verify the EC gets interrupted after a
second.
Change-Id: Ib1a14a5da49d709a4d071d44fbfa46544cc5929b
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/224998
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Simple control of SPI for flashing over USB.
This driver is working, and using the discovery board
with a W25Q16 flash chip attached flashrom can read,
erase, write, and verify the whole chip in 45 seconds.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I224f1f87cd6adc8b64c17de1df98dae0a9cfa6a5
Reviewed-on: https://chromium-review.googlesource.com/218740
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
