When compiled for Broxton, Buffers.Translations() is a stub and GCC 8
correctly identifies the use of unitialized fields. However, it can't
see that it's never called in that case. Draw the definition of
Program_Buffer_Translations() inside the respective `if` to make that
clear.
Change-Id: I8edbb8ac9249d76465d1cd07526fb6eeef0618e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26305
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Adrian-Ken Rueegsegger <ken@codelabs.ch>
On GMCH targets the Pipe index needs to be programmed in the output
register.
Change-Id: I6a614a9359c95adb59a1b6d0e34febe302fcfbf8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25410
Reviewed-by: Nico Huber <nico.h@gmx.de>
Always load i915 even if it wasn't loaded before. Also, force
`modeset=1` as that's our use case and we might have booted with
`i915.modeset=0`. Last but not least, search for the correct
vtcon* entry in sysfs instead of guessing, and always unbind it
(i.e. unbind the dummy driver when we want to switch back to
i915).
Change-Id: Ib62a05a3621aef2992372a6d3acad1196a363a95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22715
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As for the tiling, we enable support for rotated framebuffers on
platforms with Plane_Control. On every path where a rotated frame-
buffer may be expected, we have to exchange width and height in
case of 90 degree rotations. Beside the rotation setting itself,
the hardware needs to know the vertical stride instead of the hori-
zontal and a delicate page mapping in case of 90 degree rotations.
For that we divide the GTT space into two, the lower half contains
the linear mappings, the upper half mappings for a rotated scanout.
Change-Id: I1c901b7abc0fe7764bee87f6fda58ba9fa3f340d
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22711
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a Rotation setting to the Framebuffer type that tells us if the
framebuffer is rotated by 90, 180 or 270 degrees. The hardware should
rotate the picture in the opposite direction before display.
To support more complex memory layouts, we also add a V_Stride (ver-
tical stride) setting.
Change-Id: I6430fb44b5c9cfcf9fa58684a425e8c2e4647ac3
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/22710
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On platforms with Plane_Control registers (Broxton/Skylake+) we can
use X and Y tiled framebuffers for scanout (older platforms support
X tiling only). As our main use case is 90° rotation with Y tiled
framebuffers, we implement it for the newer platforms only for now.
We also set up a fence register for linear access to the tiled frame-
buffer through the aperture.
Change-Id: I913c82f62fd28b681a06ce13f41160a07e559799
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22709
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Through fence registers, we can tell the hardware which parts of the
aperture cover tiled framebuffers. Only legacy X and Y tiling is sup-
ported. According to `i915_reg.h` there are 16 fence registers from
G4x on and 32 from Ivy Bridge on (this only partially matches docu-
mentation: Haswell has 16 regs documented and the fence registers
were not documented at all before).
Change-Id: I02edc99b315e24dc175c6f93aff627e59cb1ff0b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/22708
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nico Huber <nico.h@gmx.de>
Beside linear framebuffers, we can, on Intel hardware, easily support X
and Y tiled framebuffers too. If we access the framebuffer through the
aperture window, we can let the hardware handle the tiling.
Tiling generally divides the framebuffer into rectangular pieces of
fixed size where each piece, or tile, is represented by one page of
memory. Even inside one tile, the pixels are not always ordered linearly
but either in a row-major (aka. X tiled) or column-major (aka. Y tiled)
manner.
Change-Id: I3e6f93caa8f2485a5792d72cfe2e8b3902add7a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/22707
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We only use DDI E for analog VGA outputs through the PCH DAC. DDI E
might be configured differently, though, by a previously running dri-
ver, so we have to treat the two entities seperately on the All_Off()
path.
Change-Id: I603ecd29c48af43bc21acaadbedaeae451acbcf3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20822
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
DDI E shares its two lanes with DDI A. If DDI A is configured to use
all four lanes, DDI E is disabled. As DDI E is the only DDI that can
be configured in FDI mode to feed the PCH DAC, treat `Analog` as in-
valid in this configuration.
Change-Id: I94e9537c9f30d0cbf757b816f38d44e1b43805b3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20821
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GFX Programmer's Reference Manuals (PRMs) aren't clear on this but
it's pretty clear from the processor datasheets which SKUs expose which
pins: All U/Y processors lack DDI D.
Change-Id: I84c40b6bc01091de8a512e21354243c74643e0f5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20820
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use GMA.Setup_Default_FB() to allocate framebuffers in the stolen
memory. To help with setups where we can't unload the i915 driver,
back up and restore the current GTT setup and framebuffer contents.
Also add a wrapper script and update the README.
Change-Id: I10790d35d38b7b211f41b2452f6d2baf17372e31
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20604
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Calling this is necessary for VGA text mode on at least Skylake, where
the legacy VGA registers are inaccessible otherwise.
Change-Id: I48ba1738bcc7babd4e666e5266f775dcd06b2a3f
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21323
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>
After reset DPLL_CTRL2 is initialized to 0. Which means some clock
disable bits are not set and might cause some hassle later. Set them
and close the related TODO.
Change-Id: I1a470dff55e317e8119906b3e397f6f2314abcbd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20648
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We initialize the timeout variable before the first event on the other
side (i.e. us sending a request to PCODE). With very slow debug output
sending the request itself might take longer than the timeout period.
Reorder the code to check the timeout condition only after the first
try and thereby make sure that we always try at least twice. Also issue
a debug message in case we timed out.
Change-Id: I8cdeb3e36d7eafbef8a1a8e13670f3f9838a2f38
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20647
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
First, allow updates to voltage swing too during channel equalization.
Spec just says to adjust the settings as requested.
Second, the loop conditions differ from the clock recovery phase. We
have only 6 tries in total but no particular order is enforced.
Change-Id: I4673390d8c0f9a5642702872e5b4ab11f54797c7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21215
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On DVI-I connectors the DDC is shared between the analog and digital
parts. To decide which path to take we checked the digital input bit
of the EDID. We did this overeagerly for all ports, which broke com-
patibility with DP adapters (the DP realm is very complex and we are
supposed to discover the whole downstream hierarchie, which obviously
would be overkill).
Change-Id: Ifc53e8ab985695e6e4ff1d42659826710a50eae9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20135
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new public procedure Setup_Default_FB() to configure a framebuffer
in stolen memory. The optional parameter `Clear` tells it to clear the
configured framebuffer.
Also remove Setup_Default_GTT() from the public interface.
Change-Id: I6ece4f56bbd34126ef34f0107d5ccdbde8a007ac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20603
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Honor the `Offset` field of the given framebuffer and add preconditions
that ensure we won't overflow the GTT or its target address space.
Change-Id: I6577e98e154610228734baee7674ee54b9a922e8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20602
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To be compatible with HW.PCI.Dev implementations that do actual register
accesses, we have to account for hardware state updates.
Change-Id: I86e42163d7847f7011bcf9a0ef5c2c7f25b4b1be
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21207
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Adrian-Ken Rueegsegger <ken@codelabs.ch>
Remove `MMIO_Base` option from Initialize() and try to derive it
using libhwbase' PCI mechanism instead.
Change-Id: Iacd4d098954bb96c1c6b40fdfb2636191d9517c7
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20600
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a configuration option to override the default HDMI translation.
It's not exported yet, as we've never seen a non-default value being
used. So this is just to have a common place for the defaults.
Also sets the recommended default value for Broxton as defined in the
PRM.
Change-Id: I59fae0fb4f444d9193a98b6a0edf337ecbba3b62
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20165
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This simple program scans all ports and configures pipes for the first
three available displays. It presumes that there is enough framebuffer
mapped for all pipes and fills it with test images.
The only command line parameter ist the path to a PCI-device node in
sysfs. On exit, the hardware is left in the configured state. So the
user has to make sure, that he either can work without the gfx hard-
ware or has another driver to restore a working state.
Change-Id: I2144300589e113e711db7959aa68fa96c3844568
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/18786
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Using the same type (Pos64) as in the actual calculation below, helps
current SPARK Pro to prove absence of overflows (SPARK GPL 2016 still
works too ofc).
Change-Id: Ifde556f9201f3333be0eb8566bf69b7f9df11277
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18809
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add new configuration flags for Broxton and hook up its DDI_Phy
implementation in the shared Haswell DDI code. Haswell and Skylake
get DDI_Phy stubs.
Tested (in Linux userspace) on ASRock J3455-ITX which exposes the
following ports:
o VGA through an active eDP to VGA converter chip
o HDMI 2.0 through an active DP to HDMI converter chip
o DVI-D connected to the SoC
Change-Id: If72b228c6a4c45487261e6e7435d281ec2d97f38
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18426
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Other than for the DDIs of the Core processor series, we don't select
signal levels from a preconfigured set but have to program the indivi-
dual values.
Change-Id: I3ab4d5e2ed47db0d4ce47a17c4a5fb08b5416bc2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18425
Tested-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
