There many TODOs sprinkled in the code, some of them have been
addressed or do not apply any mode. This patch removes them.
BRANCH=cr50
BUG=none
TEST=built and ran cr50 on reef
Change-Id: Ica6edb204e5cc0cc9dc7f0d43fd39e7ddaf56809
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/506496
Reviewed-by: Randall Spangler <rspangler@chromium.org>
hammer corresponds to poppy, and staff corresponds to soraka.
Current differences (hammer/staff):
- USB id (5022/502b)
- PWM frequency (10kHz/100Hz):
- On staff, driving PWM at 10kHz leads to an actual duty cycle
around 30-40%, with a PWM output at 1% (long rise/fall time).
100Hz looks better, we get ~1.45% duty with 1% PWM output.
BRANCH=none
BUG=b:38277869
TEST=Flash staff, boots fine.
TEST=pwm 0 1 shows quite dim backlight on staff.
Change-Id: I66ba2adf89fbee8578ee473afb28e3e242b4d111
Reviewed-on: https://chromium-review.googlesource.com/505855
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In a lab servo, flash_ec is executed without the board flag. In this
case, don't check the board flag for raiden and simply respect the
raiden flag.
BRANCH=none
BUG=b:38319398
TEST=Ran the flash_ec script in a lab servo.
Change-Id: Ib3757a4b7b550fd77facffdf2009cc3317591888
Reviewed-on: https://chromium-review.googlesource.com/506461
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
always_memset() implements a version of memset
that survives compiler optimization. This change
replaces instances of the (placeholder) call
dcrypto_memset() with always_memset().
Also add a couple of missing memsets and
fix related TODOs by replacing memset()
with always_memset().
BRANCH=none
BUG=none
TEST=TCG tests pass
Change-Id: I742393852ed5be9f74048eea7244af7be027dd0e
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/501368
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
We don't have an external pull-up on WP_L, so let's use an internal
one instead.
BRANCH=none
BUG=b:35582031
TEST=gpioget WP_L shows 1 as default value, servo can control
value, and when servo is not driving the pin, value goes back
to 1.
Change-Id: I75148cde9ab89c1dfb05f3182608894a3e1390fa
Reviewed-on: https://chromium-review.googlesource.com/502849
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In order to support write-protect mechanism for the internal flash
of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by
controlling the WP_L pin of internal flash. During ec initialization
or any utilities related to access status registers, we'll protect them
if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we
only can unlock write protection of internal flash by rebooting ec.
This CL also includes:
1. Add protect_range array of npcx7's internal flash (W25Q80) for
write-protect mechanism.
2. Add bypass of bit 7 of DEVCNT.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series. (Besides gru)
Build poppy board and upload FW to platform. No issues found.
Passed flash write-protect checking on npcx796f evb.
Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/501727
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When cr50 detects recovery button (not keyboard) combo:
recovery+power, volume-up+down+power, etc., it should
(ideally) hard-reset the EC.
This patch allows power-on reset in addition to reset-pin reset
to enter recovery mode when recovery button combo is pressed.
BUG=b:35585326
BRANCH=none
TEST=make buildall. Tested on Poppy.
Change-Id: I15aeef99d21ddc774441ead56fba56d459595cc9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/503573
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch adds code to control the power LED.
BUG=b:37646390
BRANCH=none
TEST=Verify LED turns green, red, amber, off. Verify LED turns green
or off when chipset is on or off, respectively.
Change-Id: I1d7940d9bb4414d97c541ead802efeb8f279533e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486947
Cr50 masks the recovery button signal on a proto board when the
power button is being pressed (b:37682117). This bug has to be
fixed for the recovery button to work.
BUG=b:37274183
BRANCH=none
TEST=make buildall
Change-Id: Ia413ffce84d67b6f24f983ccce8ae8277452ac2c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When (USB-)resuming from deep-sleep, ensure that we avoid switching back
and forth the selected USB PHY at boot, in order to avoid having a
short disconnection at resume.
To achieve this, allow the board configuration to select the PHY it is
really using with the CONFIG_USB_SELECT_PHY_DEFAULT configuration
variable, still keep the default USB_SEL_PHY1 as before.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual: build 'proto2' firmware with CONFIG_LOW_POWER_IDLE defined,
with the chip connected to the host on PHY A, make the host issue a USB
Suspend then resume and see no disconnection.
Change-Id: I7abd5e338e5c688c2dd486293f520049cdfd273b
Reviewed-on: https://chromium-review.googlesource.com/501947
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This firmware supports a board used to initialize firmware on new cr50
parts.
BUG=b:36910757
BRANCH=None
TEST=boots on scribe board, spi/usb/uart/i2c functionality works.
TEST=cr50 boots on reef, CCD EC+AP SPI/UARTS work
Change-Id: I48818225393a6fc0db0c30bc79ad9787de608361
Reviewed-on: https://chromium-review.googlesource.com/437627
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This change makes Fizz enable USB type-A ports on resume and disable
them on shutdown.
BUG=b:38226666
BRANCH=none
TEST=Boot Fizz off of USB flash drive on a USB-A port.
Change-Id: I7f22438271ffc080e950f5f300937d89706e08a4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481078
This patch adds a dedicated charge port. The number of such ports
is specified by CONFIG_DEDICATED_CHARGE_PORT_COUNT. It works as a
sink only. The total number of charge ports is represented by
CHARGE_PORT_COUNT.
BUG=chromium:721383
BRANCH=none
TEST=make buildall. Boot Fizz off of barrel jack.
Change-Id: Ibbb11f3e1c66e35b5abe190e49161eeaa2009994
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501468
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a new source policy to provide 3A if there is only one port used
as a source.
Also ensure that the load switch on VBUS when sourcing power is properly
configured to limit the current to 1.5A or 3.0A depending on the case.
BRANCH=none
BUG=b:35585396
BUG=b:35577509
TEST=On soraka (rev1), connect any USB device on port 0. On port 1
attach C-C cable to MacBook Pro. MacBook Pro charges at ~1.5A.
Disconnect USB device on port 0, MacBook Pro charges at 3A.
TEST=On soraka (rev1), connect USB key on port 0, see it enumerating,
plug another USB key on port 1, it enumerates too, and the device
on port 0 does NOT disconnect/re-enumerate.
TEST=Repeat 2 tests above, but starting with port 1.
Change-Id: I48e744c8edec89bc0a53b54c47f666ad53e47551
Reviewed-on: https://chromium-review.googlesource.com/481563
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
console_is_restricted() function exists only if
CONFIG_RESTRICTED_CONSOLE_COMMANDS is defined, and a stub if it doesn't.
so we can use CONFIG_LOW_POWER_IDLE without the former.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual: build 'proto2' board with CONFIG_LOW_POWER_IDLE defined.
Change-Id: I0c7fd201a1f07371aee2420eafd96ac62a5ae4ca
Reviewed-on: https://chromium-review.googlesource.com/500148
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
rev1 uses 604K pull-up on lid, 30.1K pull-down, 1% tolerance, so
we can just reuse rev0 detection interval. We can consider narrowing
the interval as rev1 should have tighter tolerance.
BRANCH=none
BUG=b:35582031
TEST=make BOARD=poppy; make BOARD=soraka
TEST=Soraka (rev1): Base is detected.
Change-Id: I7c3950a0b4c0bd0e1140e4a51447a3483cccc603
Reviewed-on: https://chromium-review.googlesource.com/500014
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the change, compiler won't use 64-bit division for
bd9995x_psys_charger_adc() function.
BRANCH=none
BUG=none
TEST=To replace "reg" variable and checking the return value
if it is expected for both "bd9995x_psys_charger_adc()" and
"bd9995x_amon_bmon_chg_adc()" functions.
Change-Id: Ifc461e5a54ce583ff59281ad13421c640ec9e21e
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/485083
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch declares recovery_buttons array, where each board
lists recovery buttons. Pressing those while the board reboots
makes the system enter recovery mode.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I1f204156efbd6d2a507d67ba90f75ce857b03559
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486944
power_button_x86.c and switch.c assume there is a lid switch. This
patch separate them so that a board with power button but with no
lid can be configured properly.
This patch also moves backlight control to the board directory
so that only the boards with a backlight turn it on/off when power
state changes.
BUG=none
BRANCH=none
TEST=boot fizz. make buildall.
Change-Id: If4070cdc4b1221fae68b35ec3497335d81f192fd
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/489602
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, when we jump from RO to RW, we forget our USB PD state.
To recover from this, we send a SOFT_RESET (resetting the counters...),
then either the USB PD partner is happy about it and we can continue,
or it will issue a HARD_RESET to recover from our mismatched vision of
the current connection (e.g wrong role) resulting in a reset of VBUS.
The following use-case is still problematic:
if the system is not write-protected (ie it does USB PD negotiation in
RO EC) and we have no battery (or fully drained-one) as buffer, when we
are connected to a PD power supply, if it issues the HARD_RESET
mentioned above, we are going to brown-out.
It's happening with power-supplies supporting DR_SWAP, the RO EC will
negotiate a power-contract (as a sink), then try to reverse data role
(from UFP to DFP) to identify the power-supply. We end-up being
Sink/DFP, then when we sysjump to RW, we reset roles and send the
SOFT_RESET as Sink/DFP, the power-supply identifies the incorrect data
role and issues the HARD_RESET browning us out.
As a workaround, now we never ask for the DR_SWAP in RO firmware and
stays Sink/UFP.
This is not affecting regular write-protected machines (which are not
doing USB PD in RO EC). For developers, we are no longer doing the
DR_SWAP in RO mode, this is mostly innocuous for a regular power-supply,
but this would break the docking use-case. Normally, we will do it as
soon as we have jumped to RW, so the dock should still work unless the
developer is using the machine with RO EC (eg EC development with
soft-sync disabled).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=reef
BUG=b:35648282
TEST=Boot Snappy without battery. Verify RO image doesn't swap
data roles and soft reset issued by RW image as SNK/UFP is
accepted by the HP adapter.
Change-Id: Id184f0d24a006cd46212d04ceae02f640f5bda65
Reviewed-on: https://chromium-review.googlesource.com/461142
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Sam Hurst <shurst@google.com>
On some boards, the boot key combinations do not make a lot of
sense, so we can just not process them and save a little bit
of code space.
BRANCH=none
BUG=b:37422577
TEST=Flash hammer
TEST=make newsizes shows we save 156 bytes in hammer RW.
Change-Id: Ic96d7ed1dbee10f44f8b08568ab70b2f20961842
Reviewed-on: https://chromium-review.googlesource.com/495968
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
On some boards, the special alt-volup-r/h combinations do not make
a lot of sense, so we can just not process them and save a little
bit of code space.
BRANCH=none
BUG=b:37422577
TEST=Flash hammer, alt-volup-r/h does not do anything special
TEST=make newsizes shows we save 124 bytes in hammer RW.
Change-Id: I92770fd6b8ff90780162a6b1de428a550bb44e9b
Reviewed-on: https://chromium-review.googlesource.com/495967
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The cros_ec_debugfs creates the `console_log` debugfs entry if EC
supports EC_CMD_CONSOLE_READ version 1. On device where i2c command
latency is critical, periodic console_read is impacting the timing of
commands.
BRANCH=none
BUG=b:37584134
TEST=on rose with CONFIG_CONSOLE_ENABLE_READ_V1 undefined, the kernel
should not create cros_tp/console_log.
Change-Id: I40d0b959ef36f2f410155fa30e01c8169032a3e9
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/494546
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Add new host command EC_CMD_RWSIG_ACTION for controlling rwsig task.
This allow us to make firmware stay at RO without toggling reset pin.
flashrom can use this host command and removed the need to use any
out-of-band pin to toggle the reset pin (and make RWSIG stay in RO).
BRANCH=none
BUG=b:37584134
TEST=on eve, `ectool --name=cros_tp rwsigaction abort` should prevent EC
from jumpping to RW after RWSIG check.
Change-Id: Ia435e4e3ea8ed612a1250d3bf755ca50e5db9d37
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/497787
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This CL added the support for the quasi-bidirectional buffer which has
an open-drain output and a low-impedance pull-up resistance on KSO pins.
The low-impedance pull-up is active when ec changes the output data
buffers from 0 to 1, thereby reducing the low-to-high transition time.
Add CONFIG_KEYBOARD_KSO_HIGH_DRIVE to enable/disable this feature for
npcx7 series ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
Change-Id: I138f0e433394816e1e5c58b5053580f202c1ac48
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/497189
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This CL added the support for additional 5 adc channels on npcx7 series
ec. The pin-mux functionality of adc channels was already introduced in
CL 481561.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
All 10 adc channels passed the test on npcx796f evb.
Change-Id: I2c7458958ff659fce78f265eefa160050dee7daf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/497526
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Since a04fc68e72 "usb_i2c: refactor into common", the code in
chip/stm32/usb_i2c.* is dead, let's remove it to avoid confusion.
BRANCH=none
BUG=b:35578857
TEST=On hammer, userspace application can still talk to trackpad.
Change-Id: Idd9cc1109c80f3949fa8c4e50f4fe2e267d5a7ae
Reviewed-on: https://chromium-review.googlesource.com/492768
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
First, improve debounce logic to only notify AP on base detection
change.
Then, handle side-band signals. For that purpose, base EC pulses
detection pin for 100 us to signal out of band USB wake (that
can be used to wake system from deep S3). We filter these, and
only consider a single ~100us during a debounce interval to be
a valid out-of-band signal.
BRANCH=none
BUG=b:35775062
TEST=Flash hammer and poppy, connect them together. Put poppy in
deep S3 (powerd_dbus_suspend), hammer can wake poppy on
key press.
TEST=Change hammer's board_usb_wake to send invalid pulses (too long,
too short, multiple pulses within 5ms), and see that all those
pulses are ignored.
TEST=Check that PP3300_DX_BASE is 0 when base is not connected,
and 1 when it is connected.
Change-Id: I20bf4151134099f52fe8fe0332524aa1ca5f7d63
Reviewed-on: https://chromium-review.googlesource.com/490130
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This CL added support for 8 i2c controllers and 11 i2c ports in
npcx7 series ec. we also added i2c-npcx5/7.c and moved the functions
related to chip family to them. (Such as i2c_port_to_controller(),
i2c_select_port() and so on.) Note the layout and bit position of i2c
registers which are accessed in these functions are irregular between
npcx5 and npcx7. We think abstracting them from i2c.c is easier to
maintain.
In this CL, we also modified the checking rule for I2C_PORT_COUNT in
task.h in order to prevent compiler error. So far, the ECs besides
stm32 only use TASK_EVENT_I2C_IDLE to wait for i2c hardware completes
its job. Put (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) checking rule
for all ECs seems not suitable.
It also includes
1. Remove useless NPCX_I2C_PUBIT macro function.
2. Remove useless NPCX_PWDWN_CTL_COUNT in registers.h.
3. Add CGC_OFFSET_I2C2 and CGC_I2C_MASK2 to power down the other 4 i2c
controllers of npcx7 ec.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found.
All 8 i2c controllers and 10 ports (npcx796f supports PSL.) passed
i2c stress tests on npcx796f evb.
Change-Id: I2b5076d21bcd0f8d17fd811cad2ff7bd200b112a
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/487541
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This mode had to be disabled for P1 because of leakages on PP3300_A
that affected the voltage levels on the CC lines. With EVT the leakage
issues have been resolved and now this feature can be enabled.
BUG=b:35648532
BRANCH=none
TEST=With lidopen attached sink only adapter to port 1. Then executed
'lidclose' via the EC console and verified that the port went into low
power mode as expected. In addition, without adapter connected,
verified that when in low power mode the EC console was not flooded
with low power messages.
Change-Id: I281497cc6fe251d48c4ea737c7b4242200d39421
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/496947
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
