Enable the mutable scancode sets for EVT boards and reassign the
existing F13 scancode to instead send the new 0[e0 58] 1[e0 07]
scancode instead.
BUG=b:36735408
BRANCH=none
TEST=manual testing on Eve EVT to ensure that the key that used
to send F13 now sends the new scancode. Also test on P1 to ensure
that the key still sends F13.
Change-Id: Ia134db7b069d5bf10c931ee7ce66dd1ea85d3544
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506718
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Add an option to allow the scancode sets to be mutable. The only
reason to use this is to allow a scancode to be changed at runtime,
for instance to support different keyboards in one image.
The side effect of this is the scancode sets are moved out of the
shared RO section.
BUG=b:36735408
BRANCH=none
TEST=make -j buildall
Change-Id: Iefb97691d1f295411d7b5db603d9214d41af49fd
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506717
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
First, libpayload expects the keyboard interface index to be 0.
Then, hid_iface_request needs to reply to USB_HID_DT_HID request
with the content of struct usb_hid_descriptor. With current code,
the variable name is generated (and therefore hard to guess), so
we create a new set of macros so that we can use a specific
variable name.
Also, add support for HID Get_Protocol and Set_Protocol, as they
are compulsory for devices supporting boot protocol, even though
those are mostly no-op for now.
Finally, add a note regarding USB HID keyboard boot protocol, to
make sure that we do not accidentally change the report format.
BRANCH=none
BUG=b:36538963
TEST=Keyboard works in FW screen, both trackpad and keyboard
still work when AP has booted.
TEST=hammer/staff can still be updated (both RO from RW, and RW
from RO)
Change-Id: Ibea4888385909c9ce3b430464e5805c039d4b9ed
Reviewed-on: https://chromium-review.googlesource.com/505796
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This applies the simple rule: Charging port led is on, other
is off. When charging, LED is amber, otherwise it's white.
Open questions:
- Do we want blinking on low battery? On which side(s)? In
which AP states?
- No blinking in S3? That's ok?
- Need to add led blinking support for special debug mode
- Recovery mode blinking does not work as LED is powered from
a rail that is not on when AP is in S5.
BRANCH=none
BUG=b:37970194
TEST=Charge from one side, led is first amber, then white when
battery is full. Switch side, led behaves the same way.
Change-Id: I0531d72cd621148c0d0cce57a32b7310792d9936
Reviewed-on: https://chromium-review.googlesource.com/497372
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add the evaluation board driver of npcx7 series ec for testing. If you
received the evb which ec is 128-pins package, please notice it has
the following limitations.
a. No GPIOD7/E0 pins.
b. No I2C4_0, I2C4_1, I2C5_1 and I2C6_1 ports.
c. No ADC7, ADC8 and ADC9 channels.
d. No JTAG port 1.
e. Do not enable CONFIG_HIBERNATE_PSL since no PSL circuit on evb.
This CL also includes:
1. Modified reset config from srst to sysresetreq in openocd/npcx.cfg.
Make sure openocd driver can reset ec by using NVIC_SYSRESETREQ.
2. Add flash utilities for npcx7 ec in openocd/npcx_cmds.tcl.
3. Add npcx7_evb support in flash_ec.
BRANCH=none
BUG=none
TEST=Passed all npcx7 drivers verification on the evb no matter which
ec's package is 128 or 144 pins package.
Change-Id: I8224d97cd66ce483d70816f47b2e124308f1b69c
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/505832
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Some chip supports two owned slave address. The second slave address is
used for other purpose such as board specific i2c commands. This option
can be set if user of the second slave address requires larger host
packet er size.
BRANCH=none
BUG=b:37187312
TEST=`make BOARD=rose -j`
Change-Id: I8d0b04bf4dded55e3957c7b25d849663299593e5
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/472288
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
This patch clones I2C slave and hostcmd driver from stm32f0.
This patch contains contribution from Wei-Ning Huang <wnhuang@chromium.org>
for fixing i2c slave transmitter (CL:471726).
BUG=chromium:688979
TEST=build and load on dev board, run i2cget/set on host and check
return value.
BRANCH=none
Change-Id: I3d159d5bdd4bda6c229cf6d275ab4982836628dc
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/461037
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
dabc580d7e "poppy: Add ARC++ sensor support." accidentally moved pin
from gpio 36 to 30. When updating gpio.inc for rev1, I accidentally
thought the pinout had been changed. Let's fix this.
BRANCH=none
BUG=none
TEST=Boot on poppy and soraka
Change-Id: I6f44acdcfa7bc8f21144b26887eda503a350a6b0
Reviewed-on: https://chromium-review.googlesource.com/497232
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
When AP boots and FW screen is shown (e.g. in developer mode),
AP FW is querying MKBP status in a loop, leading to a lot of "+"
being printed in the EC console.
To avoid this issue, let's print "(++)" after a command is received
5 times in a row.
BRANCH=none
BUG=b:37925684
TEST=Set GBB flags to 0x4a38, reasonable number of "+" is printed
on EC console on boot, which firmware screen is being shown.
Change-Id: I8368c558b97e7a2513b979322bd4bba442626b27
Reviewed-on: https://chromium-review.googlesource.com/505948
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
At init time, read resolution/dpi from trackpad, and check that
logical/physical dimensions match the expected values, provided
at build-time.
BRANCH=none
BUG=b:38277869
TEST=Flash staff, no error message at boot time. Flash hammer image
onto staff, a warning is shown at boot time.
Change-Id: I5ef7d25b6e6525c2bd6fc023f58f3a242134d962
Reviewed-on: https://chromium-review.googlesource.com/505857
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In principle, trackpad dimensions (logical and physical), can be
probed from the trackpad at runtime, but this would slow down setup
time, as we need to wait for the trackpad to be initialized to read
those. Also, we do not have a framework to generate HID report
at runtime, and a new base with new trackpad would probably require
a new overlay anyway.
Also, set appropriate (temporary) values for both hammer and staff.
BRANCH=none
BUG=b:38277869
TEST=Connect hammer/staff to host, correct logical dimensions are
shown in evtest, and resolution is always 32.
Change-Id: I39b84274d71ca2f4e285f3324c0841331aae9bc1
Reviewed-on: https://chromium-review.googlesource.com/505856
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Fizz has two power sources: barrel jack and type-c port. It
selects a power source at boot and does not dynamicall switch
to the other ports after that.
Fizz initializes all power suppliers of all ports to zero then
initialize the source supplier (barrel jack or type-c port).
When both sources are provided, it prefers a barrel jack. This
detection is done by reading the voltage on PPVAR_PWR_IN.
If barrel jack is detected as a sink, type-c port works as a
source only. If type-c port is detected as a sink, type-c
port works as a sink only.
Fizz does not have a battery. So, battery module is removed.
BUG=b:37573548,b:37316498
BRANCH=none
TEST=Boot on both type-c & barrel jack.
Change-Id: If4f5ff0c6019d06ac9dacb5dd365f5aa96bffef3
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/499547
Add the new scan codes for the updated keyboard matrix:
R0,C3 = Search (in addition to existing location at R1,C0)
R0,C5 = New key using code 0[e0 58] and 1[e0 07]
There are no changes to existing scan codes.
BUG=b:36735408
BRANCH=none
TEST=make -j buildall
Change-Id: Ieba22eacd21a5c2dde3c7c43eb62b767fc0db42e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/506716
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
The assert in the charge state machine when there is no battery and no AC
is causing a lot of headaches during development, and I don't believe it
adds any value to panic the EC like this as it prevents the system from
coming up and any debug from happening. This is especially bad with H1
locking out any useful debug by preventing flashing the EC.
On Eve EVT we have some 'bad' batteries that are not correctly asserting
presence pin, and when powering with adapter this this check happens before
AC_PRESENT asserts because the USB PD negotiation is still happening so the
EC gets stuck in a reboot loop.
Similarly we had issues with the Krill board in the Whale BFT station that
was triggering the same assert.
In both cases there is an underlying hardware issue which is being
investigated separately, but it is impossible to debug these systems
because the EC will not come up.
With this assert removed the EC and AP can boot and the LED blinks red to
indicate there is battery a problem and the OS also reports a problem that
the battery cannot be found, and we are able to do further debug without
having to open the case. Additionally the error message is printed every
~second and it is very obvious from the EC console that there is a problem.
Similar issues were reported at various points on Glados, Chell, Kevin,
Elm, and Reef.
BUG=b:35563537
BRANCH=none
TEST=successfully boot and debug a failing Eve system
Change-Id: I002b26d54428d29192a7097f1aae18f3223c5707
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/477733
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Cr50 holds the EC in reset when it wants to flash the EC or AP. This
will trigger a pulse on the tpm reset signal. In early Cr50 versions
when the tpm was reset we would reboot cr50, so we added some code to
prevent cr50 from resetting itself when the update was going on.
sys_rst_asserted would check if there was an update going on and ignore
the signal if update in progress was true. At the end of the update the
deferred function was used to reset Cr50 after the update was complete.
None of this is needed anymore. We can just release the EC from reset at
the end of the update. This change removes usb_spi_update_in_progress
and the deferred update_finished.
BUG=b:35571516
BRANCH=none
TEST=flash the bob ec and ap using ccd.
Change-Id: I79416dba178c06bbc7289ad96968ee4e61947c4c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/506571
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
There many TODOs sprinkled in the code, some of them have been
addressed or do not apply any mode. This patch removes them.
BRANCH=cr50
BUG=none
TEST=built and ran cr50 on reef
Change-Id: Ica6edb204e5cc0cc9dc7f0d43fd39e7ddaf56809
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/506496
Reviewed-by: Randall Spangler <rspangler@chromium.org>
hammer corresponds to poppy, and staff corresponds to soraka.
Current differences (hammer/staff):
- USB id (5022/502b)
- PWM frequency (10kHz/100Hz):
- On staff, driving PWM at 10kHz leads to an actual duty cycle
around 30-40%, with a PWM output at 1% (long rise/fall time).
100Hz looks better, we get ~1.45% duty with 1% PWM output.
BRANCH=none
BUG=b:38277869
TEST=Flash staff, boots fine.
TEST=pwm 0 1 shows quite dim backlight on staff.
Change-Id: I66ba2adf89fbee8578ee473afb28e3e242b4d111
Reviewed-on: https://chromium-review.googlesource.com/505855
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In a lab servo, flash_ec is executed without the board flag. In this
case, don't check the board flag for raiden and simply respect the
raiden flag.
BRANCH=none
BUG=b:38319398
TEST=Ran the flash_ec script in a lab servo.
Change-Id: Ib3757a4b7b550fd77facffdf2009cc3317591888
Reviewed-on: https://chromium-review.googlesource.com/506461
Commit-Ready: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
always_memset() implements a version of memset
that survives compiler optimization. This change
replaces instances of the (placeholder) call
dcrypto_memset() with always_memset().
Also add a couple of missing memsets and
fix related TODOs by replacing memset()
with always_memset().
BRANCH=none
BUG=none
TEST=TCG tests pass
Change-Id: I742393852ed5be9f74048eea7244af7be027dd0e
Signed-off-by: nagendra modadugu <ngm@google.com>
Reviewed-on: https://chromium-review.googlesource.com/501368
Commit-Ready: Nagendra Modadugu <ngm@google.com>
Tested-by: Nagendra Modadugu <ngm@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
We don't have an external pull-up on WP_L, so let's use an internal
one instead.
BRANCH=none
BUG=b:35582031
TEST=gpioget WP_L shows 1 as default value, servo can control
value, and when servo is not driving the pin, value goes back
to 1.
Change-Id: I75148cde9ab89c1dfb05f3182608894a3e1390fa
Reviewed-on: https://chromium-review.googlesource.com/502849
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
In order to support write-protect mechanism for the internal flash
of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by
controlling the WP_L pin of internal flash. During ec initialization
or any utilities related to access status registers, we'll protect them
if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we
only can unlock write protection of internal flash by rebooting ec.
This CL also includes:
1. Add protect_range array of npcx7's internal flash (W25Q80) for
write-protect mechanism.
2. Add bypass of bit 7 of DEVCNT.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series. (Besides gru)
Build poppy board and upload FW to platform. No issues found.
Passed flash write-protect checking on npcx796f evb.
Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/501727
Reviewed-by: Randall Spangler <rspangler@chromium.org>
When cr50 detects recovery button (not keyboard) combo:
recovery+power, volume-up+down+power, etc., it should
(ideally) hard-reset the EC.
This patch allows power-on reset in addition to reset-pin reset
to enter recovery mode when recovery button combo is pressed.
BUG=b:35585326
BRANCH=none
TEST=make buildall. Tested on Poppy.
Change-Id: I15aeef99d21ddc774441ead56fba56d459595cc9
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/503573
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch adds code to control the power LED.
BUG=b:37646390
BRANCH=none
TEST=Verify LED turns green, red, amber, off. Verify LED turns green
or off when chipset is on or off, respectively.
Change-Id: I1d7940d9bb4414d97c541ead802efeb8f279533e
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486947
Cr50 masks the recovery button signal on a proto board when the
power button is being pressed (b:37682117). This bug has to be
fixed for the recovery button to work.
BUG=b:37274183
BRANCH=none
TEST=make buildall
Change-Id: Ia413ffce84d67b6f24f983ccce8ae8277452ac2c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/494069
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
When (USB-)resuming from deep-sleep, ensure that we avoid switching back
and forth the selected USB PHY at boot, in order to avoid having a
short disconnection at resume.
To achieve this, allow the board configuration to select the PHY it is
really using with the CONFIG_USB_SELECT_PHY_DEFAULT configuration
variable, still keep the default USB_SEL_PHY1 as before.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual: build 'proto2' firmware with CONFIG_LOW_POWER_IDLE defined,
with the chip connected to the host on PHY A, make the host issue a USB
Suspend then resume and see no disconnection.
Change-Id: I7abd5e338e5c688c2dd486293f520049cdfd273b
Reviewed-on: https://chromium-review.googlesource.com/501947
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This firmware supports a board used to initialize firmware on new cr50
parts.
BUG=b:36910757
BRANCH=None
TEST=boots on scribe board, spi/usb/uart/i2c functionality works.
TEST=cr50 boots on reef, CCD EC+AP SPI/UARTS work
Change-Id: I48818225393a6fc0db0c30bc79ad9787de608361
Reviewed-on: https://chromium-review.googlesource.com/437627
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
This change makes Fizz enable USB type-A ports on resume and disable
them on shutdown.
BUG=b:38226666
BRANCH=none
TEST=Boot Fizz off of USB flash drive on a USB-A port.
Change-Id: I7f22438271ffc080e950f5f300937d89706e08a4
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/481078
This patch adds a dedicated charge port. The number of such ports
is specified by CONFIG_DEDICATED_CHARGE_PORT_COUNT. It works as a
sink only. The total number of charge ports is represented by
CHARGE_PORT_COUNT.
BUG=chromium:721383
BRANCH=none
TEST=make buildall. Boot Fizz off of barrel jack.
Change-Id: Ibbb11f3e1c66e35b5abe190e49161eeaa2009994
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/501468
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a new source policy to provide 3A if there is only one port used
as a source.
Also ensure that the load switch on VBUS when sourcing power is properly
configured to limit the current to 1.5A or 3.0A depending on the case.
BRANCH=none
BUG=b:35585396
BUG=b:35577509
TEST=On soraka (rev1), connect any USB device on port 0. On port 1
attach C-C cable to MacBook Pro. MacBook Pro charges at ~1.5A.
Disconnect USB device on port 0, MacBook Pro charges at 3A.
TEST=On soraka (rev1), connect USB key on port 0, see it enumerating,
plug another USB key on port 1, it enumerates too, and the device
on port 0 does NOT disconnect/re-enumerate.
TEST=Repeat 2 tests above, but starting with port 1.
Change-Id: I48e744c8edec89bc0a53b54c47f666ad53e47551
Reviewed-on: https://chromium-review.googlesource.com/481563
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
console_is_restricted() function exists only if
CONFIG_RESTRICTED_CONSOLE_COMMANDS is defined, and a stub if it doesn't.
so we can use CONFIG_LOW_POWER_IDLE without the former.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:38160821
TEST=manual: build 'proto2' board with CONFIG_LOW_POWER_IDLE defined.
Change-Id: I0c7fd201a1f07371aee2420eafd96ac62a5ae4ca
Reviewed-on: https://chromium-review.googlesource.com/500148
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
rev1 uses 604K pull-up on lid, 30.1K pull-down, 1% tolerance, so
we can just reuse rev0 detection interval. We can consider narrowing
the interval as rev1 should have tighter tolerance.
BRANCH=none
BUG=b:35582031
TEST=make BOARD=poppy; make BOARD=soraka
TEST=Soraka (rev1): Base is detected.
Change-Id: I7c3950a0b4c0bd0e1140e4a51447a3483cccc603
Reviewed-on: https://chromium-review.googlesource.com/500014
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This CL implements two methods for hibernating on npcx7 ec. One is using
PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The
other is turning off the power of all ram blocks except the last code
ram block. In order to make sure hibernate utilities are located in the
last code ram block and work properly, we introduce a new section called
'after_init' in ec.lds.S.
We also moved the hibernate utilities, workarounds for sysjump and so on
which are related to chip family into system-npcx5/7.c. It should be
easier to maintain.
It also includes:
1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for
hibernating.
2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of
wake-up inputs during hibernating.
3. Add DEVICE_ID for npcx796f.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series.
Build poppy board and upload FW to platform. No issues found. Make
sure AC_PRESENT and POWER_BUTTON_L can wake up system from
hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is
enabled or not on npcx796f evb.
Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/493006
Reviewed-by: Randall Spangler <rspangler@chromium.org>
With the change, compiler won't use 64-bit division for
bd9995x_psys_charger_adc() function.
BRANCH=none
BUG=none
TEST=To replace "reg" variable and checking the return value
if it is expected for both "bd9995x_psys_charger_adc()" and
"bd9995x_amon_bmon_chg_adc()" functions.
Change-Id: Ifc461e5a54ce583ff59281ad13421c640ec9e21e
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/485083
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This patch declares recovery_buttons array, where each board
lists recovery buttons. Pressing those while the board reboots
makes the system enter recovery mode.
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I1f204156efbd6d2a507d67ba90f75ce857b03559
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/486944
power_button_x86.c and switch.c assume there is a lid switch. This
patch separate them so that a board with power button but with no
lid can be configured properly.
This patch also moves backlight control to the board directory
so that only the boards with a backlight turn it on/off when power
state changes.
BUG=none
BRANCH=none
TEST=boot fizz. make buildall.
Change-Id: If4070cdc4b1221fae68b35ec3497335d81f192fd
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/489602
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
