This fixes an off-by-one error that was preventing two keys
(left and right arrow) on output 12 from being driven properly,
and causing some other weird ghosting effects.
BUG=chrome-os-partner:9516
TEST=Tested on Daisy
Pressing the right arrow shows this at the EC console:
[1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 40]
and pressing the left arrow shows this at the EC console:
[1 keys pressed: -- -- -- -- -- -- -- -- -- -- -- -- 80]
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ib7af21444c2d03a0787fb1a28b520a779013774d
Instead of making the STOP command synchronous, we can just have the
host-side app tell the EC to stop, then poll until it has.
BUG=chrome-os-partner:9349
TEST=manual
"make BOARD=link", then
copy build/link/util/lbplay to the host and run it.
Change-Id: I846924ae7994a498e0089197785cf239898fe2a3
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
This is referenced by various files, so should be in the gpio.h header.
BUG=none
TEST=manual:
build and boot on daisy, see that USB download still works
build on all platforms
Change-Id: If579c975ef6c82988b9e411eeaa97c950d9efce4
Signed-off-by: Simon Glass <sjg@chromium.org>
This just adds a single byte to the end of the RW firmware, so that we can
scan backwards from the end of the reserved block, skipping 0xff until we
find the actual firmware size. We need this so we can resign existing
firmware images without either signing a bunch of padding or forgetting to
sign a trailing 0xff that might be important.
BUG=chrome-os-partner:7459
TEST=none
Change-Id: If5cadb4d58c1bce39f66815c328ffd18cc3d444b
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
In case ctl decides to put it on a separate GPIO, he'll use PC7. If
he doesn't, we can reclaim this GPIO.
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7576
TEST=gpioget; signals should be present. PCH_SRTCRSTn should be 1.
Change-Id: I4ca4437515d62c36d00fd28093ca41e806ce351a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:9447
TEST=update from old EC 517 to this one
Change-Id: I275b5bf6c4ae1ab6e0c0a05cf9260314d644c79b
Signed-off-by: Randall Spangler <rspangler@chromium.org>
BUG=chrome-os-partner:7576
TEST=gpioget; signals should be present. PCH_RTCRSTn should be 1.
Change-Id: Ibdfbf555c0bb919a1a459308b5d832b50df2ffe3
Mostly stolen from Daisy.
Notable differences:
- No SYSCFGEN required for external interrupts ?
- No GPIO H bank on STM32F100, OSC_IN and OSC_OUT are not available
--> CODEC_INT and ENTERING_RW signals are missing
BUG=None
TEST=Tested on ADV2/Snow, able to see EC serialconsole
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I955e2ff180d064294d67b630ae2ee6cfcfe52ab9
0b00 for bits 1:0 (system clock switch) indicates HSI, 0b01
indicates HSE. Also, bit 23 is reserved (maybe it was just
a copying error from earlier).
BUG=None
TEST=Compiled and run on Snow
Change-Id: Ie6891492ae6e7e3bd30e4d7b183b156de1290fe0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
These GPIOs should have been removed in fd5d6c.
BUG=Yes.
TEST=built a new image and booted Daisy-EVT1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Idce4384cdbe548c2e4fe2be8b52e4275445c9f1b
This just reserves room. It doesn't actually perform any verification yet.
BUG=chrome-os-partner:7459
TEST=manual
make BOARD=link
dump_fmap build/link/ec.bin
Change-Id: I424db1d601a614be3dfe5abb200e24e8bc62e47e
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Add a Jim procedure to program the Link EC image from the default
location as generated by 'emerge-link chromeos-ec'.
BUG=none
TEST=manual
. emerge-link chromeos-ec
. start openocd as described in the Link care and feeding document
. in the port 4444 terminal session type
flash_emerged_link
. observe it succeed
Change-Id: Ibfbc38060d7e82ec8c83a73e2ccadff81d633ae4
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Rework to call functions in flash_common.c.
Also fixed a bug in parsing size of parse_offset_size().
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
BUG=chrome-os-partner:8448
TEST=on link
(CONSOLE) flashwp set 0x3d000 0x1000
(CONSOLE) flashwp lock
(HOST) flashrom -p internal:bus=lpc --wp-status
WP: write protect is enabled
WP: write protect range: start=0x0003d000, len=0x00001000
Change-Id: I4a53735c851ebf4bb0c01a55a1d301d5b706ee0c
GPIO_KB_PWR_ON and GPIO_PMIC_PWRON are active low, so add _L to each
name to make this clearer.
BUG=chrome-os-partner:9424
TEST=very ad-hoc:
1. build and boot on daisy, flash U-Boot with USB using
'cros_bundle_firmware -w usb', inserting daisy
USB cable when it says 'Reseting board via servo...'
2. Press cold reset, then power on, see that it powers on
3. Then hold power-on for 8 seconds and see that it power off
4. XPSHOLD function not tested yet
Change-Id: Ibdc0064477c36e8658ef5605cdd5811c2283aff9
Signed-off-by: Simon Glass <sjg@chromium.org>
Add this to the GPIO API. It seems that the implementation is copied
in LM4 and STM32 so I have reluctantly done the same with this new
function.
BUG=chrome-os-partner:9424
TEST=build and boot on Daisy
Change-Id: Ifddc52e69b2b33af2645384c0171dd264e588fcd
Signed-off-by: Simon Glass <sjg@chromium.org>
The changes in the message protocol break SPI support, so re-introduce
these, this time in the driver itself.
We add the concept of an option preamble in the message, a length and a
trailing byte.
BUG=chrome-os-partner:9426
TEST=run U-Boot, see that keyboard works correctly now.
Change-Id: I83b4af7e3745b935ffafcd9e2f521fce77e3bc6e
Signed-off-by: Simon Glass <sjg@chromium.org>
The position of jump_tags was shifted every time a new field was added
to struct jump_data. This broke the sysjump hook badly.
To make this more scalable, add a header_size field in struct jump_data.
Then the new code can always prepend (or reduce if jump_data becomes smaller)
some spaces between jump_data and jump_tags.
BUG=chrome-os-partner:9447
TEST=EC upgrade from EC 517 (2231) to this version, and keyboard keeps working.
Note that EC 526 (2235) to this version is not working because we have no way
to identify that header version change.
Change-Id: If1b506c6f7d22e5affaaf8ada15990f60d2f957a
Signed-off-by: Rong Chang <rongchang@chromium.org>
BUG=chrome-os-partner:8982
TEST=manual
run console command 'charger'
charger option will be displayed in bin and hex output
Change-Id: I461bce347f13eeb4f2c8595b83a7ba4c7d40ea58
We need to assert PROCHOT signal at/before 68 degree-C. Let's assert it
when CPU is at 68 degree-C. Also, we lower fan speed control threshold
to max fan speed at 65 degree-C.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:8982
TEST=none
Change-Id: Iec0d05308b1310f89bc0a2edb1ad632c8ca96c87
The address of charger temperature sensor and memory temperature sensor
are interchanged. Fix this in this CL.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:9450
TEST=Manual
Change-Id: I20ae4d39ef13992ca7cac32bb2e6be12e195731e
Rather than open code this each time, create a function for this. The
wrap-around condition may not be needed, if the timer starts at zero,
since we have 64 bits to play with.
BUG=chrome-os-partner:9424
TEST=build and boot on daisy
Change-Id: I84ae651212769b5927c452bc03f31f60a25a829e
Signed-off-by: Simon Glass <sjg@chromium.org>
We no longer support ADV EVT0 board and Discovery reference design.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=daisy && make BOARD=link
Change-Id: I7eb81e5271c070b17f018ac9c14491f1804c0e08
This modifies the existing daisy's board.c to use the new pin mapping.
BUG=None
TEST=Tested on Daisy-EVT1
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I717ce78df1ed29843d1498e979956c6ffdb05e80
this fixes the build breakage on stm32-based platforms.
In the linker script, remove the ASSERT since this macro is not designed
to work in that context and this size condition is already verified by
the linker by setting the "length" of the "FLASH" memory region.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=link && make BOARD=daisy
boot on Link and Daisy
Change-Id: I08964749d44f47caa0a359bc93c303a9611e5d73
Add STM32F support.
Based on David's changelist.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9057
TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery
Change-Id: Ide817d11480f0b56f67deaae3c08bc631f605075
Add a parameter to define the chip variant and pass it to build/make
processes.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9057
TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery
Change-Id: I87b65b582ed5fc2cf5966446e15224ac15e328e9
just rename STM32L to STM32.
Most of the STM32L15x code is common with STM32F1xx.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=chrome-os-partner:9057
TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery
Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
power related GPIO has been renamed, update the board definitions.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=None
TEST=make BOARD=adv
Change-Id: I2f0e1e9e93af22c1a6f64f354336bf0c30e9c5cd
This is very basic, so you can only rely on RO_SECTION, RW_SECTION_A, and
RW_SECTION_B for now. We'll fill in more regions as we add vboot stuff.
Still, you should be able to do things like this:
flashrom -p internal:bus=lpc -r ec.bin
flashrom -p internal:bus=lpc -w ec.bin -i RW_SECTION:ec.B.flat
BUG=chrome-os-partner:8198
TEST=manual
Build the image, look for the FMAP in it.
cd src/platform/ec
make BOARD=link
dump_fmap ./build/link/ec.bin
Change-Id: I0adbbfb8e975faae805bda271873fcef46590cf4
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
When the host reboots the EC it should be able to request the EC to
force recovery mode after reset. This is achieved by extending the
REBOOT EC command with a bitmask byte, with bit 0 dedicated to
recovery request.
So, when BIOS on the way up determines that recovery is requested, but
the EC is not running from the RO space, the BIOS would reset the EC
forcing it to run from RO and to request recovery mode through the LPC
bitmask. Then BIOS will restart itself ensuring that the system comes
up in consistent state.
Some refactoring was also done to make the code a bit more compact.
BUG=chrome-os-partner:9040
TEST=manual
. tested along with coreboot changes (test described in the coerboot CL).
Change-Id: I29801b6aec80da0901ba0e8db8e92e615cc778bd
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
LM4 reports fan stalled when fan speed is set to 0. Need to check this
before issuing warning.
Signed-off-by: Vic Yang <victoryang@chromium.org>
BUG=chrome-os-partner:7497
TEST=Did not see fan stall warning when fan speed is 0.
Change-Id: I8eecca8516b5442d4943d9195d04acc5b4041085
