There might be more than one place that will use very similar codes in
CL:542716 (usb_i2c.c). To avoid unnecessary duplication of code, we fold
the logic into i2c_xfer(). With config enabled (illustrated in this CL),
i2c_xfer() will support large reading. An early prototype of potential
usage is demostrated in CL:781300.
BRANCH=none
TEST=For CONFIG_I2C_XFER_LARGE_READ:
With proprietary software on slave: ./touchpad_updater -d
TEST=For usb_i2c regression:
./touchpad_updater still works (where the reading is less than 255)
TEST=For generic EC regression test:
On poppy EC (With CONFIG_I2C_XFER_LARGE_READ defined)
(1) Prevent override of update
/usr/share/vboot/bin/set_gbb_flags.sh 0xa39
(2) flashrom -p ec -w ec_binary_contains_this_CL.bin
(3) ectool reboot_ec cold
(4) "ectool version" verified that both RO/RW/Build info is local.
(5) Test with a type-C DP dongle on DELL 2408WFP.
(6) Plug-in type-C charger and external display still works.
(7) Confirmed that battery is charging.
(7) "ectool battery" reads same data (for fixed field) as before.
(8) "ectool usbpdpower", confirmed charger info displayed as before.
(9) "ectool usbpd 0", confirmed content exactly as before.
(10) For Gyro. Verify under Arc++
Using App: com.gamma.bubblelevel, works the same as before.
(11) For Accelerometers. Verify under Arc++
Using App: com.innoventions.sensorkinetics,
small movement's charts looks as expected.
TEST=For generic EC regression test:
On Caroline EC (Without CONFIG_I2C_XFER_LARGE_READ defined).
Details in CL:810332
BUG=b:63993891
Change-Id: I654868945fa535e784800177d54eb2d9803f5249
Signed-off-by: Chun-Ta Lin <itspeter@google.com>
Reviewed-on: https://chromium-review.googlesource.com/788479
Commit-Ready: Chun-ta Lin <itspeter@chromium.org>
Tested-by: Chun-ta Lin <itspeter@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The PNPCFG (EC2I control module) is used to set I/O port base
address and IRQ number.
On it8320, PNPCFG will be reset while system event PLTRST_L
is asserted. This means we can't decode I/O cycles correctly
until we re-initialize PNPCFG.
We disable this reset source, then we don't need to re-initialize
PNPCFG for each PLTRST_L asserted.
BRANCH=none
BUG=none
TEST=MECC board with it8320 + Intel SKL-Y RVP3 and boot to shell.
Change-Id: I7efe8f726939245424237c1d153df4f83b39ae6b
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/810428
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Update genvif so that it can create Rev 1.22 Vendor Info Files. Also
format the VIF so that it matches VIFs generated with the USB VIF
generator.
BUG=b:69972352
BRANCH=None
TEST=`make -j buildall`
Used generated VIF for nasher on GRL Test Equipment
Signed-off-by: Sam Hurst <shurst@chromium.org>
Change-Id: I35bc940c0c65c89be9a40ff9228e51123f136e7b
Reviewed-on: https://chromium-review.googlesource.com/801874
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Create a lockfile at
/run/lock/power_override/battery_tool.lock rather than
/run/lock/battery_tool_powerd.lock so that powerd doesn't
need to special-case the file's path.
BUG=chromium:784651
BRANCH=None
TEST=None
Change-Id: I151cf26d635dc969d113e9d80c93177985a7ab2f
Signed-off-by: Daniel Erat <derat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/809921
Commit-Ready: Dan Erat <derat@chromium.org>
Tested-by: Dan Erat <derat@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Even if we set the rtc alarm timeout for more than 86400 secs,
we should not crash the system.
BUG=chromium:768042
BRANCH=none
TEST=on AP console, do 'ectool rtcsetalarm 99999' and
then see 'EC result 3 (INVALID_PARAM)' without crash.
Change-Id: Ic0fa92ff101bce1f4791221c4e1eadaf7a005355
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/807624
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit just adds the GPIO for controlling the display backlight for
meowth and zoombini. The backlight should be enabled from the EC side
on transitions to S0 and turned off when suspending. Additionally, if
the lid is opened or closed the display backlight will be enabled or
disabled respectively.
BUG=b:69972660
BRANCH=None
TEST=`make -j buildall`
TEST=Flash meowth; Boot to S0, verify that the ENABLE_BACKLIGHT GPIO is
set high; Shut down; Verify that ENABLE_BACKLIGHT is 0.
TEST=Repeat above test on zoombini. Also, boot to S0, use a magnet to
simulate the lid closing, verify that ENABLE_BACKLIGHT is 0 when lid is
"closed". Verify it is 1 when lid is "open".
Change-Id: Iffc5db89a0378d354b1fe9e9e5347d57e7caf69b
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/811752
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The SN5S330 has support for detecting when Vbus is present on a port.
This commit simply adds an API to query the PPC.
BUG=None
BRANCH=None
TEST=`make -j buildall`.
TEST=Flash a board with the SN5S330, with some extra code, verify that
Vbus can be detected with this API.
Change-Id: I45bf7ff24bcdc447efe12932f51f8094108e29d5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/791502
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
The default sourcing current limit can be set by the following config
option:
CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT
However, the way that this macro was being used was incorrect for the
SN5S330 driver. Since, enum values are not known at compile time, the
check needs to happen during runtime. This commit makes this change.
BUG=None
BRANCH=None
TEST=Enable CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT on a board that uses
the SN5S330, verify that there are no build errors.
Change-Id: I04a1fa1e2e42c2f4ba49f1769857a8796b2f0a6f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/791501
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This adds a check for the current and new versions,
and will not update if they are matched.
BUG=b:69016431
BRANCH=None
TEST=sudo ./servo_updater.py -b servo_micro
Change-Id: I3462099a086278dc1589609d76facf11a64bd3bc
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/804716
Reviewed-by: Wai-Hong Tam <waihong@google.com>
This patch adds switch-slot option to reboot_ec command. When the
option is specified, it'll make EC switch the active RW slot
before reboot.
BUG=b:69921268
BRANCH=none
TEST=Run ectool reboot_ec cold switch-slot and verify the active
slot is switched.
Change-Id: Iec568be36e6010ed9a51aa768a7f35e4a63f0fc0
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/809944
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This patch sets the max PD power to 100W. It means if all devices
(chager, cable, Fizz) agree, the system can draw upto 100W from
a type-c charger.
BUG=b:70239357
BRANCH=none
TEST=Boot Fizz with Apple 87W charger and verify chgsup comamnd
prints 86W (20V, 4.3A). Boot Fizz with Zinger and verify chgsup
command prints 60W (20V, 3.0A).
Change-Id: I74885c5655f570a91eea49660d537d4f9338356c
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/810004
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Unified Host Event Programming Interface (UHEPI) enables a unified host
command EC_CMD_PROGRAM_HOST_EVENT to set/get/clear different host events.
Old host event commands (0x87, 0x88, 0x89, 0x8A, 0x8B, 0x8C, 0x8D, 0x8E,
0x8F) is supported for backward compatibility. But newer version of
BIOS/OS is expected to use UHEPI command (EC_CMD_PROGRAM_HOST_EVENT)
The UHEPI also enables the active and lazy wake masks. Active wake mask
is the mask that is programmed in the LPC driver (i.e. the mask that is
actively used by LPC driver for waking the host during suspended state).
It is same as the current wake mask that is set by the smihandler on host
just before entering sleep state S3/S5. On the other hand, lazy wake masks
are per-sleep masks (S0ix, S3, S5) so that they can be used by EC to set
the active wake mask depending upon the type of sleep that the host has
entered. This allows the host BIOS to perform one-time programming of
the wake masks for each supported sleep type and then EC can take care
of appropriately setting the active mask when host enters a particular
sleep state.
BRANCH=none
BUG=b:63969337
TEST=make buildall -j. And verfieid following scenario
1). Verified wake masks with ec hostevent command on S0,S3,S5 and S0ix
2). suspend_stress_test with S3 and S0ix
3). Verified "mosys eventlog list" in S3 and s0ix resume to confirm
wake sources (Lid, power buttton and Mode change)
4). Verified "mosys eventlog list" in S5 resume to confirm wake sources
(Power Button)
5). Verified above scenarios with combination of Old BIOS + New EC and
New BIOS + Old EC(making get_feature_flags1() return 0)
Change-Id: Idb82ee87fffb475cd3fa9771bf7a5efda67af616
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/576047
Commit-Ready: Jenny Tc <jenny.tc@intel.com>
Commit-Ready: Jenny Tc <jenny.tc@intel.corp-partner.google.com>
Tested-by: Jenny Tc <jenny.tc@intel.com>
Tested-by: Jenny Tc <jenny.tc@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
This commit introduces a driver framework for power path controllers.
It provides some common PPC APIs as well as allowing a board to use
multiple different PPCs drivers/parts. This should make it easier to
add PPC drivers in the future.
BUG=None
BRANCH=None
TEST=`make -j buildall`
TEST=Flash zoombini; verify PPC works as expected.
TEST=Flash meowth; verify PPC works as expected.
Change-Id: Icfb99f384610590b431456cfd28d4aff18442cb2
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/807630
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This CL adds the flag --save_stats_json which prints the MEAN
of sweetberry readings into json format. Corresponding unit
test has been added too. Printing just the MEAN in json format
makes it easier to read it back in power_telemetry_logger,
which uploads the stats to the dashboard.
This CL is part of the effort to start sweetberry measurements
while running power autotests.
BRANCH=None
BUG=b:68956240
TEST=./powerlog.py -b xxx.board -c xxx.scenario \
--save_stats_json [directory to store it]
python -m unittest -v stats_manager_unittest
Change-Id: I8274bcac21175f6c53184ced79b6ffe5e7d7a72a
Signed-off-by: Mengqi Guo <mqg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/807636
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
ccdstate just prints state. It is very useful for debugging ccd/servo
contention issues. This change makes it a safe command so it is
accessible even when the console is locked.
BUG=none
BRANCH=cr50
TEST=make buildall
Change-Id: I2e754f5978c83fcaca737e7a590dcf5ee445522c
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/809864
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
After firmware update, cr50 toggles the EC's reset line, expecting
the system will boot. This isn't the case for Chromebox because it
sets AP_OFF flag on a clean shutdown (to restore the previous power
state after power loss & restore).
This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot
command. It makes EC first clear AP_OFF then hibernate.
BUG=b:69721737
BRANCH=none
TEST=Verify Fizz reboot after cr50 update.
Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/802632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It will be useful to determine if a FET is enabled or not. For example,
to determine if we are sourcing power to a downstream device. This
commit simply adds an API to check if a FET is enabled or not.
BUG=None
BRANCH=None
TEST=`make -j buildall`
Change-Id: I1f8198342cf225ce9a10d218607bcfbe6aef618c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/791498
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
When the SN5S330 is powered initially, there will be certain events set
that will assert its interrupt line. As part of the initialization for
this part, we should clear all the pending interrupts and setup the
masks for the events that we care about.
This commit clears all interrupts at init time and masks all interrupts
except for overcurrent condition for PP1.
BUG=b:69139844
BRANCH=None
TEST=Flash zoombini; With nothing plugged in, verify that the interrupt
line is deasserted at boot.
TEST=Repeat the above test with a charger plugged in.
Change-Id: I7acc030184b76d6c38a729cb64658f71e376c819
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/783510
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
Also added CONFI_ISH_I2C_PORT0_SPEED, CONFI_ISH_I2C_PORT1_SPEED, and
CONFI_ISH_I2C_PORT2_SPEED to define speed for each ISH I2C port. By
default, those are set to fast mode, 400kbps, I2C_SPEED_FAST.
The values can be modified in board.h.
BUG=None
BRANCH=None
TEST=On Soraka modified board for ISH, set I2C stardard mode, fast mode
and fast mode plus, measured I2C clock freq using scope respectively and
confirmed the freq matched I2C mode.
Change-Id: I426b50dc935c3760903360a50f6069e99bd0abff
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/784091
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If VBUS toggles between 'present' and 'not-present', and fusb302 is the
arbiter of VBUS presence, wake the PD task so that it can take the
necessary protocol actions (eg. transition out of HARD_RESET_RECOVER).
BUG=b:69482362
BRANCH=None
TEST=On scarlet, issue EC reset with CableCreation source dock plugged,
verify we don't end up in hard reset loop.
Change-Id: I88d6102a6b5f4bd5151bae117c70f0a3ac0c09e7
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/804660
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This allows ec and cpu uart to start enabled,
so console or google serial can be used to log
output without servod.
Rename endpoints to be clearer in the non-servod
usecase. UART1 -> EC, UART2 -> CPU.
BUG=None
BRANCH=servo
TEST:miniterm.py -d /dev/google/Servo_Micro-2-1.2/serial/EC
Change-Id: Ifd3b753a459fdd9b80d84cc6e4ec9cde1ccb74e0
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/804899
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
The error processing logic is reversed, which results in missing error
values when errors actually happen.
BRANCH=none
BUG=none
TEST=verified that errors values are now reported properly.
Change-Id: I282920d35e978a704e8c2728a8aa71a5f1da9a00
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/802994
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
CHARGE_MAX_SLEEP_USEC was originally set to 1 minute (i.e. equal to
POLL_PERIOD_VERY_LONG) in CL:191767. However, during re-factoring in
CL:193876 it got changed to 1 second as charge_state_v1 used this
value. Looking at the way CHARGE_MAX_SLEEP_USEC is used, value of 1
minute makes more sense because sleep_usec could be set to
POLL_PERIOD_VERY_LONG when device is off or suspended. With the
current logic in suspend/off state, sleep_usec is set to
POLL_PERIOD_VERY_LONG and immediately gets reset to
CHARGE_MAX_SLEEP_USEC in charger_task.
This change fixes the above behavior by defining CHARGE_MAX_SLEEP_USEC
as 1 minute. As a side-effect of this, we might not wake up early
enough in case of critical battery. Thus, check if we need to shutdown
on critical battery and adjust sleep time accordingly.
BUG=b:69695376
BRANCH=None
TEST=make -j buildall
Change-Id: Ieba7279dc4b02c3d64022c3c5ac09fb869a3632d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/788181
Reviewed-by: Shawn N <shawnn@chromium.org>
If during PMIC initialization, it is identified that there was a VR
fault, then dump fault registers 0x16 and 0x17 to EC console. This
information is very useful during debugging sudden power losses in
field and so it is printed out to EC console.
Additionally, add panic reason with these register values as panic
data so that OS can provide this information in cros ec
panicinfo. This helps in retaining the information even if EC console
logs overflow.
BUG=b:65732924,b:69334392
BRANCH=None
TEST=Verified that on the failing Lux system, PMIC VR fault is
reported:"PMIC VRFAULT: PWRSTAT1=0x00 PWRSTAT2=0x01".
Also, verified that pmic fault register info is reported correctly in
panicinfo:
cat /sys/kernel/debug/cros_ec/panicinfo > /tmp/panicinfo
hexdump -n 1 -s 0x14 -e '"0x""%02X""\n"' /tmp/panicinfo
0x00
hexdump -n 1 -s 0x15 -e '"0x""%02X""\n"' /tmp/panicinfo
0x01
Change-Id: Ic6096887cd66046d11a5eb1d942b635b3e48a236
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/674033
Reviewed-by: Shawn N <shawnn@chromium.org>
Add a hook for CHIPSET_RESET to allow the EC to indicate if there is
any new panic info present. This helps coreboot to log EC panic info
in eventlog.
Also, update the hook priority for CHIPSET_RESET and HOOK_INIT to
HOOK_PRIO_LAST to allow the EC to first log any software panic before
it is checked.
BUG=b:65732924,b:69334392
BRANCH=None
TEST=Verified following:
1. Force panic_set_reason in EC on CHIPSET_RESET
2. reboot on AP console
3. mosys eventlog list shows "EC Event | Panic Reset in previous boot"
Change-Id: I77b49cd0b3bf05b10efc708e3d81af9ed0e3aa49
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/797911
Reviewed-by: Shawn N <shawnn@chromium.org>
This change adds a new software panic type PANIC_SW_PMIC_FAULT that
can be used to report any PMIC faults during previous boot.
BUG=b:65732924,b:69334392
BRANCH=None
TEST=make -j buildall
Change-Id: I218b5d01ee145bb02a773495046f4255f1ec8986
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/797910
Reviewed-by: Shawn N <shawnn@chromium.org>
- We have more flash space to use with nds32 toolchain GCC6.3.0,
so we enable a few console commands that were disabled previously.
And we also enable LTO to reduce the size of FW image.
- Put "__wait_evt" function into ram_code section to
fill the gap of flash and improving performance of code-fetch.
BUG=none
BRANCH=none
TEST=boot to kernel on reef_it8320.
Change-Id: I3b745ff80a57ef1163794864c39c22f7e1f86634
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/788712
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Stalling reset during when CS is asserted is useful to start with, it
was added before out of abundance of caution, but come to think of it,
should the reset happen asynchronously driven be the EC, the AP would
be reset too. And when AP is reset on its own accord, it would not be
transmitting anything on the SPI interface.
On top of that it turns out that in some cases reset on ARM platforms
is accompanied by the CS line driven low, which causes infinite loop
if Cr50 is waiting for CS to deassert before proceeding.
BRANCH=cr50
BUG=b:67008109
TEST=verified that RMA reset operates properly on both ARM and x86
platforms.
Change-Id: I43efd0cefa5d6eb543dfd27e3c9fb3b4bf1a8ea6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/791818
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Coral family has couple SKUs configured in clamshell form
factor, in order to avoid external magnetic field unexpectedly
switches clamshell device into tablet mode, this patch disables
tablet mode interrupt for SKUs in clamshell form factor.
BUG=b:67917181
TEST=emerge-coral chromeos-ec, image to clameshell device,
apply external magnetic field and examine no unexpected
switching to tablet mode through watching powerd logs;
alternately, watch the command 'ectool gpioget TABLET_MODE_L'
changes from 1 to 0 without interrupt, this requires some
hacking dump in board_set_tablet_mode() as reverse proof.
i.e.
tablet_mode_interrupt()
... (deferred hook)
enable_input_devices()
board_set_tablet_mode()
Change-Id: Iccf14cd5e2ea71ab3204aa386f476a9a0e1550c4
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/754148
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Coral family has couple SKUs configured in clamshell form
factor, in order to avoid external magnetic field unexpectedly
deasserts TABLET_MODE_L and switches device into tablet mode,
this patch ignores the TABLET_MODE_L pin status for those SKUs.
In other words, always set tablet_mode as 0 for clamshell SKUs.
BUG=b:67917181
TEST=emerge-coral chromeos-ec, image it to clamshell device,
apply external magnetic field and examine there is no unexpected
switching to tablet mode through watching powerd logs.
Change-Id: Ibbe08a00bb14144cad87fdd5a4a39cb3bfe2968e
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/748944
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Exitting the recovery insert screen requires pushing the volume up
and volume down keys simultaneously. Modifying the button command
to support multiple buttons.
BUG=b:69390675
BRANCH=None
TEST=button vup vdown 5000
button vdown vup 5000
button vup vdowne
button vdown vup
Make sure that the above command press and release both volume keys.
Make sure that there is a delay added into between presses/releases.
Change-Id: I65817ff6c9da8c422af3345b2d0878b52387b13e
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/783515
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Coffeecake can charge 5V at 3A current. Host high pullup should be
Rp3000 instead of Rp1500. This change sets USB_C_CC1_DEVICE_ODL to
push-pull mode.
BRANCH=none
BUG=b:67910633
TEST=manual
connect Twinkie sink and measure the CC adc
Signed-off-by: Rong Chang <rongchang@chromium.org>
Change-Id: I471c2f2269ad412851096acb23daf1a5b7dab437
Reviewed-on: https://chromium-review.googlesource.com/758319
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
We may as well enable this for the early builds of grunt. It changes the
initial power button state to IDLE instead of INIT_ON, adds power signal
logging, and allows port80 printing in interrupt context.
It doesn't look like we use eSPI Virtual-Wire for communication, so this
should be fine.
BUG=b:64935726
BRANCH=none
TEST=make BOARD=grunt && make buildall -j
Change-Id: Id0049dc6733a3ff8727ea9fc616ac8ce24364ae1
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/794290
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
