Move common USB charger code out of board directory including
setting VBUS supplier when VBUS changes, and initializing BC1.2
supplier types on init.
This also enables re-enabling of Pericom BC1.2 detection interrupts
when VBUS is changed on all boards that use USB_CHG task.
BUG=chrome-os-partner:42292
BRANCH=none
TEST=make -j buildall. Tested on glados and samus by plugging in
a few different chargers and making sure we charge.
Change-Id: Ib102fbf7a6aace998e6fcb6d35f3c97e5f03f5c2
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290453
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
Configure boards whose chipset cannot be a USB UFP to disconnect
USB lanes when the data role is UFP.
BUG=none
BRANCH=strago
TEST=make -j buildall. tested on glados by adding ccprintf to
usb_charger_set_switches(). verified when we are DFP, USB 2
switches are connected and when we are UFP, they are disconnected.
Change-Id: Ic8c817a0cc21b56ee67239e8cc81d5cbbda8d4de
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/290422
Reviewed-by: Shawn N <shawnn@chromium.org>
Allow more than one SPI master.
Add CONFIG variables to address the system SPI flash.
To have SPI master ports, spi_ports array must be defined.
BRANCH=smaug
TEST=compile
BUG=chrome-os-partner:42304
Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288512
Commit-Queue: David James <davidjames@chromium.org>
Enable Try.Src for Glados, Kunimitsu, Strago, and Oak so that they
default to sourcing power when connecting to other dual-role
devices.
BUG=none
BRANCH=strago
TEST=make -j buildall
Tested on glados by plugging in charger, hoho, and another
dual-role device and making sure we resolve roles appropriately.
Change-Id: I9393e30b35620eeda3ef1ef56366a97e59ba8054
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288247
Reviewed-by: Shawn N <shawnn@chromium.org>
Following features are enabled.
1. Initialise the ADC ports to avoid floating state due to thermistors.
2. Enable the daughter board volume buttons.
3. Enable the PMIC control support.
BUG=none
TEST=Device boots to UI.
BRANCH=none
Change-Id: I27907cb79e165ce6c3df9249a35904aa12717c95
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/284110
Reviewed-by: Shawn N <shawnn@chromium.org>
Allow multiple GPIOs to wake the EC from hibernate by requiring boards
to define hibernate_wake_pins and hibernate_wake_pins_used. In addition,
clean up the GPIO-skipping hibernate code, and skip setting PCH_RTCRST
as an input due to a bug on certain boards.
BUG=chrome-os-partner:42104
TEST=Manual on Glados. Run 'hibernate' from EC console, verify that EC
wakes with power button press or with "dut-control lid_open:no".
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I13a6e062393cab8ed7129eda253585951f771109
Reviewed-on: https://chromium-review.googlesource.com/285924
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Store at which frequency each sensor should be sampled.
This frequency is different from the sensor frequency:
- sensor frequency: frequency at which the sensor produce information.
- sensor sampling frequency: frequency at the which the EC gater
information.
If 2 sensors must be sampled at very different frequency,
we don't want to oversample the slow one, and filling the
software FIFO unnecessarily.
BRANCH=smaug
TEST=Unit test. Check that frequency is correct when sensor
frequencies change from IIO driver.
BUG=chrome-os-partner:39900
Change-Id: I4272963413f53d4ca004e26639dc7a2affd317eb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284616
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Remove duplicate board_discharge_on_ac() functions and create
CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM for boards that have a
unique implementation of board_discharge_on_ac().
BUG=chrome-os-partner:42294
BRANCH=none
TEST=make -j buildall.
load on samus and test 'ectool chargecontrol discharge' forces
discharging on AC, and 'ectool chargecontrol normal' resumes normal
charging.
Change-Id: I2b7c04b9278d07748d6d41798ceab1a7e90684e4
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284911
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Removed USB enable/disable as it will be handled by
HOOK task as CONFIG_USB_PORT_POWER_SMART is enabled.
BUG=none
TEST=Verified on Acer EVT GPIO USB1_ENABLE and USB2_ENABLE value
changed when state switch between S3 and S5.
BRANCH=none
Change-Id: I85f2047c1a40aebf36743a17d353ff3bc481d867
Signed-off-by: li feng <li1.feng@intel.com>
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/283593
Reviewed-by: Shawn N <shawnn@chromium.org>
GPIO_INT_DSLEEP is useful on LM4 to save power when in deep sleep
by allowing us to disable clock to gpio blocks unless it's needed
as a wake source. The MEC and ST chips don't have this option, so
all gpio's can be used as wake source from deep sleep. Therefore
remove this flag from all boards where this flag doesn't do
anything to remove confusion.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I4cb175431a22f100035a81b32e9367b510f4836e
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284742
Reviewed-by: Shawn N <shawnn@chromium.org>
This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.
BUG=chromium:496895
BRANCH=none
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Common battery cut-off host command / console command infrastructure
already exists behind CONFIG_BATTERY_CUT_OFF, so add the config rather
duplicating the code at the board level.
BUG=chromium:488157
TEST=Manual on Squawks. Verify that both "cutoff" on the ec console and
"ectool batterycutoff" succeed to cut-off the battery.
BRANCH=None
Change-Id: I159026d54924e058ea0262db04d8770c663ee613
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271513
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Move structure used by lms6ds0 to motion_sense.h,
so that bosh driver can use the same mechanism.
Use code to avoid reading chip range when reading data.
BUG=none
BRANCH=none
TEST=Check Bosh driver is working as expected.
Change-Id: Id8b5bb8735e479a122ef32ab9a400fba189d7488
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270453
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The same code exists in four (soon to be five!) different power
sequencing drivers, so move it up to common.
BUG=None
TEST=Manual on Samus. Run "pause_in_s5 on" on EC console, verify that
system stops in S5 on shutdown. Run "pause_in_s5 off" on EC console,
verify that system again goes to G3 on shutdown.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaf05ef7ce017be4f9d173e83e985a7a879ba278c
Reviewed-on: https://chromium-review.googlesource.com/269566
Reviewed-by: Randall Spangler <rspangler@chromium.org>
The USB power is off in S5 with previous ChromeBook.
The braswell platfrom should be the same as before.
BUG=chrome-os-partner:39507
BRANCH=cyan
TEST=The usb power is off in G3/S5 and is on in S3/S0 by ec console.
Change-Id: I719f213a9eb0180f7e95e4c2717c038c79ef56fe
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/267451
Reviewed-by: Shawn N <shawnn@chromium.org>
In S3 state, sensors loose their power. Prevent any initiation of
communication with the sensors.
BUG=None
TEST=With Servo connected, verify that no I2C failures are reported
on EC Console when system is brought to S3.
BRANCH=None
Change-Id: I1988c40aa9de48403e9e3a6be5aec3b7267c29e0
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/268481
Reviewed-by: Shawn N <shawnn@chromium.org>
With mec1322's EMI set to decode IO 0x800, it does not have any other
interfaces to support POST code via IO 0x80.
This change is to enable Port80 POST code support via polling method.
Limitation:
- POST Code 0xFF will be ignored.
- POST Code frequency is greater than 1 msec.
BUG=chrome-os-partner:39386
TEST=Verified Port80 POST code is captured in EC console.
Verified "port80 task" console command will disable/enable Port80 task.
Verified "port80 poll" will get the last Port80 POST code.
BRANCH=none
Change-Id: I27e53e84b5be1fd98464a44407dd58b93d8c798d
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/266783
Reviewed-by: Randall Spangler <rspangler@chromium.org>
lfw is a customized boot loader with max targeted code size of 4k
and data size of 2k.It supports minimal functionalities required to
support chromebooks RO/RW architecture.It is placed in the
write porected section with RO image .
Capabilities include SPI,DMA,UART with minimal debugging support.
Currently sysjump support is missing and exception handling is very basic.
BUG=chromium:37510
TEST=make buildall -j, flashing and booting on strago
BRANCH=None
Change-Id: I803998d489297dfe0745dcccbb54412035d73f78
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265904
Reviewed-by: Randall Spangler <rspangler@chromium.org>
mec1322 I2C controller 0 has two attached ports. Modify the I2C driver so
that both ports are usable.
BUG=chrome-os-partner:38335,chrome-os-partner:38945
TEST=Manual on strago. Verify that i2cscan is functional.
BRANCH=None
Change-Id: I18d9d516984d041a38c86fd4ec1b0bfa4e885c9f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/265951
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Previously for the mec1322 chip an ec.bin file was created in the normal way
and then it was "packed" in a post-processing stage to produce ec.spi.bin.
This change allows a chip or board build.mk file to specify the rules used to
produce ec.bin, and uses this for the mec1322 to do the packing. This means
that we can use the standard "ec.bin" name, and do not need to alter other
scripts, such as the script which creates chromeos-firmwareupdate.
BUG=None
TEST=buildall -j, flash on strago and see it still works.
BRANCH=NONE
Change-Id: I3f880d64e60d14f82cb1d21c8b3f2d4ae5e0dfef
Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265544
Tested-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Kevin K Wong <kevin.k.wong@intel.com>
This allows switch status to be updated to EC MemMap.
BUG=none
TEST=Verified mmapinfo console command is reporting the correct info.
BRANCH=none
Change-Id: I3b6683be8b92b59dffb3227e0a72a122dcda56a2
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/265493
Reviewed-by: Shawn N <shawnn@chromium.org>
In the gpio_info struct, we had a irq_handler pointer defined even
though a majority of the GPIOs did not have irq handlers associated. By
removing the irq_handler pointer out of the struct, we can save some
space with some targets saving more than others. (For example, ~260
bytes for samus_pd).
This change also brings about a new define:
GPIO_INT(name, port, pin, flags, signal)
And the existing GPIO macro has had the signal parameter removed since
they were just NULL.
GPIO(name, port, pin, flags)
In each of the gpio.inc files, all the GPIOs with irq handlers must be
defined at the top of the file. This is because their enum values from
gpio_signal are used as the index to the gpio_irq_handlers table.
BUG=chromium:471331
BRANCH=none
TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power
button, keyboard, charging, all still working.
TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build
fail.
TEST=make -j BOARD=peppy tests
TEST=make -j BOARD=auron tests
TEST=make -j BOARD=link tests
Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/263973
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
MEC1322 KSO00~03 pin has an alternate JTAG function. For board that needs JTAG
function, this #define allows hardware to use a different set of KSO pins.
For example - Uses KSO04~16 instead of KSO00~KSO12.
BUG=none
TEST=Verified keyboard is functional with all keys detected
BRANCH=none
Change-Id: I1e3c1c2b6a4420cb6296b6bc921affa8c0ed5800
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/264610
Reviewed-by: Shawn N <shawnn@chromium.org>
I2C ports initialized as per board design. Modules
assigned to its corresponding I2C port numbers
Altered the SPI flash size to match the Braswell Ref Design board
BUG=None
BRANCH=None
TEST=Tested all I2C modules on all ports using i2cscan and i2cxfer
console commands
Change-Id: I4158c1aeb29193b5bd07450ba28cdcdc2413926a
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/264261
Reviewed-by: Shawn N <shawnn@chromium.org>
Setting up numbers for Battery info like input current limit,
Battery voltage, temperature limits as per the actual battery spec.
BUG=None
TEST=Tested on Braswell Ref Design
BRANCH=None
Change-Id: I66c3dfe6166d03d2cb79d80a887168f08753d22d
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/260631
Reviewed-by: Randall Spangler <rspangler@chromium.org>
W25X40 uses a different protection register encoding than our existing
W25Q64 code. Move the SPI ROM option to a config, and add support for
the new part.
BUG=chrome-os-partner:37688
TEST=`make buildall -j`. W25X40 protection code tested in a subsequent
commit.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Iaaeabf42c6c62c20debc91afd2cf8671c14244c8
Reviewed-on: https://chromium-review.googlesource.com/258440
Reviewed-by: Randall Spangler <rspangler@chromium.org>
