The SLEEP_MASK_SPI will not be cleared, if SPI received a bad data.
It is possible to block EC to enter deep sleep if AP send a bad
packet to EC before AP goto S3/S5. In order to ensure that deep
sleep can be enabled, clear SLEEP_MASK_SPI in chipset suspend hook
to avoid this situation.
BUG=chrome-os-partner:44170
BRANCH=None
TEST=manually
1. use AP console command to let AP enter S5:
> shutdown -h now
2. check the sleepmask in EC console.
> sleepmask
sleep mask: 00000000
Change-Id: Ib5f5c421c123d9a3c2cc6fead07c8fa515e452f1
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/294432
Reviewed-by: Rong Chang <rongchang@chromium.org>
The USART peripheral in the L and F families is different enough to need
different receive drivers. In particular, the L family USART perihperal
has no way of disabling the overflow error bit. So for that family we
check and clear the bit, and keep a count of overflows.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Iea26c242d5177afd552a3bd4d6ab1a9c7a65f90e
Reviewed-on: https://chromium-review.googlesource.com/288978
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Now that v3 support is in the cros_ec kernel driver and depthcharge,
deprecate support for the old v2 protocol. At some point in the future,
support for the v2 protocol will dropped entirely.
Boards that require support for the V2 protocol should enable the
following config option.
#define CONFIG_SPI_PROTOCOL_V2
BUG=chrome-os-partner:20533
BRANCH=None
TEST=make -j buildall tests
TEST=Flash jerry, AP & EC boot successful.
TEST=`ectool protoinfo` shows only version 3 supported on jerry.
TEST=Flashrom still works on jerry.
Change-Id: I72d3aee00879314b936cc0b1002c9883550b1f1a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/291411
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Like the implementation for mec1322, add a lock around spi_transaction.
It prevents 2 tasks from accessing a given bus at the same time.
BRANCH=smaug
TEST=Check the BMI160 FIFO corruption disappeared in SPI mode.
BUG=None
Change-Id: I9e8a9e39ca96ea56692e3125930ab05ae6ef143f
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289856
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Remove assumption of only one SPI master going to the SPI flash.
SPI3 can be used as second SPI master.
Define a new module type, SPI_FLASH, that can be turned
on/off when flash is not in used without impacting other
SPI masters.
BRANCH=smaug
BUG=chrome-os-partner:42304
TEST=Test on Ryu board.
Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288514
Allow more than one SPI master.
Add CONFIG variables to address the system SPI flash.
To have SPI master ports, spi_ports array must be defined.
BRANCH=smaug
TEST=compile
BUG=chrome-os-partner:42304
Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288512
Commit-Queue: David James <davidjames@chromium.org>
Decrease default system stack size on stm32f05 which only has 8k
of RAM.
BUG=none
BRANCH=none
TEST=tested on glados. just ran glados_pd and plugged various
peripherals into type-C port and saw nothing unusual.
Change-Id: Ic051a1387903662414c8e4fdc431e6ecfd7ad57f
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/289555
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Define second DMA controller, to be used by SPI3 on STM32F373.
BRANCH=smaug
TEST=Check with dmahelp the DMA engine is activated.
BUG=chrome-os-partner:42304
Change-Id: Id2490ab91092b1ed738f5318bdeebfbe93f09171
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/288511
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The atomic_* functions are often used in contexts where the data they
will operate on are volatile (due to being shared between tasks or a
task and an interrupt handler). Adding volatile here makes using the
atomic_* functions a little easier in those cases and removes a cast
from the call sites (which could be obscuring a bug, if for instance
the variable was modified to be a uint16_t).
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I71356eb3cf2c0506df38532eee767c7d78f9240e
Reviewed-on: https://chromium-review.googlesource.com/287516
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
This adds a new transmission implementation for the multi UART driver.
It is a DMA based transmitter that can directly read from the TX queue
with zero copy overhead. The DMA channel used as well as the maximum
DMA transmission size are configurable per UART at the board level.
This also updates the Ryu AP UART to use DMA transmission.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Manually verify that the AP UART forwarding works
Change-Id: I3cb27d0f9015043d75a38c12919388afe90dc4af
Reviewed-on: https://chromium-review.googlesource.com/286274
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
The same calculation is used across the code, so move it to a common
macro.
BUG=chrome-os-partner:42104
TEST=Verify Glados still boots AP.
BRANCH=None
Change-Id: I90da348f37fc670971737cfc5ddcfb9c34096c4b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/286169
Reviewed-by: Alec Berg <alecaberg@chromium.org>
In order to support DMA transfers in one or both directions the usart
driver needs to be configurable with producer/consumer operations and
interrupt handler functions. These are now packaged up in the usart_rx
and usart_tx structs, and versions for interrupt driven RX and TX are
provided.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: I3fd14c675c90873e903195b8e20d2070d2eda5ac
Reviewed-on: https://chromium-review.googlesource.com/285023
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
To avoid FIFO errors - the fifo becomes full will we wait for the AP
to read the vectors, increase the i2c speed between EC and AP.
Target 1Mhz, 400KHz observed due to a limitation of the Tegra I2C
controller.
BRANCH=smaug
TEST=Verify with analyzer that speed is now 400KHz.
The duty cycle is still not right.
Check that FIFO underrun do not happen during tests.
BUG=chrome-os-partner:40280,chrome-os-partner:39233,chrome-os-partner:39900
Change-Id: Id6c2dfb10c34a919ec99a58bc0082207f7748b7e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284613
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This unifies all the EC header files to use __CROS_EC_FILENAME_H
as the include guard. Well, except for test/ util/ and extra/
which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively.
BUG=chromium:496895
BRANCH=none
TEST=make buildall -j
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029
Reviewed-on: https://chromium-review.googlesource.com/278121
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This just makes the LEDs blink continually, because I have a
development board sitting on my desk and I like to see it doing
something.
You can still force the GPIOs on and off using the tool in
extra/usb_gpio/.
BUG=none
BRANCH=none
TEST=make buildall
Try it:
sudo make BOARD=discovery-stm32f072 flash
The LEDs blink.
Force them on and off with:
cd extra/usb_gpio
make
./usb_gpio write -1 0
./usb_gpio write 0 -1
./usb_gpio write 2 0
./usb_gpio write 4 2
To resume blinking, use
./usb_gpio write 0 0
Change-Id: Iadbe7436c02de5b6eae81885d95bad154ca3692c
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274131
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Move disabling the TX timer up to as soon as possible after
DMA transmit is complete to avoid potentially clocking another
bit, which could corrupt the end of the transaction.
BUG=none
BRANCH=smaug
TEST=load on glados and use a scope to verify the end of transmit
is clean.
Change-Id: If52ba2475eeb9752da0acc8efc957c1f472bc711
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277298
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Change pd_tx_done() to wait specifically for the DMA complete
event using task_wait_event_mask().
This fixes a potential bug where if we get another event, for
example a TCPM event, while waiting for transmit to complete
we restore the pending event after we are done.
BUG=none
BRANCH=smaug
TEST=run on glados and make a bunch of contracts with zinger.
Change-Id: Ie28d97eba3edcc7a98fe842e8b7eb6b9d7707047
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/277297
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The in_stream and out_stream interfaces were a first attempt
at providing an abstraction for multiple stream like devices
(usart, USB, I2C/LPC host interfaces...). But, by baking
the queue into the device it proved to be hard to use and
required additional resources (task or deferred hook) to handle
passing data from one stream to another.
Since then the queue policy and producer/consumer interfaces
have replaced the stream interfaces. This CL removes the old
stream interfaces and updates the only users (deleting the
test echo code from the discovery-stm32f072 board and updating
the mcdp28x0 driver to use the queue interfaces).
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Change-Id: Ic0d2abf81eafc4fb2e61172540151f2d0ba45caf
Reviewed-on: https://chromium-review.googlesource.com/276163
Reviewed-by: Todd Broch <tbroch@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Now that we've removed boards from ToT, also delete board-specific
code used only by the removed boards.
There are still more things to remove (unused charging chips, LED
drivers, COMx support). More CLs coming.
BUG=chromium:493866
BRANCH=none
TEST=make buildall -j
Change-Id: Ie6bdeaf96e61cadd77e3f6336c73b9b54ff4eabb
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/276524
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Ensure that we put a proper start bit if the transfer only contains a
read but has the start flag set.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=smaug
BUG=chrome-os-partner:40919
TEST=On Smaug (P6), at the Linux prompt, do
"cat /sys/class/power_supply/bq27742-0/current_now" and see a proper
value rather than an error.
Change-Id: I10cc9907476b3cfb006f2c1540688139366c9195
Reviewed-on: https://chromium-review.googlesource.com/275079
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Puthikorn Voravootivat <puthik@chromium.org>
Add TCPM on EC side and TCPC on PD side to allow PD
communication. Enable PD communication on port 0.
BUG=none
BRANCH=none
TEST=load on oak. plug in hoho on port 0, and make sure
we successfully negotiate a PD contract. (note: you have
to manually enable 5V VBUS right now)
Change-Id: I0ce7c016545bc56c5e10f66b49b73722187f12dc
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271829
Reviewed-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Sheng-liang Song <ssl@chromium.org>
Commit-Queue: Sheng-liang Song <ssl@chromium.org>
This moves the STM32-specific code out of the common header file
and into the chip directory where it belongs. Note that this
doesn't actually change the code for non-STM32 SoCs; that will
happen in a separate CL for clarity.
BUG=chrome-os-partner:40693
BRANCH=none
TEST=make buildall
Change-Id: Ifdf0086e86a1088fb011b9ac4d6c70ab8da47aec
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/273577
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add initial support for Oak PD MCU on rev1 boards.
This does not include USB PD communication.
BUG=none
BRANCH=none
TEST=build and load on oak and get console. test we
resond to host commands from EC using "pdcmd 0 0" on
EC console.
Change-Id: I92045cf0fd682279ada6c286f5399f0e258a6305
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/271828
i2c_xfer was previously implemented at the chip-level, but now we want
to add some global retry logic. Rename the chip-level i2c_xfer functions
to chip_i2c_xfer and add a new global wrapper function i2c_xfer.
BUG=chrome-os-partner:39613
TEST=Run "battery" from EC console on Cyan, verify that values + strings
are correctly printed.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: If37c85cc3cf94fd53feb6931553e10c30ad6cad6
Reviewed-on: https://chromium-review.googlesource.com/272939
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Add initial support for Oak rev1 board. This is just the
EC and includes battery charging but does not include
USB PD.
BUG=none
BRANCH=none
TEST=load on oak board and get console
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Change-Id: I626f3921025fbc39ba22b04eeb6dd1084cd70777
Reviewed-on: https://chromium-review.googlesource.com/261678
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Move parts of usb_pd_config.h that are not part of the phy layer
out of usb_pd_config.h and into board.h. This cleans up the
division between the TCPC and TCPM as only the TCPC needs to
use usb_pd_config.h.
Also cleans up the use of the CC detection voltage thresholds
by creating standard macros to use based on Rp strength for the
board.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I946cceb38bea8233095b8a4b287102bb8a3a296d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270337
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Since stm32 and mec1322 now support open-ended i2c_xfer, we can move the
lm4 i2c_read_string implementation to common code and delete all
chip-specific versions.
BUG=chrome-os-partner:39613
TEST=Run "battery" from EC console on Cyan and Oak, verify that battery
info + strings are correctly printed.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I06369df64bb2eb747d163664b4c96eeacb4b1faa
Reviewed-on: https://chromium-review.googlesource.com/272938
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Previously the Producer and Consumer interfaces tracked the
Consumer and Producer respectively at the other end of the
queue that they interacted with. This was done to avoid
modifying the queue implementation, but resulted in a rougher
interface that required additional initialization steps and
prevented alternative configurations; many producers and one
consumer for example.
This commit uses the new queue policies to track this
information. The new direct policy behaves as the old producer
and consumers did. Now the producers and consumers are just
named references to the queue that they work on and a convenient
location for a notification callback when the queue is updated in
a way that is relevent to the producer or consumer.
All users of Producer and Consumer have been updated including the
stream adaptors which are in use by the echo test code and the
mcdp28x0 driver. Use of the stream adaptors has also been
simplified.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Manual testing of Ryu (P5) and discovery board echo task
Change-Id: I704be6378a31b4e20f5063295eff9943e4900409
Reviewed-on: https://chromium-review.googlesource.com/271792
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Fix master i2c when sending partial transfers using I2C_XFER_START
and I2C_XFER_STOP.
BUG=none
BRANCH=none
TEST=Tested i2c transfers on oak. tested transfers with
I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) and tested
partial transfers with just one flag. For partial transfers
I tested two different types:
- i2c_xfer START only transmitting, then another i2c_xfer with
more trasnmitting followed by a STOP. verified with logic
analyzer that there is not restart in the middle.
- i2c_xfer START with transmitting and receiving, then another
i2c_xfer with more receiving followed by a STOP. verified with
logic analyzer that there is one restart in between
transmitting and receving and no restart in between the two
calls to i2c_xfer.
Change-Id: Ie4146d1cf7d39f7dc56fd02e65add6bf02772e67
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/272690
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add config options for various parts of USB PD stack:
CONFIG_USB_POWER_DELIVERY: The use of this option has changed
slightly. It now represents whether or not to include the USB
PD protocol and policy layers of the software stack.
CONFIG_USB_PD_TCPC: Compile in type-C port controller module
which performs the phy layer of the PD stack.
CONFIG_USB_PD_TCPM_STUB and CONFIG_USB_PD_TCPM_TCPCI: If
CONFIG_USB_POWER_DELIVERY is defined, then one TCPM needs to
be defined to declare which port management module to use
to drive the TCPC.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I41aa65a478e36925745cd37a6707f242c0dfbf91
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270171
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
stm32f051 I2C slave does not clear transmit interrupt status (TXIS) on
receiving NACK. That fails to support I2C master repeated-start read.
This change moves slave transmit from host command thread's TXIS loop to
interrupt event loop. And enables NACK interrupt to handle master
restart. On the I2C master side, this CL adds i2c_xfer flags.
With this CL, stm32f0 EC can talk to stm32f051 PD through host commands.
BRANCH=None
BUG=None
TEST=make BOARD=<board with stm32f0 EC and PD>
Verify EC console command "pdcmd 1 0 0x10 0x20 0x30 0x40"
Change-Id: I771b4fb3de3732f18da90ea5e27a79afb09689b0
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267041
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the
flash footprint of the firmware.
Add additional protection to some functions/data to avoid removal by the
linker when their usage is not obvious.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall (with and without LTO enable on all boards)
Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059
Reviewed-on: https://chromium-review.googlesource.com/271291
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
- Use CONFIG_*_MEM when dealing with images in program memory.
- Use CONFIG_*_STORAGE when dealing with images on storage.
- Use CONFIG_WP when dealing with the entire WP RO region.
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches
actual layout of image. Verify flashrom succeeds flashing + verifying EC
image using host command interface.
BRANCH=None
Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/270269
Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.
CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image
CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image
CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Cleanup PD receive error enum by including RX in name since
we will have a different enum for TX errors.
BUG=none
BRANCH=none
TEST=make -j buildall
Change-Id: I355092e0e73a022acb4a92736374cd2289d324bf
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267670
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Sometimes the chipset task is slow enough that we might get messages from
the AP before chipset_in_state(CHIPSET_STATE_ON) is true. This causes us
to leave the spi off after our usual reset after every transaction
(see chrome-os-partner:31390). This would put an end to any EC communications.
Instead of relying on CHIPSET_STATE_ON we could just save the value of
"enabled" before we turn it off, then use that as a condition instead.
There shouldn't be a race condition on "enabled" because the only other place
it gets modified is in the hooks, which can't preempt spi_init
(which usually happens in the host command task).
The only problem is that in case of a sysjump enabled will be 0,
so CHIPSET_STATE_ON was left as a backup to handle that case.
This fixup was squashed from Ied3788f83fef548dff3b01bec93d0e40101ba0f7
TEST=Resume minnie from "echo mem>/sys/power/state" a few times, note ec still works
BUG=chrome-os-partner:39564, chrome-os-partner:39576
BRANCH=veyron
Change-Id: I7c33243faebfd74dc33451024c1d75080babee03
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/267593
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Identify and ignore cable reset PD command
BUG=chrome-os-partner:39464
BRANCH=samus
TEST=connect two samus'. on one samus add code to send a cable
reset like such:
int send_cable_reset(int port)
{
int off;
CPRINTF("C%d Send cable reset\n", port);
/* 64-bit preamble */
off = pd_write_preamble(port);
/* Hard-Reset: 3x RST-1 + 1x RST-2 */
off = pd_write_sym(port, off, BMC(PD_RST1));
off = pd_write_sym(port, off, BMC(PD_SYNC1));
off = pd_write_sym(port, off, BMC(PD_RST1));
off = pd_write_sym(port, off, BMC(PD_SYNC3));
/* Ensure that we have a final edge */
off = pd_write_last_edge(port, off);
/* Transmit the packet */
if (pd_start_tx(port, pd[port].polarity, off) < 0) {
pd[port].send_error = -5;
return -5;
}
pd_tx_done(port, pd[port].polarity);
/* Keep RX monitoring on */
pd_rx_enable_monitoring(port);
return 0;
}
Without this CL, the receiving samus times out and ends
up causing equivalent of hard reset. With this CL, we receive
cable reset and drop it.
Also used twinkie to measure goodCRC delay. No measureable
change in delay on samus and zinger. Samus delay is ~70us and
zinger delay is ~65us.
Change-Id: Ic0e871c8cf96502b861f430e05ee145881fb55fa
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/266981
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The memcpy like routines for moving to and from usb packet
RAM couldn't deal with all unaligned uses, this fixes their
behavior. In particular, a previous caller might assume
that the packet RAM addresses were contiguous and attempt
to break up a call into two separate chunks (as the queue
insertion/removal code does). But this can lead to invalid
pointers passed to these memcpy routines. A much cleaner
solution is to make the packet RAM address space contiguous.
To do so the memcpy routines take packet RAM addresses
instead of AHB address space mapped addresses and
__usb_ram_start needed to change to be of type usb_uint so
that pointer arithmatic on it worked correctly on all platforms,
this also allowed the usb_sram_addr macro to be simplified.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Verify that USB still works on Ryu and discovery-stm32f072
Change-Id: I479461f07a3203f1e6e0cf9705f512a5a43c4646
Reviewed-on: https://chromium-review.googlesource.com/264764
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Previously the TX and RX queues were being accessed from two
different locations without locking, which is wrong. This
moves the access to a single location in a deffered hook and
calls that hook from the old locations. The result is
correct, simpler, and not much slower. It also reduces time
in the USB interrupt handler by moving the memcpy from packet
to queue out to the deferred hook.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
BRANCH=None
BUG=None
TEST=make buildall -j
Verify that USB streams still work on Ryu and discovery-stm32f072
Change-Id: I6ea53d7c40b42c6112e86a7886f3b888408f72b7
Reviewed-on: https://chromium-review.googlesource.com/264763
Tested-by: Anton Staaf <robotboy@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Anton Staaf <robotboy@chromium.org>
Trybot-Ready: Anton Staaf <robotboy@chromium.org>
The ADC watchdog is about 2/3 of the ADC code size and it is not
optimized out when not used because adc_read_channel() needs to
stop/restart the watchdog if somebody is using it.
The feature is enabled by default to keep the current behavior on
STM32F0 platform, and it is turned off on samus_pd :
This is saving 448 bytes of flash (and 8 bytes of RAM).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=make buildall and check the firmware size before and after.
when CONFIG_ADC_WATCHDOG is disabled, adc_enable_watchdog() is not
compiled if there is any user the build will fail.
Change-Id: Ie2450bc2a8fd97662322fd3ce87e93c3fece6c6f
Reviewed-on: https://chromium-review.googlesource.com/265303
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
When using the Twinkie dongle without a protocol decoder on the host,
add a simple text tracing mechanism, so the user can get the timestamped traces
of the packets on the wire (in a best effort fashion).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=On Twinkie command-line, type "tw trace on"
then plug a DingDong to Samus through Twinkie and
see the PD message traces on the console.
Change-Id: I4fa35d6783cc6279c95209c86f37e6d717de7301
Reviewed-on: https://chromium-review.googlesource.com/237222
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
We need to clear DMA status before starting another transaction.
Otherwise, we get incorrect values.
Same fix as the one Vic did in CL 240282 for STM32F1xx and STM32F3xx.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:38902
TEST=On the twinkie USB console (without anything connected), do "tw res
rd rd" then "adc". We now always get "CC1_PD = 0 CC2_PD = 0" rather than
some fancy values for CC2_PD such as "CC2_PD = 29097".
Change-Id: I065b2f8f74ba39f805445bab96b45819322a7da3
Reviewed-on: https://chromium-review.googlesource.com/264981
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
In the gpio_info struct, we had a irq_handler pointer defined even
though a majority of the GPIOs did not have irq handlers associated. By
removing the irq_handler pointer out of the struct, we can save some
space with some targets saving more than others. (For example, ~260
bytes for samus_pd).
This change also brings about a new define:
GPIO_INT(name, port, pin, flags, signal)
And the existing GPIO macro has had the signal parameter removed since
they were just NULL.
GPIO(name, port, pin, flags)
In each of the gpio.inc files, all the GPIOs with irq handlers must be
defined at the top of the file. This is because their enum values from
gpio_signal are used as the index to the gpio_irq_handlers table.
BUG=chromium:471331
BRANCH=none
TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power
button, keyboard, charging, all still working.
TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build
fail.
TEST=make -j BOARD=peppy tests
TEST=make -j BOARD=auron tests
TEST=make -j BOARD=link tests
Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/263973
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
- Changed TX BIST mode so that it transmits for 50 msec instead
of transmitting forever.
- Added console command to initiate TX BIST mode.
- Fixed an issue with circular DMA mode which was causing watchdog.
- Modified RX BIST to account for shorter TX BIST duration.
BUG=chrome-os-partner:36335
TEST=Manual on Samus to Samus, manual on Zinger to Samus
BRANCH=Samus
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: I666347de47c81b5b7a1e82c2b99345ff3ebbb7d4
Reviewed-on: https://chromium-review.googlesource.com/256194
Tested-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Trybot-Ready: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
