The derivatives development should be done in the firmware branch.
(here it is firmware-reef-9042.B)
They are way too many 'follow reef settings' CLs, either all derivatives
should be updated at the same time or we have to cut the rotten fruits.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:36192920
TEST=make buildall
Change-Id: I20cbc4897c7e6e3355ca0a4ed0e856d6b1d17eff
Reviewed-on: https://chromium-review.googlesource.com/452459
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The default for servo_v4 DUT port is to be SRC to charge the DUT, but
a UFP data role so that the DUT's usb mux gets connected.
BUG=b:35586526
BRANCH=servo
TEST=Connect to Electro and verify that servo_v4 data role is that of
UFP and that electro is getting an IP address from the enet port on
servo_v4.
Change-Id: I8f2e4242777bf879598852004096f683d68c091c
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/452725
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Previous boards that implemented tcpc layer on chip didn't support
variable Rp values. However, servo_v4 can present any of the 3
possible Rp values and therefore the voltage thresholds that are used
to determine a no-connect or Ra attach status need a way to be set
based on the Rp value that's current attached to a given CC line.
- Added port and cc line selection to both the CC_NC and CC_RA macros
and now check if they are already defined before being defined in
usb_pd_tcpc.c.
- Defined each of these macros in board.h to use a function that's
able to select the threshold based on the current Rp configuration.
BUG=b:35586526
BRANCH=servo
TEST=Tested with servo_v4 against Electro and verified that it
connects when a charger is and is not connected to CHG port which
exercises the differnt Rp combinations that servo_v4 presents.
Change-Id: I1a31e430c0f290486f0fa8a50bdafdddf20d23ca
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451962
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This CL adds support for the DUT port to advertise different current
levels via the Rp resistor selection. The default setting is USB (500
mA).
The board_manage_chg_port function relies on the off->on transitions
only occurring when the CHG port is in a steady state condition. When
the charger being used supports PD messaging, the entry point
pd_set_input_current_limit() which is called after receiving a PS_RDY
message. For TypeC only chargers, the entry point is
typec_set_input_current_limit() which is called from SNK_DISOVERY
after only after the max number of hard reset attempts have been
attempted. This is intended to prevent this entry point from being
called when a USB PD charger is connected and the CHG port enters
SNK_DISCOVERY.
When the CHG port Vbus transitions from off->on, a src_pdo is updated
to reflect the current contract on the CHG port and this src_pdo can
then be used by the DUT port when either a new connection is done or
to update it's existing contract.
BUG=b:35586526
BRANCH=servo
TEST=Manual
Connected servo_v4 DUT port to Reef with no charger
connected. Verified that it connects, and CCD mode in Reef is enabled
(H1 console is available) and that only 500 mA charging current is
advertised. Then connected a 20V and 15V USB PD charger to the CHG
port. In each case verified that the DUT renegotiates to the 20 and
15V level respectively. Repated the test with Guppy and verifed that
VBUS is at 5V 3A. When Guppy is removed, then the DUT connection
reverts back to the host as the VBUS source.
Change-Id: I1a5eb346bbe1f0d586cb8b7bb24d77ff713fbf3c
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/449954
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Add a flash driver for the STM32L4 family.
For write and erase, the code is very similar to other variants
excepted the 'normal' writes need to be perform 2 aligned
32-bit words at a time.
Option bytes are a sligthly easier business since the hardware deals
with the option bytes page preserving and erasing for us.
For the write-protection, the STM32L4 is slightly different from the
other variants. The write-protection granularity is still a 2-kB block
(2kB here) but instead of having a 'bitmap' of the protected blocks, it
defines 2 write-protection ranges (WRP1AR and WRP1BR).
For the EC code base, we are using WRP1AR to protect the Read-Only
regions and WRP1BR to protect the Rollback and RW regions (if they
exist).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35648258
TEST=On Eve, run 'flashrom -p ec:type=fp -w /tmp/ec.bin'
and 'flashrom -p ec:type=fp --wp-enable --wp-range 0x0 0x20000'
Change-Id: Iaa98c1b4d3b07de2923ac076624bd4601c31a600
Reviewed-on: https://chromium-review.googlesource.com/456711
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
The pstate structure is written using the low-level
flash_physical_write() function. As a consequence, it is supposed to
meet the CONFIG_FLASH_WRITE_SIZE alignment constraint.
Add a build-time assertion to avoid silent failures.
Slightly decrease the maximum size of the serial number string, so the
structure has a natural 32-byte alignment which is compatible with a
large number of platforms (including STM32L4 which requires 64-bit
alignment).
Of course, this change is not fully backward-compatible.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chromium:571477 b:35648258
TEST=on STM32L442, build and run 'flashrom --wp-enable' without failure.
Change-Id: Ia8f82790a61a6c7d2cf9bfeb95bfdaf7b8c52d11
Reviewed-on: https://chromium-review.googlesource.com/458201
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Setting PWM IO type in gpio driver seems not a proper way. This
CL moves this functionality to pwm driver and introduces a new
flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it
in board driver.
BRANCH=none
BUG=none
TEST=test pwm functionality on npcx_evb.
Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/458043
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
The cr50 code might need access to certain variables stored in the TPM
NVMEM. In particular the upcoming FWMP support will require reading
the NVMEM FWMP space.
This patch adds a generic function which allows to access TPM NVMEM
spaces. The implementation was borrowed from NV_REad.c in the tpm2
tree, the only difference being that the location, if present, is read
unconditionally, without checking access controls.
The API accepts the NVMEM index in Chrome OS scope and maps it into
TPM2 specification's NVMEM index space based at HR_NV_INDEX. The
definitions are included straight from the tpm2 tree.
BRANCH=none
BUG=chrome-os-partner:62489, chrome-os-partner:62205
TEST=this code is not yet even being compiled, tested with the next
patch.
Change-Id: I8bcfd8637c192249780634491f30e4a28229984f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457823
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
This patch disables IADP immediately after the EC boots. We
observed noise on IADP/RESET pin causing SEL_ILIM_VAL to
randomly change. This seems the cause of b:35648317.
We enabled IADP to fix b:35647661 initially and also followed
the vendor's recommendation. However, the issue is only
reproducible on the particular board which was used for power
measurement and we did not see the issue on other boards with
IADP disabled.
Also the vendor assumed our EC doesn't control IBUS_LIM_SET
and ICC_LIM_SET. (I think they assumed like other thier customers
our EC controls ILIM by DAC connected to IADP/RESET pin.) If ILIM
is not set by EC and IADP is disabled, the system would brownout
because ILIM stays at 128mA. Therefore, it was (mistakenly)
recommended that our EC should keep IADP enabled.
Cros EC configures IBUS_LIM_SET and ICC_LIM_SET dynamically thus
the above concern does not apply.
We also found that we have too much noise on IADP/RESET pin. The
noise is not big enough to cause the chip to reset but it's big
enough to cause ILIM to fall in 128mA zone. We think this is why
the boards fail to boot from battery cutoff or no battery.
(Contrary to the vendor's explanation, it seems IADP/RESET pin
continusouly affects ILIM not only in the early chip power-up
period.)
BUG=b:35648317
BRANCH=none
TEST=Booted two Electro and two Snappy from 1) dead battery 2) no
battery 3) battery cutoff.
Change-Id: Ic675f1354b9ef222ceec8ce112b19713812d2752
Reviewed-on: https://chromium-review.googlesource.com/458676
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We are still building two images - for prod and dev fused H1 chips.
This requires different pairs of RO images and calls for using
different keys when signing RW images.
Each produced image is of 512K bytes in size, the ROs are paced at
offsets 0 and 0x40000, the RWs at offsets 0x4000 and 0x4000.
The signed ROs come from their respective source, their processing is
limited to converting into binary format and verifying that their key
signatures match image designation (prod vs dev).
The RWs binaries are derived from RW elf files which are the result of
running 'make BOARD=cr50'. The elves are converted into binary format
and signed, the bs script is used for that.
The bs script is modified to accept the destination file name from the
shell variable, to detect signing failures (resulting in zero sized
binaries), and to fix error reporting.
The new script create_released_image.sh expects exactly six command
line parameters:
<prod RO A>.hex <prod RO B>.hex <dev RO A>.hex <dev RO B>.hex \
<RW.elf> <RW_B.elf>
and generates two cr50 binary images.
The generated images are placed in the directory named cr50.r<ro
vers>.w<rw vers> (the versions are retrieved from the binaries using
usb_updater), and then placed in the tarball with the same base name.
This naming convention is imposed by the ebuild pulling in the tarball
from the binary component server (BCS).
On the successful completion the script prints out commands which can
be used to upload the new tarball to the BCS.
BRANCH=none
BUG=b:35587234
TEST=ran the script to generate the r0.0.10.w0.0.18 release, verified
that all components of both imagea are properly signed (are
bootable and the key signature matches the prod/dev convention).
Change-Id: I87be1d44a721c979bdeeabf986d717e3a382db45
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/439907
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
If we go to sleep with a lid close event, the trackpad is immediately
waking the system. Since we don't want to accidentally wake if the
trackpad got input while the lid is closed anyway this change will
disable trackpad wake when the lid is closed.
BUG=b:35587072
BRANCH=none
TEST=manual testing on Eve P1b:
1) enter suspend by closing lid and ensure it stays in suspend
2) enter suspend by idle, and then close the lid, and ensure
it stays suspended
Change-Id: Ied73dde61e99231f057504ca56c473432aa30e4b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/457865
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Remove unused wui sources of GPIO96/A0/A2/A4 since we don't
support them in 128/132-pins packages of npcx5mng. This CL also
removes wui source of GPO66 in case developer declares it as
GPIO_INT.
BRANCH=none
BUG=none
TEST=test gpio functionality on npcx_evb, reef and poppy.
Change-Id: I363813128d02be0fc642e82ca0b463971af22a90
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/458238
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
After running an update, we used to be dangerously close to
exhausting stack space, let's increase its size.
1 HOOKS 00000000 39.906350 476/488
BRANCH=none
BUG=b:35587171
TEST=Update FW using usb_updater2, 3 times in a row, without reboot,
no more panics.
Change-Id: Ia1559d7c4097b8d3179a6fa2f38bef126cb8055e
Reviewed-on: https://chromium-review.googlesource.com/458319
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
With the rest of support in place, this patch adds code which would
corrupt the headers received during firmware updates.
The VENDOR_CC_TURN_UPDATE_ON vendor command will be required to enable
the new images.
Care should be taken that other commands operating on the inactive
image header do not do anything with it before it was enabled, some
code is being added for that.
The minor RW version is being bumped up to 19 to clearly indicate that
the device is expecting the vendor command to enable the new image
(this is used by usb_updater when downloading the image without the -p
or -u command line options).
BRANCH=cr50
BUG=b:35580805
TEST=verified that the new image can be installed and started by the
new usb_updater.
- the inactive header after uploading with the -p option (the
image_size field's offset is 0x32c):
> md 0x84320 4
00084320: 00000000 00000000 80033800 00084000
rebooting the device does not start the new image.
- the inactive header after uploading without the -p option:
> md 0x84320 4
00084320: 00000000 00000000 00033800 00084000
the device running a DBG image reports the following in the end of
the image update:
[64.176780 FW update: done]
turn_update_on: rebooting in 100 ms
Change-Id: I4d763eb89c8b1a43a13697033201066779826e85
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457678
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the upcoming availability of the downloaded header corruption,
there needs to be a mechanism for usb_updater to restore the corrupted
header, so that the downloaded code can run right away.
This patch separates image download and reset functionality. Download
happens as before, and the UPGRADE_DONE PDU is sent immediately once
image transfer completes. This puts the receive state machine into the
idle state and allows to send other commands.
The reset function is different for the target supporting protocol
versions 5 and above. The only command version 5 recognizes is the
indirect reboot command (the UPGRADE_DONE PDU sent the second time in
a row). For protocol version 6 and above the reset could be immediate
or posted, and for targets running RW version 19 or above the command
to restore the corrupted header is required.
When running on the target the command to restore the corrupted header
would be generated by the AP firmware on the reboot.
BRANCH=cr50
BUG=b:35580805
TEST=with the next patch of the series applied observed the corrupted
header properly restored and the device rebooted.
Change-Id: If87c12fe8578cd6f1b4beed6d113471356f6b6c2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457677
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The upcoming move of the Cr50 firmware update to the background
requires postponing the activation of the newly uploaded Cr50 image to
a later point in time, when the AP is ready to switch to start using
the new Cr50 image.
The suggested way of achieving it is as follows: when downloading the
new image, the current Cr50 code modifies the header's 'image_size'
field, setting its top bit to 1. This both makes the size invalid and
guarantees that the new image would not verify on the following Cr50
restarts.
When the AP is ready to switch to running the new Cr50 image, it will
send a vendor command, which would trigger the currently running Cr50
image to restore the other image's size field. This vendor command
would also communicate the timeout for the Cr50 to wait before
rebooting, if there has been at least one header (ro or rw) restored.
Rebooting the Cr50 would trigger rebooting the AP, resulting in the
entire system running the updated firmware.
Response sent to the AP will indicate if there has been a header
restored and the reboot is indeed upcoming, this would allow the AP to
quiesce the state of the device to handle the reboot gracefully.
BRANCH=cr50
BUG=b:35580805
TEST=with the rest of the patches applied observed the system properly
after the new header version was restored.
Change-Id: Ia1edee67b6aa8f458810d5dc2931477cfaab1566
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There is no reason to reject the incoming USB packet if its
size equals the amount of space in the queue.
BRANCH=none
BUG=b:35587171
TEST=usb_updater2 works fine, even with 64-byte USB packets.
Change-Id: I2e54f1a758dd8a370dacdc8c2519bbd91e9cb4e5
Reviewed-on: https://chromium-review.googlesource.com/458042
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Rowan uses BMI160 as g-sensor and gyro sensor.
This change removes KX022 settings and adds BMI160 settings.
The LID_ANGLE config is also removed.
BRANCH=none
BUG=chrome-os-partner:62673
TEST=check the values of the sensors are correct:
run ectool motionsense while the machine is flat on the table, raised on
its left side and raised on its front edge. With these 3 measurements
the accel data along the Z, X and Y axis are showing + 1G.
Change-Id: I03c84f143bbfc3037fd5232398d15e9c2a511291
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/427566
Commit-Ready: Rong Chang <rongchang@chromium.org>
Tested-by: Rong Chang <rongchang@chromium.org>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
By generating the wui mapping table for GPIO pins which have interrupt
handler like CL 451366 did, we needn't browse all items in original
gpio_wui_table to find the MIWU info. It saves code space and improves
interrupt lantency.
BRANCH=none
BUG=none
TEST=Test gpio functionality on npcx_evb, reef and poppy.
Change-Id: I77e9ad439ecf6a501a7976fe5099dd309dba81ee
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/449514
For the upcoming header restore vendor command implementation there is
a need to allow rw access to the alternative RO area.
A static function for this is available in upgrade_fw.c, let's make it
available to other users.
BRANCH=cr50
BUG=b:35580805
TEST=verified that it is still possible to update the RO.
Change-Id: I879804ff180c5d00cf6860ce5669f2fe48731832
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457501
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
There are no early H1 chips left in circulation, all released chips
(starting with RW 0.0.10) support update protocol version 5.
This patch drops all technical debt associated with supporting earlier
protocol versions.
BRANCH=cr50
BUG=b:35580805
TEST=downgraded an H1 test board to ro 0.0.8 rw 0.0.9. Updated it to
the latest image (ro 0.0.10 rw 0.0.18).
Change-Id: I28c9b0c597122c7aa602a88fb56f9c7bf04b9984
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457500
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
tigertail allows muxing a usb-c port onto two different
passthough targets. This allows for automated switching
between USB host and device without DUT or endpoint knowledge.
tigertail also routes SBU lines to stm32 UART, and has INAs on
VBUS and VCONN to measure power.
BUG=b:35849284
BRANCH=None
TEST=Muxing power, muxing USB, uart works, INAs work.
Change-Id: I5bf2ba038aa78e59352ad99cd71efb0f0d0fbec9
Reviewed-on: https://chromium-review.googlesource.com/438677
Commit-Ready: Nick Sanders <nsanders@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
In order to enable toggling on/off of LTE based on chipset power state
transitions, define WIRELESS_GPIO_WWAN that would allow the common
wireless component to take care of the gpio toggling.
BUG=b:36447195
BRANCH=None
TEST=Verified that PP3300_A drops down from 0.9V to 0.63V when
apshutdown is done on EC console and system transitions to fake G3.
Change-Id: Id46bcbdffde06e4929910b6ab87a6d9a96d18a23
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/457402
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jerry Parson <jwp@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
When invoking ectool fan commands on older ECs not supporting
EC_CMD_GET_FEATURES, the tool is choking on the lack of the command at
the beginning of get_num_fans() and not going further.
The regression was introduced by
https://chromium-review.googlesource.com/c/359069/, let's go back to the old
behavior for machines without feature bits and skip the
EC_FEATURE_PWM_FAN check.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35575890
TEST=on Buddy, run 'ectool pwmgetnumfans' and 'ectool pwmgetfanrpm all'
and get results.
Change-Id: Ie9255d4afc9fa95a55807c310e9593a28c2aadc1
Reviewed-on: https://chromium-review.googlesource.com/456598
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
In order to support waking from Deep S3 the trackpad interrupt
is routed to the EC.
The EC needs to enable this interrupt when going into S3, and
disable it otherwise.
It also needs to filter events and only wake the system when it
is not in tablet mode.
This is accomplished with the following rules:
1) Enable trackpad wake in S0->S3 transition, if !tablet_mode
2) Disable trackpad wake in S3->S5 transition
3) Disable trackpad wake in S3->S0 transition
4) Disable trackpad wake when entering tablet mode in S3
5) Enable trackpad wake when lid angle is <180 degrees and in S3
And finally a check in the trackpad interrupt itself to ensure that
it only sends the wake event if not in tablet mode.
The function to enable or disable trackpad wake uses a static variable
to keep track of the enable state because when enabling the GPIO for
wake it first clears pending events and if multiple transitions are
happening (suspending, plus lid angle rotation) this can get called
multiple times in quick succession.
Currently a placeholder KEY_PRESSED event is used to wake the AP
since we do not have device specific events. Fixing this behavior
is tracked in b/36024430.
BUG=b:35587072
BRANCH=none
TEST=manual testing on eve P1b:
1) ensure that trackpad wake in clamshell mode works
2) ensure that trackpad wake in tablet mode does not waork
3) ensure that if in S3 during transition to or from tablet
mode the wake event is enabled appropriately
Change-Id: Ib2020b5010bdde396a3b05243894431b67edb503
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://chromium-review.googlesource.com/450954
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
PS8751 does not restore all register contents when resuming
from low power mode. This change makes tcpm call board_init
when it stops auto-toggling so that register contents can be
restored.
BUG=b:35585399
BRACH=none
TEST=On Snappy, the board_init funciton is called every time a device
is plugged in and register contents are restored.
Change-Id: I50c51334f43c02e3c4d8453e1e966bf6eb3ce769
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/454139
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Let's split the usb headers in 3 different parts, instead of having
usb_descriptor.h pull in usb_hw.h and usb_api.h.
- usb_api.h: EC functions related to usb (e.g. connect/disconnect)
- usb_descriptor.h: common USB names and structures
- usb_hw.h: Functions required for interactive with EC's USB HW
BRANCH=none
BUG=b:35587171
TEST=make buildall -j
Change-Id: I37ead61e3be5e7ae464f1c9137cf02eaab0ff92e
Reviewed-on: https://chromium-review.googlesource.com/454861
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Increasing key length from 2048 bits to 3072 bits provides more
security, at the cost of about 2.25x the amount of time being
spent in verification (roughly 100ms instead of 45ms).
CQ-DEPEND=CL:449060
BRANCH=none
BUG=b:35582031
TEST=Flash hammer, verification succeeds.
Change-Id: I2ac7e87941c847bb4e9bd376034e6539988d1743
Reviewed-on: https://chromium-review.googlesource.com/449023
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
If the charging current is less than the BD9995X's minimum charging current
it is overwritten to BD9995X's minimum charging current. However in idle
mode we write the charging current which is known to the charger during
that time, which can be less than the BD9995X's charging current. Hence,
do not overwrite the charging current in idle mode.
BUG=b:35984679
BRANCH=none
TEST=Manually tested on Electro. In idle mode charge current is 0mA.
Change-Id: I2e605b63c8519383c6a62d76718bc52660e7270e
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/453999
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The anx74xx tcpm driver for the usb_mux_set() function is always
connecting the DP aux lines to the SBU signals regardless of whether
the bit flag MUX_DP_ENABLED was set or not. For CCD opertation the sbu
lines are used to establish a USB connection to H1. This means that if
a PD port ever attaches to a sink debug accessory, usb_mux_set would
result in interrupting the USB connection being used for CCD.
In addition, the anx74xx_tcpm_mux_exit() function had a bug where the
value read from ANALOG_CTRL_5 was being masked by 0x09 and then
written to ANALOG_CTRL_2.
Added functions anx74xx_tcpm_mux_enter_safe_mode() and
anx74xx_tcpm_mux_exit_safe_mode() so that writes to the 3 CTRL
registers that are used to configure ALT_DP mode can be easily
bookended.
BUG=b:36007652
BRANCH=reef
TEST=Connected servo_v4 to port 0 of electro, verified that H1 console
access worked. Then initiated a data role swap so that port 0 on
electro was in DFP mode and the H1 console stayed connected.
- Tested with dingdong that could connect to a 4k monitor.
- Tested with USB3 flash drive.
- Tested Anker USBC -> USBA hub
Change-Id: I2d045134fbdd21b6b492bbeabc85ab23aef73b9a
Signed-off-by: Scott <scollyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/451837
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: S Wang <swang@analogix.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Some people love to address the EC device nodes by number with ectool,
add the special offset for the FP MCU (e.g. '--dev=8').
Addressing it by name already works (e.g. '--name=cros_fp').
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35648259
TEST=on Eve, execute 'ectool --dev=8 version'
and see a similar result to 'ectool --name=cros_fp version'
e.g. "RO version: eve_fp_v1.1.6177-945b19f+ [...]"
Change-Id: Ic08e3b7a3ae31b7e1b73bccc8375badf3284b49c
Reviewed-on: https://chromium-review.googlesource.com/453179
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
As advised by Daisuke makes the new API slightly better:
- remove the useless rxlen assignment.
- keep the normal asynchronous behavior of the function by skipping the
last dma wait.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:35648259
TEST=on Eve, use the FP sensor with the passthru.
Change-Id: Iedb8e77cb1af58c273ab5ae6f0a670ce93dfde5a
Reviewed-on: https://chromium-review.googlesource.com/454699
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Master chip/g FW still needs to support deprecated RO, so re-add support
for the old version_struct. This CL can be reverted once we no longer
need to support deprecated RO on master.
BUG=chromium:698881,chromium:698882
TEST=Flash old FW (f51fdf2) to RW_B slot and updated FW to RW_A. Verify
cr50 boots into RW_A, and "version" on the console prints RW_B version,
not "Error".
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3c255afcd12da5694ca128960de8d2abe41686dc
Reviewed-on: https://chromium-review.googlesource.com/450860
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Image used size is now part of the image_data struct present in all
images at a fixed offset, so use it rather than scanning from the end of
the image.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that system_get_image_used() returns
the same value as the old implementation, for both RO and RW images.
BRANCH=None
Change-Id: I35f0aa87f5ab1371dbd8b132f22b9d0044358223
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450859
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Store our image size (known at build time) in our version struct (now
renamed to image_data). This will allow us to more efficiently determine
the size of an image in a follow-up CL.
Note that compatibility is broken for old ROs that do not include this
CL.
BUG=chromium:577915
TEST=Verify on kevin + lars + lars_pd that stored image size matches
output of system_get_image_used() for both RO and RW images.
BRANCH=None
Change-Id: I7b8dc3ac8cf2df3184d0701a0e0ec8032de8d81b
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/450858
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
